EPF8820AQC208-3 - FLEX 8000 FPGA, 672 LEs, 208-PQFP | Altera
MPN: EPF8820AQC208-3 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $24.9 | $2,490.00 |
| 250 | $21.4 | $5,350.00 |
| 500 | $18.95 | $9,475.00 |
Drop-in alternatives for EPF8820AQC208-3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPF8820AQC208-2N
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View Datasheet βEPF8820AQC160-4
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View Datasheet βEPF8820AQC160-3
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View Datasheet βEPF8820AQC160-2
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View Datasheet βEPF81188AQC208-3
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View Datasheet βEPF8820AQC208-3 Maximum Ratings & Electrical Characteristics
| Family | FLEX 8000 |
| Device Type | FPGA (Field Programmable Gate Array) |
| Logic Elements (LEs) | 672 |
| Usable Gates | 8,000 |
| Logic Array Blocks (LABs) | 84 |
| User I/Os | 152 |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | 0 C to 70 C (Commercial) |
| Package | 208-pin PQFP (Plastic Quad Flat Pack), 28 x 28 mm |
| Mounting Type | Surface Mount (Gull-Wing) |
| Process Technology | CMOS SRAM |
| Configuration Method | Serial or parallel EPROM (EPC1, EPC1064, EPC1213, EPC1441), system controller |
| Boundary Scan | JTAG IEEE 1149.1 |
| In-Circuit Reconfigurability | Yes (ICR) |
| Speed Grade | -3 |
| Lifecycle Status | Obsolete (EOL) |
EPF8820AQC208-3 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank A) |
| Pin 2 | I/O β User I/O pin (bank A) |
| Pin 3 | I/O β User I/O pin (bank A) |
| Pin 4 | I/O β User I/O pin (bank A) |
| Pin 5 | I/O β User I/O pin (bank A) |
| Pin 6 | I/O β User I/O pin (bank A) |
| Pin 7 | I/O β User I/O pin (bank A) |
| Pin 8 | I/O β User I/O pin (bank A) |
| Pin 9 | I/O β User I/O pin (bank A) |
| Pin 10 | I/O β User I/O pin (bank A) |
| Pin 11 | I/O β User I/O pin (bank A) |
| Pin 12 | I/O β User I/O pin (bank A) |
| Pin 13 | I/O β User I/O pin (bank A) |
| Pin 14 | I/O β User I/O pin (bank A) |
| Pin 15 | I/O β User I/O pin (bank A) |
| Pin 16 | VCC β 5V supply |
| Pin 17 | GND β Ground |
| Pin 18 | I/O β User I/O pin (bank B) |
| Pin 19 | I/O β User I/O pin (bank B) |
| Pin 20 | I/O β User I/O pin (bank B) |
| Pin 21 | I/O β User I/O pin (bank B) |
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| Pin 30 | I/O β User I/O pin (bank B) |
| Pin 31 | I/O β User I/O pin (bank B) |
| Pin 32 | I/O β User I/O pin (bank B) |
| Pin 33 | VCC β 5V supply |
| Pin 34 | GND β Ground |
| Pin 35 | I/O β User I/O pin (bank C) |
| Pin 36 | I/O β User I/O pin (bank C) |
| Pin 37 | I/O β User I/O pin (bank C) |
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| Pin 47 | I/O β User I/O pin (bank C) |
| Pin 48 | I/O β User I/O pin (bank C) |
| Pin 49 | I/O β User I/O pin (bank C) |
| Pin 50 | VCC β 5V supply |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin (bank D) |
| Pin 53 | I/O β User I/O pin (bank D) |
| Pin 54 | I/O β User I/O pin (bank D) |
| Pin 55 | I/O β User I/O pin (bank D) |
| Pin 56 | I/O β User I/O pin (bank D) |
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| Pin 60 | I/O β User I/O pin (bank D) |
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| Pin 63 | I/O β User I/O pin (bank D) |
| Pin 64 | I/O β User I/O pin (bank D) |
| Pin 65 | I/O β User I/O pin (bank D) |
| Pin 66 | I/O β User I/O pin (bank D) |
| Pin 67 | VCC β 5V supply |
| Pin 68 | GND β Ground |
| Pin 69 | I/O β User I/O pin (bank E) |
| Pin 70 | I/O β User I/O pin (bank E) |
| Pin 71 | I/O β User I/O pin (bank E) |
| Pin 72 | I/O β User I/O pin (bank E) |
| Pin 73 | I/O β User I/O pin (bank E) |
| Pin 74 | I/O β User I/O pin (bank E) |
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| Pin 81 | I/O β User I/O pin (bank E) |
| Pin 82 | I/O β User I/O pin (bank E) |
| Pin 83 | I/O β User I/O pin (bank E) |
| Pin 84 | VCC β 5V supply |
| Pin 85 | GND β Ground |
| Pin 86 | I/O β User I/O pin (bank F) |
| Pin 87 | I/O β User I/O pin (bank F) |
| Pin 88 | I/O β User I/O pin (bank F) |
| Pin 89 | I/O β User I/O pin (bank F) |
| Pin 90 | I/O β User I/O pin (bank F) |
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| Pin 94 | I/O β User I/O pin (bank F) |
| Pin 95 | I/O β User I/O pin (bank F) |
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| Pin 98 | I/O β User I/O pin (bank F) |
| Pin 99 | I/O β User I/O pin (bank F) |
| Pin 100 | I/O β User I/O pin (bank F) |
| Pin 101 | VCC β 5V supply |
| Pin 102 | GND β Ground |
| Pin 103 | I/O β User I/O pin (bank G) |
| Pin 104 | I/O β User I/O pin (bank G) |
| Pin 105 | I/O β User I/O pin (bank G) |
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| Pin 115 | I/O β User I/O pin (bank G) |
| Pin 116 | I/O β User I/O pin (bank G) |
| Pin 117 | I/O β User I/O pin (bank G) |
| Pin 118 | VCC β 5V supply |
| Pin 119 | GND β Ground |
| Pin 120 | I/O β User I/O pin (bank H) |
| Pin 121 | I/O β User I/O pin (bank H) |
| Pin 122 | I/O β User I/O pin (bank H) |
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| Pin 132 | I/O β User I/O pin (bank H) |
| Pin 133 | I/O β User I/O pin (bank H) |
| Pin 134 | I/O β User I/O pin (bank H) |
| Pin 135 | VCC β 5V supply |
| Pin 136 | GND β Ground |
| Pin 137 | I/O β User I/O pin (bank A) |
| Pin 138 | I/O β User I/O pin (bank A) |
| Pin 139 | I/O β User I/O pin (bank A) |
| Pin 140 | I/O β User I/O pin (bank A) |
| Pin 141 | I/O β User I/O pin (bank A) |
| Pin 142 | I/O β User I/O pin (bank A) |
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| Pin 149 | I/O β User I/O pin (bank A) |
| Pin 150 | I/O β User I/O pin (bank A) |
| Pin 151 | I/O β User I/O pin (bank A) |
| Pin 152 | VCC β 5V supply |
| Pin 153 | GND β Ground |
| Pin 154 | I/O β User I/O pin (bank B) |
| Pin 155 | I/O β User I/O pin (bank B) |
| Pin 156 | I/O β User I/O pin (bank B) |
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| Pin 165 | I/O β User I/O pin (bank B) |
| Pin 166 | I/O β User I/O pin (bank B) |
| Pin 167 | I/O β User I/O pin (bank B) |
| Pin 168 | I/O β User I/O pin (bank B) |
| Pin 169 | VCC β 5V supply |
| Pin 170 | GND β Ground |
| Pin 171 | I/O β User I/O pin (bank C) |
| Pin 172 | I/O β User I/O pin (bank C) |
| Pin 173 | I/O β User I/O pin (bank C) |
| Pin 174 | I/O β User I/O pin (bank C) |
| Pin 175 | I/O β User I/O pin (bank C) |
| Pin 176 | I/O β User I/O pin (bank C) |
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| Pin 178 | I/O β User I/O pin (bank C) |
| Pin 179 | I/O β User I/O pin (bank C) |
| Pin 180 | I/O β User I/O pin (bank C) |
| Pin 181 | I/O β User I/O pin (bank C) |
| Pin 182 | I/O β User I/O pin (bank C) |
| Pin 183 | I/O β User I/O pin (bank C) |
| Pin 184 | I/O β User I/O pin (bank C) |
| Pin 185 | I/O β User I/O pin (bank C) |
| Pin 186 | VCC β 5V supply |
| Pin 187 | GND β Ground |
| Pin 188 | I/O β User I/O pin (bank D) |
| Pin 189 | I/O β User I/O pin (bank D) |
| Pin 190 | I/O β User I/O pin (bank D) |
| Pin 191 | I/O β User I/O pin (bank D) |
| Pin 192 | I/O β User I/O pin (bank D) |
| Pin 193 | I/O β User I/O pin (bank D) |
| Pin 194 | I/O β User I/O pin (bank D) |
| Pin 195 | I/O β User I/O pin (bank D) |
| Pin 196 | I/O β User I/O pin (bank D) |
| Pin 197 | I/O β User I/O pin (bank D) |
| Pin 198 | I/O β User I/O pin (bank D) |
| Pin 199 | I/O β User I/O pin (bank D) |
| Pin 200 | I/O β User I/O pin (bank D) |
| Pin 201 | I/O β User I/O pin (bank D) |
| Pin 202 | I/O β User I/O pin (bank D) |
| Pin 203 | VCC β 5V supply |
| Pin 204 | GND β Ground |
| Pin 205 | nCONFIG β Configuration control (active low) |
| Pin 206 | nSTATUS β Configuration status (active low) |
| Pin 207 | CONF_DONE β Configuration done indicator |
| Pin 208 | TCK β JTAG test clock (IEEE 1149.1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8820AQC208-3 is suitable for 6 applications: Legacy Telecom Glue Logic, Industrial Control Front-End, Custom Peripheral Bus Bridge, Hardware State-Machine Controller, DSP Pre/Post-Processing Accelerator, Test & Measurement Fixture Logic.
Legacy Telecom Glue Logic
The EPF8820AQC208-3 fits telecom glue-logic designs thanks to its 152 5V-tolerant I/Os that connect directly to legacy TTL/CMOS bus peripherals without level shifters. With 672 LEs across 84 LABs it bridges E1/T1 framers, HDLC controllers, and time-slot interchangers at line rates up to tens of MHz. Unlike smaller CPLDs, the FastTrack interconnect delivers uniform tpd across the die, simplifying timing closure when fanning out to multiple bus segments. A typical circuit places the EPF8820AQC208-3 between a framer IC and a backplane transceiver, with JTAG access for boundary-scan production test.
Recommended
Industrial Control Front-End
The EPF8820AQC208-3 is widely deployed in industrial PLC and motion-control front-ends because its 5 V I/O tolerance mates directly with 24 V isolated digital inputs and 5 V sensor buses via external buffers. The 672-LE capacity is sufficient for PWM generation, encoder decoding (incremental and SSI), and custom deterministic state machines. The commercial 0C to 70C operating range suits cabinet-mounted controllers, while JTAG boundary-scan accelerates in-circuit test on densely populated backplanes. Designers benefit from FastTrack predictable routing when fanning out 100+ control signals across multiple connector banks.
Recommended
Custom Peripheral Bus Bridge
With 152 user I/Os and 8,000 usable gates, the EPF8820AQC208-3 can implement multi-master bus bridges between legacy ISA, PC/104, and proprietary peripheral buses. Its SRAM-based fabric lets designers iterate bridge protocols during system bring-up without mask charges, and JTAG enables live reconfiguration of bus protocol state machines during field debug. The 208-pin PQFP footprint offers ample 5V-tolerant I/O for both address/data multiplexing and interrupt/control signal replication. Compared to a discrete 74-series implementation, the EPF8820AQC208-3 reduces PCB area by 5-10x and consolidates timing-critical glue into one timing-closed device.
Recommended
Hardware State-Machine Controller
The EPF8820AQC208-3 excels at implementing complex, multi-state control sequencers that would otherwise require dozens of PAL/GAL devices. With 84 LABs it can hold 50+ parallel finite state machines plus their interlock logic, and its SRAM configuration enables late-stage firmware changes. The 5V I/Os interface directly to opto-isolated industrial outputs, while the JTAG TAP controller provides a window into internal states during integration testing. Designers typically use MAX+PLUS II to enter state machines as AHDL/Verilog and synthesize into the device. Compared to a microcontroller, the FPGA delivers deterministic single-clock-cycle state transitions without RTOS overhead.
Recommended
DSP Pre/Post-Processing Accelerator
In cost-sensitive DSP subsystems, the EPF8820AQC208-3 acts as a hardware accelerator for FIR filtering, data formatting, and protocol encapsulation offloaded from a host DSP. Its 672 LEs support 16-tap FIR filters or parallel CRC engines running at full 5V I/O speeds, and FastTrack interconnect ensures uniform sample-to-sample timing. Designers often pair the FPGA with a serial EEPROM configuration device (EPC1 or EPC1064) for fast power-up boot, and route JTAG to a header for emulator access. Compared to a DSP software implementation, the FPGA variant typically delivers 3-10x throughput per MHz while freeing the host DSP for control tasks.
Recommended
Test & Measurement Fixture Logic
The EPF8820AQC208-3 is a strong fit for ATE pin-card and bed-of-nails fixture logic, where 152 5V I/Os connect to UUT pins through relays and the FPGA orchestrates stimulus/response sequences. Its SRAM fabric lets test engineers swap personality bitstreams for different UUTs in seconds, and JTAG provides full visibility into FPGA states during fixture bring-up. The commercial temperature range suits bench fixtures, while the 208-PQFP is easy to socket or rework. Designers appreciate the deterministic FastTrack delays when sequencing parallel test vectors to multiple UUT pins at once.
Recommended
Recommended Products Summary
Engineering reference data for EPF8820AQC208-3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8820AQC208-2N | EPF8820AQC208-2 | EPF8820AQC160-4 | EPF8820AQC160-3 | EPF8820AQC160-2 | EPF81188AQC208-3 |
|---|---|---|---|---|---|---|---|
| Package | 208-pin PQFP (28x28 mm) | 208-pin PQFP - same | 208-pin PQFP - same | 160-pin PQFP - same family | 160-pin PQFP - same family | 160-pin PQFP - same family | 208-pin PQFP - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Family | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 |
| Logic Elements | 672 | 672 | 672 | 672 | 672 | 672 | 1,188 |
| Speed Grade | -3 | -2 (faster) | -2 (faster) | -4 (fastest) | -3 (same) | -2 (faster) | -3 (same) |
| Usable Gates | 8,000 | 8,000 | 8,000 | 8,000 | 8,000 | 8,000 | 12,000 |
| User I/Os | 152 | 152 | 152 | 120 | 120 | 120 | 171 |
| Supply Voltage | 5 V (4.75 V to 5.25 V) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) |
Key Differentiators
- Higher logic density with same 208-PQFP footprint (vs EPF81188AQC208-3)
- Faster speed grade variant available (vs EPF8820AQC208-2N)
- Reduced pin-count footprint option (vs EPF8820AQC160-3)
Design Notes
The EPF8820AQC208-3 requires a clean 5 V supply (4.75 V to 5.25 V) with adequate decoupling. Place one 0.1 uF ceramic capacitor per VCC pin pair and one bulk 22-47 uF tantalum or aluminum polymer capacitor near each VCC bank. SRAM-based FPGAs draw surge currents during configuration; the bulk capacitor prevents VCC droop that can cause configuration failures. Estimated: at 25 MHz toggle activity on 100 I/Os, ICCINT is typically 150-250 mA; size the regulator for at least 1.5x this value plus headroom for inrush.
Use a 4-layer PCB with dedicated VCC and GND planes for the EPF8820AQC208-3. Route all 152 user I/Os on short, matched traces and avoid 90-degree bends to reduce reflections on 5V TTL-level signals. Place configuration EPROM (EPC1/EPC1064/EPC1213/EPC1441) within 50 mm of the FPGA to keep configuration traces short. Expose JTAG pins (TCK, TMS, TDI, TDO, nCONFIG, nSTATUS, CONF_DONE) to a 0.1-inch header or 10-pin JTAG ribbon for debug and production programming.
Because the EPF8820AQC208-3 is marked Obsolete/EOL, do not use it for new production designs without a written last-time-buy commitment from Altera/Intel. Modern designs should target Cyclone IV, MAX II, or MAX V as functionally equivalent replacements, but note that none of these are pin-compatible - a PCB redesign is required. For legacy support, qualify a single broker-sourced lot and verify authenticity before use.
The 208-pin PQFP package has relatively long lead inductance (~5-7 nH) that can create ground bounce on heavily-loaded outputs. Use series damping resistors (22-33 ohm) on outputs driving backplane connectors, and avoid simultaneous switching of more than 16 outputs per bank. For clock distribution, dedicate one global FastTrack buffer per clock domain to minimize skew.
Compliance Information
The EPF8820AQC208-3 is an obsolete Altera FLEX 8000 device; compliance documentation is not explicitly listed in current distributor data. The PQFP-208 package is typically Pb-free for legacy Altera commercial parts, but RoHS/REACH status is not confirmed by current datasheets.
