Altera

EPM9320ARC208-10N - 320-Macrocell MAX 9000 CPLD, 10ns | Altera

Name: EPM9320ARC208-10N - 320-Macrocell MAX 9000 CPLD, 10ns | Altera
Brand: Altera
SKU: EPM9320ARC208-10N

MPN: EPM9320ARC208-10N ✗ Akhir Hidup

5 V Vdss 208-pin RQFP (BFQFP with exposed pad) Package 144.9 MHz Speed Non-volatile EEPROM Memory

Ajukan Diskon

MOQ: 1 |

Lihat Datasheet (PDF) Lihat Alternatif

Kuantitas

EPM9320ARC208-10N Ringkasan

The Altera EPM9320ARC208-10N is a 320-macrocell, 6,000-gate CMOS Complex Programmable Logic Device (CPLD) from the MAX 9000 family, packaged in a 208-pin RQFP (Plastic Quad Flat Pack) with exposed pad. It provides 10 ns pin-to-pin logic delay, 144.9 MHz maximum operating frequency, and operates from a 5 V supply, integrating high-density system-level logic in a single non-volatile device.

What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL/GAL-style macrocell arrays with a central programmable interconnect matrix. In the broader taxonomy, a CPLD sits between simple SPLDs (PALs, GALs, 22V10s) and FPGAs: CPLDs offer deterministic timing, instant-on non-volatile configuration (EEPROM-based in MAX 9000), predictable I/O pin-to-pin delays, and high drive strength, while FPGAs provide higher logic density and richer register features at the cost of volatile configuration and longer propagation delays. CPLDs are typically chosen for glue logic, bus interface bridging, state-machine controllers, and power-up instant-on decoding.

Key features of the EPM9320ARC208-10N include 320 macrocells distributed across 16 Logic Array Blocks (LABs), 12 dedicated input pins, and 168 user I/O pins. It supports in-system programmability via IEEE Std. 1149.1 JTAG, includes an open-drain JTAG pin option, and provides 5 V tolerant I/O. The 'ARC' suffix indicates the 208-pin RQFP package; the '10' speed grade gives the 10 ns tPD timing; and the trailing 'N' indicates a lead-free / RoHS-compliant finish.

Architecturally, the MAX 9000 device uses an enhanced EPLD architecture with multiple LABs interconnected by the Programmable Interconnect Array (PIA). Each LAB contains 16 macrocells, each with a programmable AND/OR array, configurable flip-flop, and I/O architecture. The non-volatile EEPROM configuration cell provides instant-on behavior at power-up with no external configuration PROM required, distinguishing MAX 9000 from SRAM-based FPGAs and giving it deterministic boot for critical control paths.

Typical applications include high-speed bus decoding and address mapping, peripheral interfacing and glue logic in microprocessor systems, state-machine control, fast datapath multiplexing, JTAG-driven board-level test integration, and legacy 5 V system logic consolidation. Designers select this part when they need fast deterministic pin-to-pin delays combined with non-volatile instant-on configuration.

When designing with the EPM9320ARC208-10N, ensure VCC rises monotonically during power-up, place decoupling capacitors (0.1 uF plus bulk) close to every VCC pin, and respect the input undershoot/overshoot limits (transitions may undershoot to -2.0 V or overshoot to 7.0 V only for periods under 20 ns at no-load). Use the JTAG chain to program in-system; the open-drain JTAG pin requires an external pull-up.

This page consolidates distributor pricing, same-package drop-in speed-grade variants, and design notes not found in the original datasheet.

Alternatif penggantian untuk EPM9320ARC208-10N — paket yang sama, pin-pada-pin kompatibel. Bagian paket yang berbeda memerlukan kerja ulang PCB diabaikan.

Variasi di dalam seri ini

Model-series yang sama yang kompatibel dengan penggantian EPM9320ARC208-10N (sama faktor bentuk dan footprint) — berbeda di dalam Package, Operating Temperature, RoHS Status, Supply Voltage, In-System Programmability.

EPM9320ARC208-10

Altera

Package: RQFP-208 (Power Quad Flat Pack)

Supply Voltage: 5.0 V