FPGA & CPLD
製品 (6666)
EPM7128SQC100-10N - MAX 7000 128-Macro-Cell CPLD, 10ns | Altera
The Altera EPM7128SQC100-10N is a high-density, high-performance CMOS CPLD (Complex Programmable Logic Device) from the MAX 7000 family, featuring 128 macro cells, 2,500 usable gates, and a 100-pin PQFP (Plastic Quad Flat Pack) package with 10ns pin-to-pin logic delay and 100 MHz internal operating frequency at 5V supply. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architecture of a PAL (Programmable Array Logic) with the density of an FPGA. CPLDs occupy a position in the programmable logic hierarchy between simple PLDs and FPGAs: PLD -> CPLD -> FPGA -> programmable logic -> semiconductor. They are valued for their deterministic timing, instant-on non-volatile configuration (EEPROM-based in the MAX 7000 family), and low power consumption, making them ideal for glue logic, bus interfacing, and state-machine implementation in industrial, telecommunications, and embedded systems. Key features of the EPM7128SQC100-10N include 128 macro cells organized as 8 Logic Array Blocks (LABs) of 16 macro cells each, 84 user I/O pins, 5V core supply with 3.3V or 5V I/O compatibility via MultiVolt interface, in-system programmability (ISP) via the JTAG-compliant 4-pin IEEE Std. 1149.1 interface, and 10ns combinatorial propagation delay (tPD). The MAX 7000 architecture is built on Altera's second-generation MAX architecture with EEPROM configuration memory. From a technical depth perspective, the MAX 7000 family uses a programmable interconnect array (PIA) that routes signals between LABs without contention, and each macro cell contains a programmable AND/OR array, a product-term select matrix, and a configurable flip-flop. The device supports JTAG boundary-scan testing per IEEE 1149.1 and includes built-in test logic for board-level verification. The 100-pin PQFP package has a body size of approximately 20 x 14 mm with 0.65 mm pitch gull-wing leads. Typical applications include industrial control glue logic, address decoding and bus interfacing in embedded systems, state machines for motor control, peripheral interfacing in telecommunications equipment, and legacy 5V system designs where FPGAs are overkill. The wide operating voltage tolerance (4.75V to 5.25V) also supports -40C to +85C industrial temperature range operation. When designing with this device, ensure the JTAG chain is properly terminated to avoid programming failures, and use the Quartus Prime or MAX+PLUS II software for design entry, synthesis, and programming file generation. Power sequencing should maintain VCC within specification before JTAG operations to prevent partial configuration. This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
The Altera (now Intel) EPM7128SQC100-15 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000 family, providing 128 macrocells, 84 user I/Os, and a 15 ns pin-to-pin logic delay in a 100-pin PQFP package. It operates from a 5 V supply (5% tolerance) and supports in-system programmability through the IEEE Std. 1149.1 (JTAG) interface and a built-in Altera MasterBlaster or ByteBlaster programming path. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell arrays on a single die with a global interconnect fabric. The MAX 7000 family is Altera's second-generation EEPROM-based CPLD architecture, positioned between simple PLDs and FPGAs in the programmable logic hierarchy: PLD -> CPLD -> FPGA -> SoC FPGA. MAX 7000 parts retain configuration in on-chip EEPROM, so they boot instantly at power-up without an external configuration PROM - an advantage over SRAM-based FPGAs in deterministic-startup applications. Key features of the EPM7128SQC100-15 include 128 macrocells organized into 4 Logic Array Blocks (LABs), a 2,500-gate typical density, 84 user I/O pins, programmable power management with macrocell-level slew-rate control, and a 15 ns tPD (worst-case pin-to-pin delay) suitable for 66 MHz operation. The device also provides 4 dedicated inputs, 6 to 10 product terms per macrocell, and a JTAG boundary-scan test interface compliant with IEEE 1149.1. The architecture uses Altera's classic MAX (Multiple Array matriX) interconnect, with each LAB containing 16 macrocells feeding a Programmable Interconnect Array (PIA). This structure delivers fast, predictable combinational and registered logic delays that are independent of routing density - a key reason MAX 7000 CPLDs remain in long-life programs where deterministic timing matters more than raw density. Typical applications include bus-interface glue logic, peripheral decoders and address mapping, state-machine control in industrial automation, board-level signal conditioning in telecom backplanes, and pin-compatible upgrades for legacy 5 V TTL/CMOS designs. The 5 V tolerance and PQFP-100 footprint also make it a common choice for maintenance of installed equipment in factory automation and aerospace ground systems. When designing with this part, plan for an external 5 V regulator with at least 200 mA headroom and follow Altera's JTAG chain layout guidelines (TCK pull-down, TMS/TDI pull-ups) to avoid programming failures. Note that the EPM7128SQC100-15 is a mature / legacy product; verify lifecycle status before new designs. This page synthesizes distributor pricing, drop-in same-package alternatives from the MAX 7000 / MAX 7000A families, and practical design notes not found in the manufacturer datasheet itself.
EPM7128SQC100-6 - 128-Macrocell MAX 7000S CPLD, 5V | Intel
The Intel (formerly Altera) EPM7128SQC100-6 is a 128-macrocell member of the classic MAX 7000S family of complex programmable logic devices (CPLDs), fabricated on a 5V CMOS EEPROM process and packaged in a 100-pin PQFP (SQC). The device integrates 2,500 usable gates and 128 macrocells with 84 user I/O pins, providing non-volatile, instant-on logic with 6 ns pin-to-pin propagation delay and an internal frequency up to 147.1 MHz. It supports in-system programmability (ISP) via the IEEE 1149.1 JTAG interface and 5V tolerant I/Os, making it suitable for legacy glue-logic, bus-interface, and state-machine replacement designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single chip, connected through a programmable interconnect matrix (PIA). CPLDs sit between simple PLDs and FPGAs in the programmable logic taxonomy: PLD -> CPLD -> FPGA -> programmable logic -> semiconductor. Unlike SRAM-based FPGAs, CPLDs retain their configuration without external memory and offer deterministic, sub-10 ns timing that engineers can rely on for asynchronous glue logic, decoder replacement, and bus-interfacing tasks. The MAX 7000S architecture implements each macrocell with a programmable product-term array, a programmable register (D/T/JK/SR flip-flop), and a tri-state output buffer. With 128 macrocells the device delivers up to 6.25 ns combinational propagation and 147.1 MHz internal operation; the -6 speed grade specifies a maximum 6 ns pin-to-pin delay. MultiVolt I/O supports interfacing with 3.3V and 5V mixed-voltage systems. ISP via JTAG allows field upgrades, while the 100-pin PQFP provides ample I/O density for bus bridges, peripheral controllers, and industrial glue logic. Typical applications for the EPM7128SQC100-6 include PCI/local-bus interface bridges, peripheral glue logic in 5V industrial systems, JTAG-controlled scan and boundary-test fixtures, address decoding and interrupt management in embedded motherboards, and legacy designs migrating discrete 74LS/74HC logic into one programmable device. Its instant-on, deterministic timing and 5V tolerance make it a common choice in industrial and telecom platforms where 3.3V-only FPGAs are not suitable. When designing with the EPM7128SQC100-6, ensure 5V-tolerant I/O banks are configured to match downstream logic levels; use a 100-pin PQFP land pattern with sufficient copper area for thermal dissipation; and program via Quartus II or the legacy MAX+PLUS II toolchain using the JTAG chain defined in the datasheet. Always respect the device's 5V VCCIO absolute maximum and decouple VCC pins with 0.1 uF ceramic capacitors close to the package. This page synthesizes distributor stock and pricing for EPM7128SQC100-6, MAX 7000S family drop-in speed-grade and package alternatives (EPM7128SQC100-7, -10, -15, -10N, -10F) that share the same 100-pin PQFP footprint, and practical design notes not consolidated in the manufacturer datasheet.
EPM7128SQC100-7 - 128-Macro 5V CPLD, 7.5ns, 100-Pin PQFP | Altera (Intel)
The Altera (now Intel) EPM7128SQC100-7 is a high-density, 5V, in-system programmable Complex Programmable Logic Device (CPLD) from the MAX 7000S family, offering 128 macro cells, 84 user I/O pins, and a 7.5 ns pin-to-pin propagation delay in a 100-pin Plastic Quad Flat Pack (PQFP) package. A CPLD (Complex Programmable Logic Device) is a non-volatile, instantly-on programmable logic device that sits between discrete glue-logic ICs and larger FPGAs. Within the broader semiconductor taxonomy, the EPM7128SQC100-7 belongs to the CPLD category -> programmable logic -> digital IC -> semiconductor. MAX 7000S devices use a classic EEPROM-based architecture, providing deterministic timing, infinite reconfigurability (over 100 program/erase cycles), and 100% non-volatile storage so designs power up in a known state without external boot memory. Key features include 2,500 usable gates, a maximum internal operating frequency of 125 MHz (with some sources citing up to 250 MHz internal), 5.0V VCCIO/VCCINT operation, in-system programmability through a standard 4-pin JTAG interface (IEEE Std 1149.1), and built-in support for the MAX+PLUS II and Quartus development flows. The device includes 128 macro cells, each composed of a programmable AND/OR array feeding a configurable flip-flop, and provides flexible I/O standards including TTL and CMOS. Architecturally, the EPM7128SQC100-7 organizes its 128 macro cells into four Logic Array Blocks (LABs) interconnected through the Programmable Interconnect Array (PIA). This matrix-based interconnect delivers predictable, fixed-delay signal routing - a key advantage over SRAM-based FPGAs for deterministic glue-logic, bus-interface, address-decoding, and timing-critical applications where race conditions must be eliminated. Typical applications include bus-interface bridging (e.g., 8-bit/16-bit microprocessor glue logic), address decoding and chip-select generation, state-machine controllers, peripheral interface expansion, and legacy 5V system designs that require non-volatile, instantly-on logic. The 84 available user I/Os accommodate wide parallel buses and multi-channel control logic. When designing with this device, plan for a single 5V supply rail and verify that total output loading plus simultaneous switching I/O does not exceed the thermal envelope. For new designs, note that the MAX 7000 family is in legacy support - consider the MAX II or MAX V series for cost-sensitive modern designs, but the EPM7128 remains a proven solution for sustaining legacy 5V systems and as a pin-compatible firmware drop-in. This page synthesizes distributor pricing (as of 2026-09-13), drop-in pin-compatible alternatives (including the Atmel/Microchip ATF1508AS family noted by the Intel/Altera community as a silicon drop-in), practical design notes, and a parameter comparison matrix not found in the original datasheet alone.
EPM7128SQC100-7F - MAX 7000S 128-Macrocell CPLD 7.5ns | Altera
The Altera EPM7128SQC100-7F is a 128-macrocell CMOS CPLD from the MAX 7000S family, housed in a 100-pin PQFP (Plastic Quad Flat Pack) package. It delivers 7.5 ns pin-to-pin logic delay, 125 MHz maximum operating frequency, and 84 user I/O pins with 5V (4.75V–5.25V) tolerance, providing approximately 2,500 usable gates for glue-logic, bus-interface, and state-machine consolidation tasks. A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable IC that implements combinational and sequential logic in a single chip. CPLDs sit hierarchically between simple PLDs and FPGAs: they offer predictable timing (fixed propagation delay), deterministic power-up behavior, and much higher logic density than 22V10-style GALs, but lower density than SRAM-based FPGAs. MAX 7000S belongs to the EEPROM-based CPLD class — the configuration is retained without external memory and the device is in-system programmable (ISP) via JTAG. Key features of the EPM7128SQC100-7F include eight logic array blocks (LABs) of 16 macrocells each, a programmable interconnect array (PIA), per-macrocell flip-flops with clear/preset, and JTAG boundary-scan test (BST) circuitry compliant with IEEE 1149.1. The 'SQC100' package code denotes a surface-mount PQFP-100 at commercial 0 °C to 70 °C temperature range, while the '-7F' speed suffix specifies the 7.5 ns tPD grade with lead-free (Pb-free) matte-tin terminations. The architecture uses 5V-tolerant I/O with multi-voltage support, open-drain output option, and a global clock network shared by all LABs. Each macrocell contains a product-term array of 5×32 = 160 gates feeding a programmable register, which can be bypassed for pure combinational logic. Compared to its MAX 7000E predecessor, the 'S' (suffix S) variant adds JTAG BST in 128-macrocell and larger devices, expanded ISP capability, and the open-drain output option for wired-OR/wired-AND buses. Typical applications include legacy peripheral bus decoding (ISA, PCI, VME glue logic), address/data multiplexing between microprocessors and memories, state-machine controllers in industrial automation, and board-level configuration management in telecom and networking line cards. The instant-on behavior makes it well suited for boot-time logic that must be valid before any processor begins execution. When designing with this part, note that the MAX 7000S series is mature and Intel/Altera has marked most OPNs as obsolete or last-time-buy; verify current lifecycle status before starting a new design. For new designs where lifecycle supply assurance matters, evaluate the MAX II or MAX V families as modern equivalents. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet, helping engineers source, replace, and integrate the EPM7128SQC100-7F reliably.
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
The Intel (formerly Altera) EPM7128SQC100-7N is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, packaged in a 100-pin Plastic Quad Flat Pack (PQFP). The device integrates 128 macrocells, 8 logic array blocks, 2 global clocks, and up to 84 user I/Os, delivering 2,500 usable system gates with 5ns pin-to-pin delays and counter speeds up to 175.4 MHz in the -7 speed grade (7.5 ns tPD). A CPLD (Complex Programmable Logic Device) is a non-volatile reconfigurable logic device that bridges the gap between small PLDs and large FPGAs. It contains multiple PAL-like logic blocks interconnected by a programmable switch matrix, with non-volatile EEPROM storage that retains configuration without external memory. The MAX 7000 family sits in the CPLD -> Programmable Logic -> Logic IC -> Integrated Circuit taxonomy, traditionally used for glue logic, bus interfacing, and state-machine replacement. Key features include In-System Programmability (ISP) via IEEE 1149.1 JTAG, 32 product terms per macrocell, multiVolt I/O supporting 2.5V/3.3V/5V mixed-voltage interfacing, and individually programmable security bits. The device is fabricated on a 0.30µm CMOS EEPROM process, providing instant-on operation since configuration is stored on-chip. Typical applications span legacy industrial glue logic, address decoding and bus arbitration in microcontroller/microprocessor systems, peripheral I/O expansion, and state-machine implementation. Its 5V-tolerant I/O makes it especially useful for translating between 5V legacy buses and 3.3V modern logic. When designing with this part, note that the EPM7128SQC100-7N is now reported as Obsolete by Arrow, with the -N suffix denoting lead-free (Pb-free) packaging. Designers of new products should evaluate the ATF1508AS from Microchip as a silicon drop-in alternative.
EPM7128SQC160-10 - MAX 7000 CPLD, 128 Cells, 100 I/O, 10ns | Altera
The Altera (Intel) EPM7128SQC160-10 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000 family, delivering 128 macro cells, 2,500 usable gates, and 100 user I/O pins in a 160-pin PQFP (Plastic Quad Flat Pack) package with 10ns pin-to-pin propagation delay. Operating from a 5V core supply (with 3.3V or 5V I/O compatibility), the device provides in-system programmability via the IEEE Std. 1149.1 JTAG interface plus a legacy Altera ByteBlaster parallel port, enabling rapid prototyping and field upgrades. A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on programmable logic IC that integrates multiple PAL-like logic blocks (called macro cells) onto a single chip with a programmable interconnect matrix. CPLDs sit in the programmable logic hierarchy below FPGAs but above discrete glue logic, offering deterministic timing, predictable routing delays, and the ability to replace many SSI/MSI logic packages with a single device. The MAX 7000 family is Altera's second-generation MAX architecture, optimized for high-speed bus bridging, state-machine decoding, and peripheral interface glue logic. Key features of the EPM7128SQC160-10 include 128 macro cells (each containing a programmable AND/OR array and a configurable flip-flop with clear, preset, and clock-enable controls), 8 dedicated logic array blocks (LABs), a global interconnect called the Programmable Interconnect Array (PIA), and a per-pin tri-state buffer with user-programmable slew-rate control. The device supports hot-socketing insertion, I/O pins are 5V-tolerant with PCI-compliant drive capability, and in-system programming duration is typically under one second via JTAG. The 10ns speed grade provides a maximum toggle frequency of 100 MHz, sufficient for memory interfaces, bus arbitration logic, and high-speed glue logic. Architecture-wise, the EPM7128SQC160-10 uses Altera's classic EEPROM-based configuration cells (one per macro-cell bit), which means the design is non-volatile and retains its programmed logic without external boot memory - true instant-on behavior. Designers typically use Quartus II (legacy) or the MAX+PLUS II classic toolchain for design entry, fitting, and JTAG programming. The Programmable Interconnect Array (PIA) routes any LAB output to any other LAB input with fixed delay, simplifying static timing closure. Typical applications include PCI bus interface bridging, memory address decoding and chip-select generation, microcontroller peripheral expansion (address/data bus de-multiplexing), legacy 8051/68k/ColdFire system glue logic, and industrial control boards replacing dozens of 74LS/74F-series logic packages. Industrial designers also use the part for state-machine controllers and bus arbitration between multiple masters. Compared to FPGAs, the EPM7128S offers sub-100 mW standby power and deterministic 10 ns logic-array delays without configuration time. Design consideration: the 160-pin PQFP has 0.65 mm lead pitch and requires careful PCB layout to avoid solder bridges - a reflow profile with proper soak and peak temperature stages is recommended. Designers should also note that Quartus II support for legacy MAX 7000 devices requires the legacy device-support installer add-on. This page synthesizes distributor pricing, drop-in MAX 7000 speed-grade alternatives, JTAG programming guidance, and practical design notes not found in the manufacturer datasheet alone.
EPM7128SQC160-10N - 128-Macrocell MAX 7000 CPLD, 100MHz | Intel
The Intel (formerly Altera) EPM7128SQC160-10N is a 128-macrocell Complex Programmable Logic Device (CPLD) from the MAX 7000 family, housed in a 160-pin PQFP (Plastic Quad Flat Pack) package. It operates at 5V with up to 100 MHz counter frequency and 10 ns pin-to-pin delays, providing 2,500 usable gates and 100 user I/O pins for high-density glue-logic designs. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash/EEPROM-based programmable logic device that combines the deterministic timing of PAL/GAL architectures with higher logic density. It sits hierarchically below an FPGA but above simple PLDs in the programmable logic taxonomy: CPLD -> PLD -> programmable logic -> semiconductor. Compared to FPGAs, CPLDs offer instant-on configuration, predictable timing, and lower power for moderate-density glue logic. Key features include 128 macrocells (each with 36 product terms), 5V core supply, in-system programmability via JTAG (IEEE 1149.1), and built-in JTAG boundary-scan test circuitry on MAX 7000S devices with 128 or more macrocells. The 5-ns pin-to-pin logic delays and 175.4-MHz counter frequencies make the EPM7128SQC160-10N a strong fit for bus-interface bridging and address decoding in legacy 5V systems. The MAX 7000 architecture employs a second-generation MAX fabric with a global interconnect matrix, programmable interconnect array (PIA), and per-macrocell flip-flops. CMOS EEPROM technology stores configuration non-volatilely, so the device powers up in a known state with no external boot PROM, a defining advantage over SRAM-based FPGAs in deterministic boot applications. Typical applications include PCI/ISA bus interface logic, address decoding, glue logic for microprocessors, state-machine control, and 5V system prototyping. It is also used in industrial controllers, telecom backplane glue logic, and legacy system upgrades where 5V tolerance is mandatory. When designing, note that this part is in the MAX 7000 family and shares the classic Altera ByteBlaster/USB-Blaster programming flow via JTAG. Decoupling: place 0.1 uF and 10 uF caps near each supply pin pair to keep the global interconnect matrix quiet during simultaneous switching. This page synthesizes distributor pricing, same-family MAX 7000 drop-in alternatives (including speed-grade and temperature-grade variants), and practical design notes not found in the original manufacturer datasheet.
EPM7128SQC160-15 - MAX 7000 CPLD, 128 Macrocells, 100 I/O | Intel
The Intel (formerly Altera) EPM7128SQC160-15 is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, offering 128 macrocells, 2,500 usable gates, and 100 user I/Os in a 160-pin PQFP package with a 15 ns pin-to-pin propagation delay. Built on Altera's second-generation MAX architecture, it combines non-volatile EEPROM configuration memory with a 5V-tolerant I/O ring, making it suitable for legacy 5V system designs and 3.3V-tolerant interfaces. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits in the digital logic hierarchy between simple PLDs (PALs/GALs) and FPGAs. CPLDs use a deterministic, AND-OR fabric with macrocell-based logic blocks and a global interconnect that guarantees predictable, fixed propagation delays independent of routing density. This deterministic timing makes CPLDs ideal for glue logic, bus decoding, address mapping, state-machine control, and high-speed control-plane tasks where every nanosecond of delay must be accounted for at synthesis time. Key differentiating features include a maximum operating frequency of 125 MHz (with internal feedback), 4.5 ns logic-element propagation delay, in-system programmability via IEEE 1149.1 JTAG, and support for 5V/3.3V multi-voltage I/O via the MAX 7000S I/O ring. The 160-pin PQFP (Plastic Quad Flat Pack) package provides a generous thermal envelope for industrial and commercial temperature grades. Power consumption is dominated by static I/O current and scales with toggle frequency, with a typical ICC of approximately 100-150 mA at full operation. Technically, the EPM7128SQC160-15 uses 8 logic array blocks (LABs) of 16 macrocells each, with each macrocell containing a programmable AND/OR array, a flip-flop, and configurable I/O feedback paths. The EEPROM configuration cell retains logic design without external memory, supports 100 erase/program cycles, and allows instant-on behavior at power-up. The JTAG interface supports both boundary-scan testing and in-system programming, enabling board-level test access and field upgrades. Typical applications include bus-interface glue logic for 5V and 3.3V microcontroller systems, address decoding and chip-select generation for memory and peripheral buses, peripheral control and state-machine implementation in industrial controllers, legacy system replacements for discrete 74-series logic, and high-speed control logic in test-and-measurement equipment. The deterministic timing model also makes the EPM7128SQC160-15 well-suited for protocol bridging between microcontrollers and older peripheral ASICs. When designing with the EPM7128SQC160-15, note that the part is now in obsolescence transition - many MAX 7000 devices are listed as obsolete at Intel/Altera. Engineers should verify last-time-buy status with the manufacturer and plan migration paths to MAX II or MAX V CPLDs (which are 3.3V/2.5V/1.8V-only and require re-synthesis). Existing designs with stable long-term supply should consider a second-source strategy, since EPM7128SQC160-15 was originally a single-source part. This page synthesizes distributor pricing, verified drop-in alternatives drawn from the MAX 7000 family, and practical design notes - information not consolidated in the original Altera datasheet. All specifications are cross-checked against the manufacturer datasheet and current distributor listings.
EPM7128SQC160-15N - 128-Macro 15ns CPLD MAX 7000 | Intel / Altera
The Intel / Altera (formerly Altera) EPM7128SQC160-15N is a 128-macrocell, 100-IO Complex Programmable Logic Device (CPLD) from the second-generation MAX 7000 family, housed in a 160-pin Plastic Quad Flat Pack (PQFP-160 / BQFP-160) package. Built on a 5V-tolerant CMOS EEPROM process, it provides 15ns pin-to-pin logic delay, a 76.9 MHz internal counter frequency, and 2.5K usable gates, making it suitable for medium-density glue-logic and bus-interface applications. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the instant-on characteristics of PAL/GAL architecture with the density of a small FPGA. Within the broader programmable-logic taxonomy, CPLDs sit between discrete PALs (small, simple, fast) and FPGAs (large, register-rich, SRAM-based). The MAX 7000 family was Altera's second-generation CPLD architecture (succeeding the classic MAX 5000/9000) and introduced the multi-matrix interconnect plus ISP (in-system programmability) via JTAG, features that made it the de-facto industry standard for glue logic from the mid-1990s onward. Key features of the EPM7128SQC160-15N include 128 macrocells arranged in 8 logic array blocks (LABs), 100 user I/O pins, 15ns combinatorial propagation delay, a maximum internal counter frequency of 76.9 MHz, and 5V-tolerant I/O supporting both 3.3V and 5V mixed-voltage systems. The device is non-volatile (EEPROM-based) so the configuration is retained without an external boot PROM, and it supports in-system programming via the JTAG-compatible 4-pin interface. Programmable interconnect allows wide AND-OR logic functions across LABs with predictable timing. The architecture uses Altera's classic MAX (Multiple Array matriX) routing structure: each LAB contains 16 macrocells that share a programmable interconnect array, and LABs communicate through the PIA (Programmable Interconnect Array). This gives the EPM7128SQC160-15N deterministic, pin-locked timing that does not change with routing density - a property that distinguishes CPLDs from SRAM-based FPGAs where delay varies with placement. Typical applications include bus-interface bridging (PCI/ISA glue logic), address decoding and chip-select generation, power-up sequencing and reset distribution, motor control peripheral logic, industrial PLC I/O expansion, and replacement of multiple discrete TTL/CMOS logic packages. The wide 5V I/O tolerance is especially valued when interfacing legacy microcontrollers or bus transceivers to modern 3.3V ASICs. When designing with this device, note that the PQFP-160 footprint has longer lead lengths than modern BGA/QFN packages, which limits high-speed signal edge rates above ~50 MHz. For new designs above 100 MHz I/O, consider migrating to a MAX V, MAX 10, or MAX II CPLD in a smaller QFN package while preserving the MAX 7000 logic architecture. This page synthesizes distributor pricing, SameFrame-pinout drop-in alternatives, and practical glue-logic design notes not found in the original 1998-vintage datasheet.
EPM7128SQC160-6 - MAX 7000S 128-Macro Cell CPLD, 6ns, PQFP-160 | Altera/Intel
The Altera (Intel) EPM7128SQC160-6 is a 128-macrocell member of the MAX 7000S family of Complex Programmable Logic Devices (CPLDs) housed in a 160-pin Plastic Quad Flat Pack (PQFP) package. It is built on a 0.5 µm CMOS EEPROM process with 2.5K usable gates and offers a pin-to-pin propagation delay of 6 ns, making it suitable for high-speed glue-logic, bus decoding, and interface bridging applications. The device operates from a single 5 V supply (4.75 V – 5.25 V) and provides 100 user I/O pins organized in 4 I/O banks, supporting both 5 V and 3.3 V LVTTL/LVCMOS interfacing when configured via the Quartus or MAX+PLUS II toolchains. A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device that combines multiple PAL-like macrocell arrays with a central interconnect matrix. In the system hierarchy, the CPLD sits between simple SPLDs (PAL/GAL) and larger FPGAs, offering deterministic timing, low power, and in-system programmability via IEEE 1149.1 JTAG. MAX 7000S devices are particularly favored for glue logic, address decoding, peripheral bridging, and state-machine controllers where deterministic propagation delay is more important than raw gate count. Key features include in-system programmability through JTAG (IEEE Std 1149.1), 128 macrocells distributed across 4 logic array blocks (LABs), 2.5K equivalent gates of usable logic, 100 user I/O pins, and an internal fmax of 147.1 MHz. The EPM7128SQC160-6 supports ISP (In-System Programming) via the dedicated JTAG pins, allowing field upgrades without removing the device from the PCB. The architecture provides predictable interconnect delays and a global clear/preset network. The MAX 7000S architecture uses a classic EEPROM-based, non-volatile programming cell that retains configuration indefinitely without external memory. Each macrocell contains a programmable AND/OR array plus a configurable flip-flop, with product-term allocation steering logic to balance speed and density. The 6 ns speed grade is the second-fastest commercial bin in this family (only 5 ns is faster), making the -6 well suited for memory interface controllers, bus bridges, and high-speed state machines where the 10 ns and 15 ns grades are too slow. Typical applications include address decoding for 8/16/ and 32-bit microprocessors, asynchronous bus interfaces between processors and peripherals, peripheral controllers (UART, timers, interrupt controllers), I/O expansion, and 5 V glue logic on legacy industrial platforms. The PQFP-160 footprint allows drop-in replacement of the slower EPM7128SQC160-10 and EPM7128SQC160-15 grades with identical pinout. When designing with this part, note that the part is mature and approaching obsolescence - verify long-term supply before committing to new designs. For new designs, consider MAX II (EPM240) or MAX V CPLDs in modern packages for better toolchain support. Use Quartus II 13.0 or earlier, or MAX+PLUS II, for synthesis and fitting. This page synthesizes distributor pricing, drop-in alternatives drawn from the same MAX 7000S family, and practical design notes not consolidated on any single distributor page.
EPM7128SQI100-10 - MAX 7000S CPLD 128-Macrocell 84-IO 10ns | Altera
The Altera (Intel) EPM7128SQI100-10 is a member of the MAX 7000S family of high-density, high-performance CMOS Complex Programmable Logic Devices (CPLDs) based on Altera's second-generation MAX architecture. It provides 128 macrocells, 84 user I/Os, and 2,500 usable gates in a 100-pin PQFP package, with pin-to-pin propagation delay of 10 ns and a maximum internal frequency of 125 MHz to 250 MHz depending on configuration. The "I" suffix designates the industrial operating temperature range of -40C to +85C, while the "Q" denotes the PQFP-100 package option. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that combines the architectural simplicity of a PAL with the density and flexibility of an FPGA. CPLDs sit in the programmable logic hierarchy between simple SPLDs (single PAL/GAL arrays) and FPGAs (gate-array style SRAM-based devices). They use EEPROM or flash configuration cells, retain their configuration without external memory, and are typically used for glue logic, bus bridging, state-machine control, and address decoding in cost-sensitive industrial designs. The MAX 7000S family targets 5V tolerant interfaces and provides in-system programmability (ISP) via IEEE 1149.1 JTAG. Key features of the EPM7128SQI100-10 include pin-to-pin delays of 10 ns, counter speeds up to 175.4 MHz, 100% TTL-compatible I/O, JTAG-compliant ISP, and an extended industrial temperature range. The device supports 5V core operation with multi-voltage I/O support, making it suitable as a bridge between legacy 5V logic and modern 3.3V peripherals. Built-in JTAG (IEEE 1149.1) boundary-scan support simplifies board-level test. Architecturally, the MAX 7000S device uses Logic Array Blocks (LABs) of 16 macrocells each, interconnected via a programmable interconnect array (PIA). Each macrocell contains a programmable AND/OR/registered logic block with configurable flip-flop polarity, clock, clear, and preset controls, and an I/O control block with tri-state, open-drain, or registered output options. The EEPROM cell technology guarantees 100 reprogram/erase cycles minimum. Typical applications include industrial control glue logic, bus interface bridging (e.g., PCI to local bus), address decoding and chip-select generation, state-machine controllers in motor drives, and 5V-to-3.3V level translation in legacy system upgrades. The 84 user I/Os make it well-suited for medium-density interface aggregation. When designing with the EPM7128SQI100-10, ensure the 5V VCC supply is well-decoupled with 0.1uF and 10uF capacitors placed close to the device. Unused I/O pins should be configured as outputs and left unconnected, or tied to a defined logic level through the Quartus design software. Industrial-grade parts require proper thermal management at high toggle rates. This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design notes drawn from the MAX 7000S datasheet family, providing information not consolidated on any single distributor or manufacturer page.
EPM7128SQI100-10N - 128-Macrocell MAX 7000S CPLD, 10ns, PQFP-100 | Intel / Altera
The Intel / Altera EPM7128SQI100-10N is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, offering 128 macrocells, 84 user I/Os, 2,500 usable gates, and 10 ns pin-to-pin logic delays in a 100-pin PQFP (Plastic Quad Flat Pack) package. It operates from a 5 V core supply and supports programmable VCCIO for mixed 3.3 V / 5 V I/O interfacing, with counter frequencies up to 175.4 MHz and ISP (in-system programmability) via JTAG. What is a CPLD? A Complex Programmable Logic Device is a non-volatile, reprogrammable digital IC that sits between simple PAL/GAL spld devices and high-density FPGAs. CPLDs (hierarchy: CPLD -> PLD -> programmable logic -> digital IC -> semiconductor) use a deterministic routing fabric and on-chip EEPROM/flash configuration memory, so they retain logic at power-up with no external boot PROM. The MAX 7000S family from Altera (now Intel FPGA) is a second-generation MAX architecture family widely used as glue logic, bus bridges, and state-machine controllers in industrial, telecom, and embedded designs. Key features of the EPM7128SQI100-10N include 5-ns pin-to-pin delays (commercial speed grade), 100 MHz maximum operating frequency, IEEE Std. 1149.1 JTAG boundary-scan test (BST) circuitry, multiVolt I/O for 2.5 V / 3.3 V / 5 V interfacing, and individual macrocell clear/preset for synchronous or asynchronous control. The 'I' suffix indicates the industrial temperature grade (-40C to +85C), and the 'N' suffix indicates a lead-free / Pb-free RoHS-compliant assembly. Architecturally, the EPM7128SQI100-10N organizes its 128 macrocells into four Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). Each macrocell contains a programmable AND/OR array plus a configurable flip-flop with product-term clock, clear, and preset - giving designers 32 product terms per macrocell for sum-of-products logic. The deterministic PIA routing yields predictable, glitch-free timing that is independent of design placement - a key advantage over FPGAs for control-plane logic. Typical applications include bus decoding and address mapping, peripheral chip-select generation, state-machine controllers, I/O expansion and bus bridging, glue logic between microprocessors and peripherals, and JTAG-controlled test access. The wide I/O count and PQFP-100 footprint make it well-suited for legacy industrial backplanes and 5 V-tolerant designs. When designing with this device, ensure the VCCINT-to-VCCIO supply sequencing follows the datasheet monotonic-rise requirements and that unused I/O pins are correctly terminated (per AN 74). The JTAG chain should include the proper bypass instructions to avoid contention when multiple devices share TCK/TMS. This page synthesizes distributor pricing, drop-in compatible alternatives, and practical design notes that go beyond the manufacturer datasheet to help engineers select, source, and apply the EPM7128SQI100-10N with confidence.
EPM7128SQI100-15N - 128-Macrocell CPLD, 15ns, PQFP-100 | Intel
The Intel (formerly Altera) EPM7128SQI100-15N is a 128-macrocell CMOS EE-PLD (erasable electrically programmable logic device) from the MAX 7000S programmable logic device family, housed in a 100-pin Plastic Quad Flat Pack (PQFP) package and specified for industrial temperature grade operation. It delivers a 15 ns pin-to-pin propagation delay, supports up to 76.9 MHz maximum clock frequency, and offers 80 user I/O lines that can be configured for either 3.3 V or 5 V logic levels, all on a 4.5 V to 5.5 V core supply. What is a CPLD? A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic semiconductor that combines multiple PAL/GAL macrocell arrays with a central interconnect matrix, retaining configuration in on-chip EEPROM or flash memory. CPLDs sit in the broader taxonomy of programmable logic devices (PLDs) alongside simple PLDs (SPLDs), FPGAs, and structured ASICs, and are typically chosen over FPGAs for glue-logic, bus-interface bridging, state-machine and power-up sequencing tasks where deterministic timing and instant-on behavior matter more than raw logic density. As a member of the MAX 7000S family, the EPM7128SQI100-15N targets logic densities up to 2,500 usable gates with the deterministic timing that characterizes this product line. Key features that differentiate the EPM7128SQI100-15N include the 128-macrocell logic capacity, the dual-voltage I/O capability (3.3 V / 5 V) provided by the MAX 7000S output structure, the 15 ns propagation delay suitable for 66 MHz PCI and similar bus interfaces, and the non-volatile in-system programmability via the JTAG-compatible IEEE 1149.1 boundary-scan interface. The 'S' suffix denotes the MAX 7000S sub-family, while the 'I' industrial temperature range and 'N' lead-free lead finish mark identify the specific orderable part number. Compared with older MAX 7000 variants, the 'S' family reduces power consumption and adds JTAG support. Architecturally, the device combines four logic array blocks (LABs) interconnected by a programmable interconnect array (PIA), with each LAB containing 16 macrocells. Each macrocell integrates a programmable AND/OR array, a product-term select matrix, a flip-flop, and an I/O control block supporting configurable slew rate, open-drain, and registered/combinational modes. The in-system EEPROM configuration cell technology provides instant-on behavior at power-up with no external boot PROM required, a key advantage versus SRAM-based FPGAs for industrial control and avionics applications. Typical applications include PCI bus-interface glue logic, microprogrammed state-machine controllers, address decoding and chip-select generation in microprocessor systems, power-supply sequencing logic, industrial motor-control state machines, and legacy board-level replacement of discrete TTL/CMOS glue. Because the device is non-volatile, it is well suited to safety-critical or deterministic-startup applications where a configuration bitstream cannot be lost. Designers should budget adequate 5 V core current (typically tens of milliamps quiescent, plus dynamic current proportional to toggle rate), place 0.1 µF / 10 µF decoupling close to each VCC/GND pair on the PQFP-100 footprint, and follow Altera/Intel AN70 (MAX 7000S family) application-note guidance for in-system programming and JTAG chain termination. Verify timing against the most recent Intel MAX 7000 device datasheet, not legacy Altera revisions, because part numbering has remained stable but specifications have been re-baselined. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that go beyond a single datasheet excerpt, helping engineers rapidly decide whether the EPM7128SQI100-15N is the right MAX 7000S member for a 15 ns, 128-macrocell industrial design in PQFP-100.
EPM7128SQI160-10 - 128-Macrocell MAX 7000S CPLD, 10ns, PQFP-160 | Intel
The Intel (formerly Altera) EPM7128SQI160-10 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, housed in a 160-pin Plastic Quad Flat Pack (PQFP) package. Built on Altera's second-generation MAX architecture, the device integrates 128 macrocells, 2.5K equivalent gates, and a maximum operating frequency of 100 MHz at a 5V core supply. The "10" suffix denotes the 10 ns pin-to-pin logic delay speed grade, with a 10 ns tPD and a counter frequency of 100 MHz. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with higher density. In the system hierarchy, a CPLD sits below FPGAs in logic capacity but above discrete glue logic in integration, providing fast, deterministic I/O-to-I/O timing for address decoding, bus interfacing, state-machine control, and peripheral bridging. MAX 7000S devices use EEPROM-based configuration cells, so they are instantly programmable in-system via JTAG (IEEE 1149.1) and retain their configuration without external memory. Key features include in-system programmability (ISP) through the 4-wire JTAG interface, 100% routability with predictable timing, programmable macrocell flip-flops with individual clear, preset, clock, and clock-enable controls, open-drain output option, and a multi-volt I/O interface supporting 3.3 V or 5 V operation from a 5 V VCCINT supply. Each macrocell contains a programmable AND/OR/expander-array logic block with a configurable flip-flop. The device also supports a global clock network, four dedicated inputs, security-bit protection for the configuration, and an enhanced JTAG instruction set. Architecturally, the EPM7128SQI160-10 organizes its 128 macrocells into four Logic Array Blocks (LABs) of 16 macrocells each, interconnected through the Programmable Interconnect Array (PIA). Each I/O pin has an associated I/O control block providing slew-rate control, tri-state buffering, and a programmable pull-up resistor. The EEPROM-based Look-Up Tables (LUTs) and product-term arrays produce deterministic combinational and sequential logic with no hidden routing delays. Typical applications include bus-interface glue logic, address decoding for microprocessors and DSPs, peripheral controllers, state-machine implementation, power-up sequencing logic, JTAG-driven board-test infrastructure, and legacy 5V industrial control designs. The wide PQFP-160 package offers 100+ user I/O pins, making it suitable as a system-level glue-logic hub replacing multiple 22V10-style SPLDs. When designing with this device, the user must supply a stable 5 V VCCINT and observe the JTAG programming voltages. Quartus II or MAX+PLUS II software is used for design entry, synthesis, place-and-route, and device programming. Place decoupling capacitors (0.1 uF and 10 uF) close to every VCC and GND pin pair. This page synthesizes distributor pricing, pin-compatible same-family alternatives, and design guidance not found on standard manufacturer listings, giving engineers a single consolidated reference for the EPM7128SQI160-10.
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
The Altera (now Intel) EPM7128STC100-10 is a high-density, high-performance Complex Programmable Logic Device (CPLD) from the MAX 7000S family, featuring 128 macro cells, 2,500 usable gates, and 84 user I/Os in a 100-pin TQFP package. Built on a 5V CMOS EEPROM process, it delivers a 10 ns pin-to-pin propagation delay and an internal frequency up to 100 MHz (with some derivative markings indicating up to 250 MHz internal performance). It is in-system programmable via the IEEE 1149.1 JTAG interface and supports 3.3V or 5V multi-volt I/O operation through Altera's MultiVolt feature. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that sits between simple gate arrays and high-density FPGAs in the digital logic hierarchy: PLA/PAL < CPLD < FPGA. CPLDs provide predictable, deterministic timing (fixed propagation delay) and instant-on behavior because the configuration is stored in on-chip EEPROM rather than loaded from external flash at boot. The MAX 7000S family uses Altera's second-generation MAX architecture with an Enhanced FastTrack interconnect and Logic Array Blocks (LABs), offering faster carry chains, more I/O per macrocell, and the popular JTAG-based ISP (in-system programmability) that made MAX 7000S a workhorse of glue-logic designs from the mid-1990s through the 2010s. Key features include 128 macro cells distributed across 8 Logic Array Blocks of 16 macrocells each, 84 user I/O pins, 10 ns tPD (pin-to-pin delay), 100 MHz fCNT internal counter frequency, and 3.3V/5V MultiVolt I/O compatibility. The device also integrates a JTAG-compliant boundary-scan test interface, four input pins that can be used as global clock/clear/preset/OE controls, and open-drain or programmable slew-rate output options per pin. Typical applications include bus-interface bridging, address decoding and chip-select generation, state-machine and sequencer logic, peripheral glue logic for microprocessors and DSPs, board-level power-up sequencing, and legacy industrial control retrofits where deterministic timing and instant-on behavior are required. It is widely used in telecommunications backplane glue, factory automation controllers, and test equipment front-ends. Designers should note that the EPM7128STC100-10 is programmed with Altera/Intel Quartus software (legacy MAX+PLUS II is also supported). Pin assignments and JTAG chain topology must follow the MAX 7000S device handbook. The '10' suffix denotes the 10 ns speed grade; the faster '7' grade (EPM7128STC100-7) is pin-compatible. The 'C100' package is TQFP-100. This page synthesizes distributor pricing, package-equivalent drop-in alternatives from the same MAX 7000S family, and practical design notes not aggregated in the manufacturer datasheet.
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
The Altera (Intel) EPM7128STC100-10N is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, offering 2,500 usable gates, 128 macrocells, and 84 user I/Os in a 100-pin TQFP package. The device operates from a 5V VCC supply, features a 10ns pin-to-pin propagation delay, and supports an internal frequency up to 100 MHz, making it suitable for high-speed glue-logic, bus-interface bridging, and state-machine applications. The "N" suffix indicates lead-free / Pb-free terminal finish compliant with modern RoHS manufacturing standards. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that combines the instant-on characteristics of PAL/GAL architecture with macrocell-based logic blocks interconnected via a programmable AND/OR array. CPLDs sit in the programmable logic hierarchy below FPGAs but above simple PLDs, providing deterministic 10 ns-class timing, high I/O count, and unlimited in-system reprogrammability via JTAG. The MAX 7000S family uses Altera's second-generation MAX architecture with each macrocell containing a programmable AND array, a fixed-OR array, a flip-flop, and a product-term steering network. Key features of the EPM7128STC100-10N include 128 macrocells organized into 8 Logic Array Blocks (LABs) of 16 macrocells each, 84 user I/O pins, in-system programmability through the IEEE 1149.1 JTAG interface, MultiVolt I/O supporting 2.5V/3.3V/5V interface levels, and built-in JTAG boundary-scan test support. The device also includes 4 dedicated input pins, a global clock network, and per-macrocell configurable registers that can be implemented as D, T, JK, or SR flip-flops. The non-volatile EEPROM-based configuration provides instant-on behavior with no external boot memory required. The architecture is based on a CMOS EEPROM process with 5V-tolerant I/O cells. The MAX 7000S family is supported by Altera's legacy MAX+PLUS II and Quartus Prime design tools, with the Quartus II Web Edition providing a free development environment for this and other legacy MAX devices. Programmable Security Bits protect the design against unauthorized readback. The device supports both 3.3V and 5V JTAG in-system programming, with VCCIO pins enabling mixed-voltage I/O operation. Typical applications include bus-interface bridging (PCI to ISA, microcontroller to peripheral glue logic), state-machine controllers, address decoding and chip-select generation, power-supply sequencing logic, communication protocol conversion (UART, SPI, I2C bridging), industrial control replacement of discrete 74-series logic, and high-speed bus arbitration. The 100-pin TQFP footprint is also suitable for legacy industrial designs where instant-on, deterministic timing is required. When designing with the EPM7128STC100-10N, observe the VCCINT and VCCIO decoupling guidelines: place one 0.1 µF ceramic capacitor per power pin within 3 mm of each pin, plus a 10 µF bulk capacitor near the device. The JTAG pins (TCK, TMS, TDI, TDO, and optional TRST) require careful routing and a 10 kΩ pull-up on TCK per IEEE 1149.1 recommendations. Unused I/O pins can be left floating, but configured-as-input pins should be tied to a defined logic level through internal pull-ups or external resistors to avoid quiescent Icc drift. This page synthesizes distributor pricing, drop-in same-brand and cross-brand alternatives, and practical design considerations not found in the standalone manufacturer datasheet.
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
The Intel / Altera EPM7128STC100-15N is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, offering 2,500 usable gates, 128 macro cells, and 84 user I/O pins in a 100-pin TQFP package. It operates from a 5 V supply with a -15 speed grade (15 ns pin-to-pin logic delay) and a maximum internal toggle frequency of 76.9 MHz. A CPLD is a non-volatile, instantaneously-on programmable logic device that implements glue logic, bus decoding, state machines, and interface bridging between disparate voltage or timing domains. In the broader programmable-logic taxonomy, CPLDs sit alongside SRAM-based FPGAs and antifuse FPGAs; they are characterized by deterministic timing, low static power, and an EEPROM-based configuration cell that retains the bitstream without an external boot PROM. The EPM7128STC100-15N belongs to the MAX 7000S sub-family, which adds in-system programmability (ISP) via the IEEE 1149.1 JTAG interface to the original MAX 7000 architecture. Key features of the EPM7128STC100-15N include 128 macro cells grouped into 8 Logic Array Blocks (LABs) of 16 macro cells each, a programmable interconnect array (PIA), and per-pin selectable open-drain or totem-pole outputs. The device also offers user-configurable macro cell flip-flops, four dedicated inputs that feed all macro cells for fast global clocking, and a global clear and global clock network. Each I/O pin is compatible with 5 V, 3.3 V, and 2.5 V logic levels through programmable voltage-clamp circuitry. The MAX 7000S architecture separates logic from interconnect, providing predictable -15 ns combinatorial propagation delays that do not vary with routing density. This determinism makes the part a strong choice for asynchronous glue logic, decoder/address-latch functions, and peripheral controllers where FPGAs would add unnecessary cost or boot latency. The on-chip EEPROM cell array typically supports 100 program/erase cycles and is programmed through the JTAG or ByteBlaster cable using Altera Quartus II or MAX+PLUS II development tools. Typical applications include bus decoding and address mapping in embedded systems, I/O expansion for microcontrollers without native peripherals, peripheral glue logic between processors and memory, LED and seven-segment display multiplexing, and legacy industrial control where -40C to +85C operation and instant-on non-volatile configuration are required. Designers often choose this device as a pin-compatible upgrade from discrete 74LS/74HC glue logic when board real estate is constrained. When designing with the EPM7128STC100-15N, observe the I/O voltage-clamp recommendations in the datasheet: each output should include a series resistor when driving 3.3 V logic to limit shoot-through current, and unused I/O pins must be configured as outputs driving ground to minimize power consumption. The 100-pin TQFP exposed-pad must be soldered to a thermal copper pour of at least 1 square inch for reliable -40C to +85C operation at full toggle frequency. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the manufacturer product brief, with values verified against multiple distributor sources as of the last-verified date.
EPM7128STC100-6 - MAX 7000S CPLD 128-Macrocell 6ns | Intel
The Intel (formerly Altera) EPM7128STC100-6 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, featuring 128 macrocells, 2.5K equivalent gates, and a 6 ns pin-to-pin propagation delay in a 100-pin TQFP (STC100) package. It operates from a 5 V supply and supports in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface, with a maximum internal operating frequency of 147.1 MHz and 84 user I/O pins. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like logic blocks on a single chip with a programmable interconnect matrix. CPLDs sit in the programmable logic hierarchy between small SPLDs and large FPGAs: they offer deterministic, fast input-to-output timing (a few nanoseconds), instant-on configuration from on-chip EEPROM, and are widely used for glue logic, bus interfacing, address decoding, and state-machine replacement. The MAX 7000S family uses Altera's second-generation MAX architecture with each macrocell containing a programmable AND/OR/expanders array and a configurable flip-flop. Key features include 6 ns tPD (commercial speed grade -6), 147.1 MHz fCNT internal counter frequency, 100% tested PCI-compliant timing in -6/-7/-10 speed grades for 33 MHz PCI Local Bus Revision 2.2, JTAG boundary-scan test support, and four-pin JTAG ISP. Each macrocell provides up to 36 product terms, and the device supports programmable power-saving modes that cut standby current by 50% or more on unused macrocells. The MAX 7000S architecture employs a classic EEPROM-based configuration cell, a fast interconnect matrix (FastTrack), and individual macrocell registers. The 5 V core and I/O make this device suitable for legacy 5 V systems where modern 3.3 V or 1.8 V CPLDs cannot interface directly. The 100-pin TQFP package has a 1.0 mm lead pitch and supports surface-mount reflow assembly on standard FR-4 boards. Typical applications include 5 V system glue logic, address decoding and chip-select generation, asynchronous state machines, bus arbitration logic, 33 MHz PCI interface glue, industrial control replacement of discrete TTL/CMOS logic, and JTAG-configurable I/O expansion. The instant-on behavior makes it ideal for boot-ROM replacement, power-sequencing controllers, and reset-distribution networks. When designing with this device, observe the 5 V VCC tolerance and ensure 5 V-tolerant I/O are not exposed to higher-voltage signals. Use the Quartus Prime (or legacy MAX+PLUS II) toolchain for design entry, fitting, and JTAG programming, and budget JTAG chain length when cascading multiple MAX 7000S devices on a single scan chain. This page synthesizes distributor pricing, verified drop-in alternatives, and JTAG programming guidance not found in the manufacturer datasheet - helping engineers accelerate board bring-up and second-source the device across MAX 7000S speed grades.
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
The Altera (now Intel) EPM7128STC100-6N is a high-density, high-performance EEPROM-based CPLD from the MAX 7000S family, delivering 2,500 usable gates, 128 macro cells, and 84 user I/Os in a 100-pin TQFP package with 147.1 MHz maximum internal frequency and 5 ns pin-to-pin propagation delay. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that sits between simple PAL/GAL chips and FPGAs in the programmable logic hierarchy. CPLDs use EEPROM or flash configuration memory, provide deterministic timing with predictable propagation delays, and typically include on-chip non-volatile storage - making them ideal for glue logic, bus interfacing, and power-up configuration tasks. Within the taxonomy, EPM7128STC100-6N belongs to: CPLD > Complex Programmable Logic Device > Programmable Logic Device > Semiconductor IC. Key features include 250 MHz internal counter frequency, IEEE 1149.1 JTAG boundary-scan support, in-system programmability (ISP) via JTAG, multi-volt core and I/O operation, and 5V-tolerant I/Os. The device is fabricated on a CMOS EEPROM process and supports Altera's Quartus and MAX+PLUS II development environments for schematic, VHDL, and Verilog HDL design entry. The MAX 7000S architecture combines a Programmable Logic Array (PLA) with a Programmable Logic Device (PLD) macro-cell structure, providing each macro cell with a configurable register, product-term selection, and programmable I/O. This architecture yields fast, deterministic propagation delays and high logic density per I/O pin, suitable for high-speed glue-logic and state-machine applications. Typical applications include address decoding for microprocessor and DSP systems, peripheral bus interface bridging (PCI, ISA, VME), state-machine control for industrial automation, bus arbitration and protocol conversion in telecommunications, and legacy system upgrade paths requiring 5V-tolerant logic. The 5V tolerant I/Os allow direct interface to legacy TTL logic without level shifters. When designing with this part, verify power-supply decoupling: each VCC/VCCIO pin should have a 0.1 microfarad ceramic decoupling capacitor placed within 3 mm of the pin. Unused I/O pins should be configured as outputs driving ground to minimize power consumption. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
EPM7128STC100-7 - MAX 7000S CPLD, 128 Macro, 7.5ns, TQFP-100 | Intel
The Intel (formerly Altera) EPM7128STC100-7 is a 128-macrocell high-density CPLD from the MAX 7000S family, packaged in a 100-pin TQFP and operating from a 5V supply with 84 user I/Os. Based on Altera's second-generation MAX architecture, it provides approximately 2,500 usable gates and supports in-system programmability through a 4-pin JTAG interface. The part is rated for a 7.5 ns pin-to-pin propagation delay with a maximum internal frequency of 125 MHz (some sources list 250 MHz for internal performance), suiting glue-logic, bus-interface and state-machine designs that require fast deterministic response. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable IC that combines multiple PAL-like macrocell blocks on a single die with a programmable interconnect matrix. In the system hierarchy, the CPLD sits between discrete 74-series glue logic and an FPGA, offering deterministic timing, instant-on behavior from on-chip EEPROM, and typically 30-600 macrocells per device. Because the configuration is stored in non-volatile memory, MAX 7000S CPLDs boot in microseconds with no external boot PROM, making them ideal for power-on control, I/O expansion and bus bridging. Key features of the EPM7128STC100-7 include 128 macrocells distributed across 8 logic array blocks (LABs) of 16 macrocells each, 84 available user I/O pins, and a 36-input programmable interconnect network. The device supports 5V in-system programmability (ISP) via JTAG (IEEE 1149.1), multi-volt I/O interfacing (3.3V and 5V), and per-pin programmable slew rate and open-drain control. Each macrocell provides a programmable flip-flop with D, T, JK or SR modes, plus configurable product-term steering for combinatorial or registered outputs. The MAX 7000S architecture uses Altera's classic second-generation EEPROM-based logic elements with a unified global routing pool, which yields predictable timing independent of design placement. The 7.5 ns tPD figure is valid across commercial temperature and voltage ranges, allowing the device to replace multiple discrete TTL/CMOS 74-series packages while reducing board area and improving design flexibility through software-based logic changes. Typical applications include address decoding and bus-interface logic in microprocessor and DSP systems, peripheral glue logic in embedded designs, state-machine controllers, and 5V I/O expansion for ASICs and microcontrollers. Industrial automation and legacy equipment upgrades also leverage the MAX 7000S for backward-compatible 5V logic integration. When designing with the EPM7128STC100-7, ensure each I/O pin's output enable and slew rate are configured in the Quartus II / MAX+PLUS II fitting tool to match signal integrity targets. JTAG chain ordering must be defined to allow in-field reprogramming, and unused pins should be set to "As input tri-stated" to minimize power and EMI. This page synthesizes distributor pricing, pin-compatible MAX 7000S drop-in alternatives, and practical design notes not found on a single manufacturer datasheet.
EPM7128STI100-10N - 128-Macrocell CPLD, 10ns, 100-pin TQFP | Altera
The Altera (Intel) EPM7128STI100-10N is a high-density, high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family. It delivers 128 macrocells with up to 2,500 usable gates, a 10 ns pin-to-pin logic delay, and is housed in a 100-pin TQFP (Industrial temperature grade) package. The device operates from a single 5 V supply and supports in-system programmability (ISP) via the built-in IEEE 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays with a central programmable interconnect matrix. It sits between simple SPLDs (e.g., GAL22V10) and high-density FPGAs in the programmable logic hierarchy, offering deterministic timing, instant-on behavior from EEPROM configuration, and high I/O count with low power. The MAX 7000S family specifically uses second-generation MAX architecture fabricated in CMOS EEPROM technology, providing up to 5,000 usable gates across the family. Key features include 84 user I/O pins (100-pin TQFP), 5 V core operation with 5 V tolerant I/O, JTAG boundary-scan test (BST) support, an open-drain output option on each I/O (in MAX 7000A variants), and a typical counter frequency up to 175.4 MHz. The 10 ns tPD supports glue-logic, interface bridging, and bus decoding at system clock rates up to approximately 100 MHz. Industrial temperature range is -40C to +85C. Architecturally, the EPM7128STI100-10N is organized into 4 Logic Array Blocks (LABs), each containing 16 macrocells, with a programmable interconnect array (PIA) routing signals between LABs and to the I/O pins. The EEPROM configuration cell ensures zero-power non-volatile storage and instant power-on valid I/O within microseconds, a key advantage over SRAM-based FPGAs. Typical applications include bus-interface bridging (e.g., PCI to local bus), address decoding and chip-select generation in microprocessor systems, glue-logic replacement of multiple 74-series TTL/CMOS parts, peripheral control in embedded designs, and state-machine implementation in industrial control. The 5 V I/O tolerance is particularly valuable for legacy 5 V system integration. When designing with this part, account for the 5 V supply requirement (cannot directly interface with 3.3 V-only systems without level translation), ensure JTAG chain integrity if multiple devices share the TAP, and respect the I/O current-limit specifications when driving heavy loads. This page synthesizes distributor pricing, drop-in same-family and cross-brand alternatives, and practical design notes not found in the manufacturer datasheet alone, supporting faster component selection for engineers.
EPM7160ELC84-12 - MAX 7000 CPLD, 160 Macrocells, 12ns | Altera
The Altera (Intel PSG) EPM7160ELC84-12 is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, providing 160 macrocells, 64 user I/Os, and a maximum pin-to-pin delay of 12 ns, housed in an 84-pin PLCC (J-Lead) package. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays on a single chip. CPLDs sit between simple SPLDs (PALs/GALs) and larger FPGAs in the programmable logic hierarchy: SPLD -> CPLD -> FPGA. They offer deterministic, near-zero standby power, instant-on configuration from on-chip EEPROM, and predictable timing that is well suited to glue logic, bus decoding, and state-machine control. The MAX 7000 family uses Altera's second-generation MAX architecture fabricated in CMOS, and supports 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. Key features include 3,200 usable gates, four logic array blocks (LABs), 68 maximum user I/Os, a 12 ns pin-to-pin propagation delay with counter speeds up to 90.9 MHz, and a single 5.0 V supply (4.75 V to 5.25 V). The 'E' suffix designates the enhanced MAX 7000E variant with additional global clocks, additional output enable controls, enhanced interconnect resources, and fast input registers. In-system programmability via JTAG eliminates the need for a dedicated programmer and enables field upgrades. Typical applications include bus decoding and address mapping in 5V microprocessor systems, glue logic between microcontrollers and peripherals, state-machine and sequencer designs, and replacement of discrete TTL/CMOS logic gates. The wide I/O count also makes it attractive for industrial control and telecommunication line-card glue functions. When designing with the EPM7160ELC84-12, remember that the 84-pin PLCC footprint requires a through-hole or socketed footprint with J-leads, not a standard surface-mount land pattern. Plan for JTAG chain access in PCB layout to enable ISP. Total power dissipation scales with the number of toggling outputs and the toggle frequency; use Altera's Quartus II MAX+PLUS II power estimator for accurate budgeting. This page synthesizes distributor pricing, same-family drop-in alternatives with different speed grades and temperature ratings, and practical design notes not consolidated in any single manufacturer datasheet.
EPM7160ELC84-15 - MAX 7000 CPLD, 160 Macrocells, 15ns, 84-PLCC
The Intel (formerly Altera) EPM7160ELC84-15 is a high-density, high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, delivering 3,200 usable gates, 160 macrocells, and 76.9 MHz counter frequency in a 84-pin Plastic Leaded Chip Carrier (PLCC) package. It provides in-system programmability (ISP) through the IEEE Std. 1149.1 JTAG interface and pin-to-pin delays as fast as 15 ns for the -15 speed grade. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple SPLDs/GALs and FPGAs in the programmable logic hierarchy. It uses a classic AND-OR (sum-of-products) macrocell fabric with on-chip EEPROM to retain configuration without external memory, executes logic deterministically with predictable timing, and is widely used for glue logic, bus interfacing, and state-machine replacement. The MAX 7000 family uses Altera's second-generation MAX architecture, which adds fast input registers, programmable interconnect, and four dedicated Logic Array Blocks (LABs) per device for deterministic, pin-locked timing. Key features include 64 macrocells across 4 Logic Array Blocks, 36 usable I/O pins, 5.0-V in-system programmability via JTAG, an internal 3.3-V PCI-compliant output drive option, and a programmable power-saving mode that reduces typical Icc standby to a fraction of active current. The EPM7160ELC84-15 is offered in the 84-pin PLCC (J-lead) package, providing easy prototyping on traditional through-hole PLCC sockets and reliable surface-mount assembly on J-lead land patterns. The architecture partitions logic into LABs, each containing 16 macrocells with a programmable AND array feeding a fixed OR term, a flip-flop, and product-term allocation. This produces consistent, jitter-free combinatorial and registered propagation delays ideal for address decoding, interrupt control, peripheral bridging, and synchronous state machines. The 15-ns pin-to-pin delay translates to a maximum counter frequency of 76.9 MHz at 5 V. Typical applications include bus-interface and address decoding in legacy 5-V systems, peripheral glue logic replacement for discrete 74LS/74HC TTL, industrial control and instrumentation, telecommunications line cards, and military/aerospace systems requiring non-volatile EEPROM-based logic. The wide 5-V tolerance and JTAG ISP make it well suited for both new designs and long-life maintenance of installed equipment. When designing with this part, ensure your supply is 5 V (the 'E' suffix indicates the 5-V commercial-temp variant). Drive unused I/O pins to a defined state through software to minimize Icc, and use the JTAG boundary-scan chain to simplify board test. Designers migrating from 74LS/74HC logic should target the macrocell-limited MAX 7000S variants (e.g. EPM7160SLC84-10) when in-system programmability is required.