EPM7128SQC160-15N - 128-Macro 15ns CPLD MAX 7000 | Intel / Altera
部品番号: EPM7128SQC160-15N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $44.11 | $44.11 |
| 10 | $39.7 | $397.00 |
| 100 | $33.1 | $3,310.00 |
| 500 | $27.6 | $13,800.00 |
| 1,000 | $23 | $23,000.00 |
EPM7128SQC160-15N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the instant-on characteristics of PAL/GAL architecture with the density of a small FPGA. Within the broader programmable-logic taxonomy, CPLDs sit between discrete PALs (small, simple, fast) and FPGAs (large, register-rich, SRAM-based). The MAX 7000 family was Altera's second-generation CPLD architecture (succeeding the classic MAX 5000/9000) and introduced the multi-matrix interconnect plus ISP (in-system programmability) via JTAG, features that made it the de-facto industry standard for glue logic from the mid-1990s onward.
Key features of the EPM7128SQC160-15N include 128 macrocells arranged in 8 logic array blocks (LABs), 100 user I/O pins, 15ns combinatorial propagation delay, a maximum internal counter frequency of 76.9 MHz, and 5V-tolerant I/O supporting both 3.3V and 5V mixed-voltage systems. The device is non-volatile (EEPROM-based) so the configuration is retained without an external boot PROM, and it supports in-system programming via the JTAG-compatible 4-pin interface. Programmable interconnect allows wide AND-OR logic functions across LABs with predictable timing.
The architecture uses Altera's classic MAX (Multiple Array matriX) routing structure: each LAB contains 16 macrocells that share a programmable interconnect array, and LABs communicate through the PIA (Programmable Interconnect Array). This gives the EPM7128SQC160-15N deterministic, pin-locked timing that does not change with routing density - a property that distinguishes CPLDs from SRAM-based FPGAs where delay varies with placement.
Typical applications include bus-interface bridging (PCI/ISA glue logic), address decoding and chip-select generation, power-up sequencing and reset distribution, motor control peripheral logic, industrial PLC I/O expansion, and replacement of multiple discrete TTL/CMOS logic packages. The wide 5V I/O tolerance is especially valued when interfacing legacy microcontrollers or bus transceivers to modern 3.3V ASICs.
When designing with this device, note that the PQFP-160 footprint has longer lead lengths than modern BGA/QFN packages, which limits high-speed signal edge rates above ~50 MHz. For new designs above 100 MHz I/O, consider migrating to a MAX V, MAX 10, or MAX II CPLD in a smaller QFN package while preserving the MAX 7000 logic architecture.
This page synthesizes distributor pricing, SameFrame-pinout drop-in alternatives, and practical glue-logic design notes not found in the original 1998-vintage datasheet.
ドロップイン代替品: EPM7128SQC160-15N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM7128SQC160-15N （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Supply Voltage (VCCINT), Logic Array Blocks (LABs), Usable Gates.
クイック比較ツール — 並列比較する代替部品を選択:
EPM7128SQC160-15
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EPM7128SQC160-10
✅ ドロップイン✓ 在庫あり
$14.2 / 個
データシートを見る →EPM7128SQC160-10N
✅ ドロップイン✓ 在庫あり
$9.2 / 個
データシートを見る →EPM7128SQC100-15
✅ ドロップイン✓ 在庫あり
$8.2 / 個
データシートを見る →EPM7128SQC160-15N 最大定格＆電気的特性
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 7000 |
| Macro Cells | 128 |
| Logic Array Blocks (LABs) | 8 |
| User I/O Count | 100 |
| Usable Gates | 2.5K |
| Propagation Delay (tPD) | 15 ns |
| Maximum Internal Frequency | 76.9 MHz |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage Tolerance | 3.3 V / 5 V mixed |
| Programming Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG-compatible) |
| パッケージ | 160-pin PQFP / BQFP (Plastic Quad Flat Pack) |
| 実装タイプ | Surface Mount |
| 動作温度 | 0°C to +70°C (commercial) |
EPM7128SQC160-15N ピン構成
| ピン 1 | I/O — User I/O pin (function per design) |
| ピン 2 | I/O — User I/O pin (function per design) |
| ピン 3 | I/O — User I/O pin (function per design) |
| ピン 4 | I/O — User I/O pin (function per design) |
| ピン 5 | I/O — User I/O pin (function per design) |
| ピン 6 | I/O — User I/O pin (function per design) |
| ピン 7 | I/O — User I/O pin (function per design) |
| ピン 8 | I/O — User I/O pin (function per design) |
| ピン 9 | I/O — User I/O pin (function per design) |
| ピン 10 | I/O — User I/O pin (function per design) |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O pin (function per design) |
| ピン 13 | I/O — User I/O pin (function per design) |
| ピン 14 | I/O — User I/O pin (function per design) |
| ピン 15 | I/O — User I/O pin (function per design) |
| ピン 16 | I/O — User I/O pin (function per design) |
| ピン 17 | I/O — User I/O pin (function per design) |
| ピン 18 | I/O — User I/O pin (function per design) |
| ピン 19 | I/O — User I/O pin (function per design) |
| ピン 20 | I/O — User I/O pin (function per design) |
| ピン 21 | GND — Ground |
| ピン 22 | I/O — User I/O pin (function per design) |
| ピン 23 | I/O — User I/O pin (function per design) |
| ピン 24 | I/O — User I/O pin (function per design) |
| ピン 25 | I/O — User I/O pin (function per design) |
| ピン 26 | I/O — User I/O pin (function per design) |
| ピン 27 | I/O — User I/O pin (function per design) |
| ピン 28 | I/O — User I/O pin (function per design) |
| ピン 29 | I/O — User I/O pin (function per design) |
| ピン 30 | I/O — User I/O pin (function per design) |
| ピン 31 | GND — Ground |
| ピン 32 | I/O — User I/O pin (function per design) |
| ピン 33 | I/O — User I/O pin (function per design) |
| ピン 34 | I/O — User I/O pin (function per design) |
| ピン 35 | I/O — User I/O pin (function per design) |
| ピン 36 | I/O — User I/O pin (function per design) |
| ピン 37 | I/O — User I/O pin (function per design) |
| ピン 38 | I/O — User I/O pin (function per design) |
| ピン 39 | I/O — User I/O pin (function per design) |
| ピン 40 | I/O — User I/O pin (function per design) |
| ピン 41 | GND — Ground |
| ピン 42 | I/O — User I/O pin (function per design) |
| ピン 43 | I/O — User I/O pin (function per design) |
| ピン 44 | I/O — User I/O pin (function per design) |
| ピン 45 | I/O — User I/O pin (function per design) |
| ピン 46 | I/O — User I/O pin (function per design) |
| ピン 47 | I/O — User I/O pin (function per design) |
| ピン 48 | I/O — User I/O pin (function per design) |
| ピン 49 | I/O — User I/O pin (function per design) |
| ピン 50 | I/O — User I/O pin (function per design) |
| ピン 51 | GND — Ground |
| ピン 52 | I/O — User I/O pin (function per design) |
| ピン 53 | I/O — User I/O pin (function per design) |
| ピン 54 | I/O — User I/O pin (function per design) |
| ピン 55 | I/O — User I/O pin (function per design) |
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| ピン 57 | I/O — User I/O pin (function per design) |
| ピン 58 | I/O — User I/O pin (function per design) |
| ピン 59 | I/O — User I/O pin (function per design) |
| ピン 60 | I/O — User I/O pin (function per design) |
| ピン 61 | GND — Ground |
| ピン 62 | I/O — User I/O pin (function per design) |
| ピン 63 | I/O — User I/O pin (function per design) |
| ピン 64 | I/O — User I/O pin (function per design) |
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| ピン 69 | I/O — User I/O pin (function per design) |
| ピン 70 | I/O — User I/O pin (function per design) |
| ピン 71 | GND — Ground |
| ピン 72 | I/O — User I/O pin (function per design) |
| ピン 73 | I/O — User I/O pin (function per design) |
| ピン 74 | I/O — User I/O pin (function per design) |
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| ピン 79 | I/O — User I/O pin (function per design) |
| ピン 80 | I/O — User I/O pin (function per design) |
| ピン 81 | GND — Ground |
| ピン 82 | I/O — User I/O pin (function per design) |
| ピン 83 | I/O — User I/O pin (function per design) |
| ピン 84 | I/O — User I/O pin (function per design) |
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| ピン 88 | I/O — User I/O pin (function per design) |
| ピン 89 | I/O — User I/O pin (function per design) |
| ピン 90 | I/O — User I/O pin (function per design) |
| ピン 91 | GND — Ground |
| ピン 92 | I/O — User I/O pin (function per design) |
| ピン 93 | I/O — User I/O pin (function per design) |
| ピン 94 | I/O — User I/O pin (function per design) |
| ピン 95 | I/O — User I/O pin (function per design) |
| ピン 96 | I/O — User I/O pin (function per design) |
| ピン 97 | I/O — User I/O pin (function per design) |
| ピン 98 | I/O — User I/O pin (function per design) |
| ピン 99 | I/O — User I/O pin (function per design) |
| ピン 100 | I/O — User I/O pin (function per design) |
| ピン 101 | GND — Ground |
| ピン 102 | I/O — User I/O pin (function per design) |
| ピン 103 | I/O — User I/O pin (function per design) |
| ピン 104 | I/O — User I/O pin (function per design) |
| ピン 105 | I/O — User I/O pin (function per design) |
| ピン 106 | I/O — User I/O pin (function per design) |
| ピン 107 | I/O — User I/O pin (function per design) |
| ピン 108 | I/O — User I/O pin (function per design) |
| ピン 109 | I/O — User I/O pin (function per design) |
| ピン 110 | I/O — User I/O pin (function per design) |
| ピン 111 | GND — Ground |
| ピン 112 | I/O — User I/O pin (function per design) |
| ピン 113 | I/O — User I/O pin (function per design) |
| ピン 114 | I/O — User I/O pin (function per design) |
| ピン 115 | I/O — User I/O pin (function per design) |
| ピン 116 | I/O — User I/O pin (function per design) |
| ピン 117 | I/O — User I/O pin (function per design) |
| ピン 118 | I/O — User I/O pin (function per design) |
| ピン 119 | I/O — User I/O pin (function per design) |
| ピン 120 | I/O — User I/O pin (function per design) |
| ピン 121 | GND — Ground |
| ピン 122 | I/O — User I/O pin (function per design) |
| ピン 123 | I/O — User I/O pin (function per design) |
| ピン 124 | I/O — User I/O pin (function per design) |
| ピン 125 | I/O — User I/O pin (function per design) |
| ピン 126 | I/O — User I/O pin (function per design) |
| ピン 127 | I/O — User I/O pin (function per design) |
| ピン 128 | I/O — User I/O pin (function per design) |
| ピン 129 | I/O — User I/O pin (function per design) |
| ピン 130 | I/O — User I/O pin (function per design) |
| ピン 131 | GND — Ground |
| ピン 132 | I/O — User I/O pin (function per design) |
| ピン 133 | I/O — User I/O pin (function per design) |
| ピン 134 | I/O — User I/O pin (function per design) |
| ピン 135 | I/O — User I/O pin (function per design) |
| ピン 136 | I/O — User I/O pin (function per design) |
| ピン 137 | I/O — User I/O pin (function per design) |
| ピン 138 | I/O — User I/O pin (function per design) |
| ピン 139 | I/O — User I/O pin (function per design) |
| ピン 140 | I/O — User I/O pin (function per design) |
| ピン 141 | GND — Ground |
| ピン 142 | I/O — User I/O pin (function per design) |
| ピン 143 | I/O — User I/O pin (function per design) |
| ピン 144 | I/O — User I/O pin (function per design) |
| ピン 145 | I/O — User I/O pin (function per design) |
| ピン 146 | I/O — User I/O pin (function per design) |
| ピン 147 | I/O — User I/O pin (function per design) |
| ピン 148 | I/O — User I/O pin (function per design) |
| ピン 149 | I/O — User I/O pin (function per design) |
| ピン 150 | I/O — User I/O pin (function per design) |
| ピン 151 | TDI — JTAG Test Data In (dedicated) |
| ピン 152 | TMS — JTAG Test Mode Select (dedicated) |
| ピン 153 | TCK — JTAG Test Clock (dedicated) |
| ピン 154 | I/O — User I/O pin (function per design) |
| ピン 155 | I/O — User I/O pin (function per design) |
| ピン 156 | I/O — User I/O pin (function per design) |
| ピン 157 | I/O — User I/O pin (function per design) |
| ピン 158 | I/O — User I/O pin (function per design) |
| ピン 159 | TDO — JTAG Test Data Out (dedicated) |
| ピン 160 | VCC — Core + I/O supply (5 V) |
主な用途
EPM7128SQC160-15N の用途: 7 件s: PCI / ISA Bus Glue Logic, Address Decoding & Chip-Select Generation, Power-Up Sequencing & Reset Distribution, Motor Control Peripheral Logic, Industrial PLC I/O Expansion, Legacy TTL / CMOS Logic Replacement, Embedded System Peripheral Bridging.
PCI / ISA Bus Glue Logic
The EPM7128SQC160-15N fits PCI/ISA bus glue-logic roles because its 128 macrocells provide ample AND-OR decoding capacity for chip-select generation, address decoding, and bus-cycle control. Its 15 ns tPD comfortably meets the 33 MHz PCI clock-to-output timing (minimum 30 ns cycle budget allows ~15 ns combinational delay), and the 100 user I/Os support the wide bus and interrupt/grant signals of legacy PC architectures. The non-volatile EEPROM configuration eliminates boot-PROM overhead - critical for instant-on BIOS extension ROMs and adapter cards. Compared to discrete 74LS/74FTTL gates, a single EPM7128SQC160-15N replaces dozens of packages, reducing PCB area and BOM cost while preserving deterministic, pin-locked timing.
おすすめ
Address Decoding & Chip-Select Generation
The EPM7128SQC160-15N is widely deployed as an address decoder in microcontroller and embedded systems. Its wide AND-OR product-term architecture can decode large address ranges - up to the full 24- or 32-bit address space - in a single device, producing chip-select strobes for memory banks, peripherals, and I/O expanders. The 15 ns propagation delay ensures chip-selects are valid before the CPU's first memory-access cycle, eliminating wait-state insertion. Non-volatile EEPROM programming means the decoding map is fixed at power-up with no bootloader overhead. Compared to discrete 74HC138/139 decoders, the CPLD approach supports custom, non-power-of-two decode regions and reduces part count.
おすすめ
Power-Up Sequencing & Reset Distribution
Power-up sequencing in multi-rail systems benefits from the EPM7128SQC160-15N's deterministic timing and instant-on behavior. The MAX 7000S EEPROM configuration is valid within microseconds of VCC ramp, allowing the CPLD to drive early-stage enables such as the core voltage regulator's PG (Power Good) handshakes before the main CPU resets. With 100 I/Os, it can fan out independent reset and enable signals to multiple ASICs, FPGAs, and analog rails, each gated by its own programmable time delay built from internal macrocell counters. The 5V-tolerant I/O and 3.3V/5V mixed-voltage support make it ideal for sequencing mixed-voltage boards. This usage remains common in industrial PLC backplanes and telecom line cards.
おすすめ
Motor Control Peripheral Logic
Industrial motor drives use the EPM7128SQC160-15N as peripheral glue between a microcontroller/DSP and the power stage. Typical functions include PWM dead-time insertion, fault-input synchronization, encoder quadrature decoding, and gate-driver enable logic - all of which require deterministic, sub-microsecond timing that the 15 ns tPD comfortably provides. The 100 user I/Os interface to multiple Hall-effect sensors, encoder channels, and isolated gate drivers, while the 5V-tolerant I/O directly accepts 5V Hall/encoder signals without level shifters. The non-volatile EEPROM configuration survives factory-programmed motor profiles that must persist across power cycles. The MAX 7000S SameFrame footprint lets designers migrate to higher-density 256-macrocell MAX 7000S parts as control complexity grows.
おすすめ
Industrial PLC I/O Expansion
PLC backplanes use the EPM7128SQC160-15N as a flexible I/O expansion and isolation interface between the central processor and field-side drivers. Its 100 user I/Os can scan a multi-module backplane, debounce mechanical contacts in hardware (via macrocell flip-flops), and present a clean register-mapped interface to the CPU. The EEPROM-based configuration lets OEMs re-flash I/O maps via JTAG without changing firmware, accelerating line-rebuild. The 5V-tolerant I/O tolerates noisy 24V field-side signals after simple resistive dividers. Industrial customers value the part's long lifecycle, wide operating range, and SameFrame migration path, even though the silicon is NRD.
おすすめ
Legacy TTL / CMOS Logic Replacement
A classic use of the EPM7128SQC160-15N is consolidating dozens of discrete 74LS/74HC/74FTTL packages into a single programmable device, simplifying PCB layout and BOM. Its 128 macrocells typically replace 20-40 SSI/MSI packages while preserving exact logic function and timing. This reduces PCB layer count, assembly cost, and test time. The 5V I/O is directly compatible with legacy TTL thresholds, eliminating level translation. This use case is especially valuable in aerospace, defense, and industrial OEMs maintaining production of legacy systems where re-spinning a board for a different CPLD family would require re-certification. The EEPROM configuration is also more reliable than soldered-in discrete logic.
おすすめ
Embedded System Peripheral Bridging
Bridging mismatched peripherals - for example, an 8-bit microcontroller to a 16-bit LCD bus, or a SPI master to a parallel ADC - is a natural fit for the EPM7128SQC160-15N. With 128 macrocells, the CPLD can implement protocol converters, bus-width adapters, and FIFO-like flow-control logic with deterministic timing. The 15 ns tPD easily keeps up with typical 8- and 16-bit microcontroller peripheral speeds (tens of MHz), and the 100 I/Os provide ample headroom for parallel buses. The non-volatile configuration means the bridge starts working at first power-up, even before the main CPU boots. This pattern is common in custom instrumentation and medical-device embedded boards.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM7128SQC160-15N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM7128SQC160-15 | EPM7128SQC160-10 | EPM7128SQC160-10N | EPM7128SQC100-15 |
|---|---|---|---|---|---|
| Package | PQFP-160 | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same |
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S |
| Macro Cells | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 15 ns | 15 ns | 10 ns | 10 ns | 15 ns |
| Lead-Free (N suffix) | Yes (N-suffix) | No (legacy leaded) | No (legacy leaded) | Yes (N-suffix) | No (legacy leaded) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
主な差別化要因
- Wide 5V-tolerant I/O with 3.3V/5V mixed-voltage support （vs MAX V CPLDs (e.g., 5M160ZE64))
- Non-volatile EEPROM configuration - instant-on at power-up （vs SRAM-based FPGAs (e.g., Cyclone))
- SameFrame pinout across density and package options （vs Discrete 74LS/74F TTL logic)
- Deterministic, pin-locked timing independent of routing density （vs ispMACH 4000 (Lattice))
設計ノート
PQFP-160 packages have long lead lengths (~3 mm) and significant lead inductance. Place at least one 0.1 µF decoupling capacitor per VCC pin, within 5 mm of the package body. Use a continuous ground plane on the layer directly beneath the CPLD to control return-current paths and EMI. Avoid routing high-speed signals (>50 MHz) under the PQFP body to limit crosstalk into the device's analog substrate.
Each EPM7128SQC160-15N user I/O can source/sink up to 25 mA DC and supports 5V TTL thresholds. When driving long PCB traces or cables, add a 33 Ω series resistor near the CPLD pin to dampen ringing. Inputs from noisy buses should be filtered with a 100 ns RC network or a Schmitt-trigger input buffer. Do not exceed the absolute maximum DC input voltage of 7V; undershoot below -2V for >100 mA / >20 ns is also prohibited.
Do not confuse the speed-grade suffix: -10 / -10N are faster than -15N. Note that VCC must rise monotonically for EPM7128A / EPM7256A devices only - this constraint does NOT apply to the non-A MAX 7000S EPM7128SQC160-15N. For ISP via JTAG, ensure TCK is not floating during board power-up; tie TCK to GND through a 10 kΩ pull-down. Always re-verify the configuration after reflow because EEPROM retention is sensitive to thermal exposure above 150 °C.
The PQFP-160 package has a thermal resistance (θJA) of approximately 35-40 °C/W on a standard 4-layer PCB. The EPM7128SQC160-15N typically dissipates 0.5-1.5 W depending on toggle frequency and IO loading. Estimate: at full 76.9 MHz toggle with 100 I/Os at 20 pF each, ICC ≈ 150-300 mA and P ≈ 0.75-1.5 W, giving a junction rise of ~30-60 °C above ambient. Ensure ambient remains below 70 °C to keep Tj within the 125 °C commercial limit.
コンプライアンス情報
RoHS, REACH, halogen-free, and conflict-minerals status are not explicitly stated in the verified web data; marked unknown. The N suffix indicates lead-free build. AEC-Q100 not applicable - this is a commercial-grade CPLD, not an automotive-qualified part.
