EPM7128SQI160-10 - 128-Macrocell MAX 7000S CPLD, 10ns, PQFP-160 | Intel
部品番号: EPM7128SQI160-10 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $33.2 | $332.00 |
| 100 | $27.85 | $2,785.00 |
| 500 | $23.1 | $11,550.00 |
| 1,000 | $19.95 | $19,950.00 |
EPM7128SQI160-10 概要
A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with higher density. In the system hierarchy, a CPLD sits below FPGAs in logic capacity but above discrete glue logic in integration, providing fast, deterministic I/O-to-I/O timing for address decoding, bus interfacing, state-machine control, and peripheral bridging. MAX 7000S devices use EEPROM-based configuration cells, so they are instantly programmable in-system via JTAG (IEEE 1149.1) and retain their configuration without external memory.
Key features include in-system programmability (ISP) through the 4-wire JTAG interface, 100% routability with predictable timing, programmable macrocell flip-flops with individual clear, preset, clock, and clock-enable controls, open-drain output option, and a multi-volt I/O interface supporting 3.3 V or 5 V operation from a 5 V VCCINT supply. Each macrocell contains a programmable AND/OR/expander-array logic block with a configurable flip-flop. The device also supports a global clock network, four dedicated inputs, security-bit protection for the configuration, and an enhanced JTAG instruction set.
Architecturally, the EPM7128SQI160-10 organizes its 128 macrocells into four Logic Array Blocks (LABs) of 16 macrocells each, interconnected through the Programmable Interconnect Array (PIA). Each I/O pin has an associated I/O control block providing slew-rate control, tri-state buffering, and a programmable pull-up resistor. The EEPROM-based Look-Up Tables (LUTs) and product-term arrays produce deterministic combinational and sequential logic with no hidden routing delays.
Typical applications include bus-interface glue logic, address decoding for microprocessors and DSPs, peripheral controllers, state-machine implementation, power-up sequencing logic, JTAG-driven board-test infrastructure, and legacy 5V industrial control designs. The wide PQFP-160 package offers 100+ user I/O pins, making it suitable as a system-level glue-logic hub replacing multiple 22V10-style SPLDs.
When designing with this device, the user must supply a stable 5 V VCCINT and observe the JTAG programming voltages. Quartus II or MAX+PLUS II software is used for design entry, synthesis, place-and-route, and device programming. Place decoupling capacitors (0.1 uF and 10 uF) close to every VCC and GND pin pair.
This page synthesizes distributor pricing, pin-compatible same-family alternatives, and design guidance not found on standard manufacturer listings, giving engineers a single consolidated reference for the EPM7128SQI160-10.
ドロップイン代替品: EPM7128SQI160-10 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM7128SQI160-10 （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Usable Gates, Configuration Memory, Programming Interface.
クイック比較ツール — 並列比較する代替部品を選択:
EPM7128SQC160-10
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$14.2 / 個
データシートを見る →EPM7128SQC160-10N
✅ ドロップイン✓ 在庫あり
$9.2 / 個
データシートを見る →EPM7128SQC160-15
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.95 / 個
データシートを見る →EPM7128SQC160-15N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$23 / 個
データシートを見る →EPM7128SQC160-6
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$11.1 / 個
データシートを見る →EPM7128EQC160-10
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EPM7128SQI160-10 最大定格＆電気的特性
| Family | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Logic Elements / Gates | 2.5K equivalent gates |
| Propagation Delay (tPD) | 10 ns |
| Maximum Frequency | 100 MHz |
| Logic Blocks (LABs) | 4 (16 macrocells each) |
| User I/O Pins | 100 (approx., PQFP-160) |
| Supply Voltage VCCINT | 5 V |
| I/O Voltage Tolerance | 3.3 V / 5 V multi-volt interface |
| Process Technology | CMOS, EEPROM-based configuration |
| パッケージ | PQFP-160 (Plastic Quad Flat Pack) |
| 実装タイプ | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Operating Temperature Grade | Industrial (-40C to +85C) |
| Configuration Memory | EEPROM (non-volatile, instant-on) |
EPM7128SQI160-10 pqfp-160 (plastic quad flat pack) ピン配置ガイド
EPM7128SQI160-10 (pqfp-160 (plastic quad flat pack) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EPM7128SQI160-10.
詳細は データシート をご参照ください。
主な用途
EPM7128SQI160-10 の用途: 6 件s: Microprocessor Address Decoding, Bus Interface and Glue Logic, State Machine and Sequential Control, Power-Up Sequencing and Reset Control, Peripheral Controllers (UART, SPI, I2C Bridges), Legacy Industrial and Test Equipment.
Microprocessor Address Decoding
The EPM7128SQI160-10 is widely used as a high-density address decoder for 8/16/32-bit microprocessor and DSP systems. Its 128 macrocells can decode multiple bank selects, chip-enable signals, and memory-mapped peripheral enables simultaneously, replacing stacks of discrete 22V10 SPLDs or 74LS-series TTL glue logic. The 10 ns tPD plus the 100 MHz maximum counter frequency comfortably meet the timing requirements of legacy 5V 8086, 68k, and early ARM7 buses. Quartus II fits the decoded equations into 4 LABs and routes them through the PIA with deterministic timing, eliminating race conditions.
おすすめ
Bus Interface and Glue Logic
The 160-pin PQFP package provides approximately 100 user I/O pins, making the EPM7128SQI160-10 an ideal glue-logic hub between microprocessors, memory, and peripherals. Engineers routinely implement level shifters between 5V and 3.3V domains, parallel-to-serial converters, FIFO controllers, and interrupt arbiters in a single chip. The multi-volt I/O pins handle both 3.3V and 5V signaling, eliminating external level-translator ICs on mixed-voltage boards. JTAG boundary-scan support enables board-level interconnect testing, critical for high-density PCBs where bed-of-nails fixtures are impractical.
おすすめ
State Machine and Sequential Control
Each of the 128 macrocells includes a programmable flip-flop with dedicated clear, preset, clock, and clock-enable controls, making the EPM7128SQI160-10 well suited to multi-state sequential control logic. Typical applications include motor-control state machines, vending-machine controllers, traffic-light sequencers, and protocol-state engines for UARTs, SPI, and I2C master/slave controllers. The 100 MHz global clock network feeds every macrocell flip-flop, allowing complex state machines to operate at full speed without skew issues. Design entry via state-machine diagrams in Quartus II produces compact, optimized state encoding.
おすすめ
Power-Up Sequencing and Reset Control
Because the EPM7128SQI160-10 is EEPROM-based, it is fully configured and operational within microseconds of VCC ramp - ideal for generating power-rail enable signals and reset pulses during system startup. Multi-rail power-supply designs for FPGAs, ASICs, and DSPs require precise sequencing (1.0V, then 1.8V, then 3.3V) to prevent latch-up. Engineers implement 8 to 16-channel sequencers with adjustable delays, watchdog timers, and brown-out detectors in a single EPM7128SQI160-10, replacing discrete supervisor ICs and RC delay networks. Industrial-grade temperature range ensures reliable sequencing in harsh environments.
おすすめ
Peripheral Controllers (UART, SPI, I2C Bridges)
The 128 macrocells and 100 user I/Os of the EPM7128SQI160-10 comfortably host soft UARTs, SPI master/slaves, I2C controllers, and parallel-to-LCD bridges. The 100 MHz fCNT plus JTAG-style debugging lets engineers iterate quickly on legacy peripheral glue where off-the-shelf controllers are unavailable. Multi-drop bus arbitration, addressable UART muxes, and custom serial protocols all fit within a single device. The 5V VCCINT requirement matches legacy industrial and military embedded systems.
おすすめ
Legacy Industrial and Test Equipment
The EPM7128SQI160-10 has decades of deployment history in industrial control, automated test equipment (ATE), and military/aerospace systems, where long-life-cycle support outweighs the cost premium of newer devices. Its 5V tolerance, EEPROM non-volatility, and -40C to +85C industrial temperature grade make it a drop-in solution for extending the life of legacy systems that cannot be redesigned. JTAG boundary-scan simplifies board-level testing in high-density ATE pin-electronics, and the deterministic timing model ensures repeatable production behavior across decades of field deployment.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM7128SQI160-10 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM7128SQC160-10 | EPM7128SQC160-10N | EPM7128SQC160-15 | EPM7128SQC160-15N | EPM7128SQC160-6 | EPM7128EQC160-10 |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | PQFP-160 | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 10 ns | 15 ns (-50% slower) | 15 ns (-50% slower) | 6 ns (faster) | 10 ns |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) |
| Family Variant | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000E (enhanced) |
| Supply Voltage (VCCINT) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Approx. Unit Price (USD, qty 100) | 27.85 | 26.50 | 29.20 | 24.10 | 26.80 | 31.50 | 32.40 |
主な差別化要因
- Industrial temperature grade (-40C to +85C) versus commercial variants （vs EPM7128SQC160-10)
- 10 ns speed grade balances timing margin and unit cost （vs EPM7128SQC160-15)
- MAX 7000S base variant versus enhanced MAX 7000E features （vs EPM7128EQC160-10)
設計ノート
The EPM7128SQI160-10 requires a stable 5 V ±5% VCCINT supply and supports 3.3 V or 5 V signaling on I/O pins via the multi-volt interface. Decoupling must include one 0.1 uF X7R ceramic capacitor per VCC/GND pin pair placed within 3 mm of the package, plus a single 10 uF tantalum or ceramic bulk capacitor near the PQFP-160 body. Estimated: ICC at typical 25 MHz operation is ~150 mA; at full 100 MHz fCNT with all I/O toggling, ICC may reach ~250 mA. Add bulk decoupling sized for the highest transient current expected.
Route JTAG signals (TCK, TMS, TDI, TDO) as a 4-wire daisy-chain with TCK length-matched across all JTAG devices on the board. Place a 10 kohm pull-up on TCK, TMS, and TDI, and add 33 ohm series-termination near the JTAG connector to suppress ringing. The 160-pin PQFP has a 0.65 mm pitch and a low lead coplanarity tolerance - use 0.10 mm thick solder paste with a Type 3 or Type 4 powder, and reflow with a ramp rate of 1-3 C/s above the liquidus line. Confirm lead-free reflow profile compatibility if using the EPM7128SQC160-10N Pb-free variant.
Do not exceed 5.5 V on VCCINT or apply power before JTAG pins are driven to a defined state. Ensure unused I/O pins are configured as outputs with low drive, or as inputs with the internal pull-up enabled - floating inputs can cause ICC creep and oscillator-like behavior in the input buffer. Estimated: each floating input can add 0.5 mA of supply current; with 100 I/O pins the cumulative effect can reach 50 mA. The MAX 7000S JTAG instruction set supports EXTEST, BYPASS, SAMPLE/PRELOAD, IDCODE, and ISP_ENABLE - do not assert ISP_ENABLE during normal operation as it will reconfigure the device.
コンプライアンス情報
RoHS/REACH compliance status not explicitly listed in the verified web data. EPM7128SQI160-10 is the original Altera-branded (pre-Intel-acquisition) part - RoHS-compliant 'N' suffix variants exist (EPM7128SQI160-10N) for lead-free requirements.
