EPM7128SQC160-10N - 128-Macrocell MAX 7000 CPLD, 100MHz | Intel
部品番号: EPM7128SQC160-10N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.2 | $132.00 |
| 100 | $11.85 | $1,185.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.2 | $9,200.00 |
EPM7128SQC160-10N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile, flash/EEPROM-based programmable logic device that combines the deterministic timing of PAL/GAL architectures with higher logic density. It sits hierarchically below an FPGA but above simple PLDs in the programmable logic taxonomy: CPLD -> PLD -> programmable logic -> semiconductor. Compared to FPGAs, CPLDs offer instant-on configuration, predictable timing, and lower power for moderate-density glue logic.
Key features include 128 macrocells (each with 36 product terms), 5V core supply, in-system programmability via JTAG (IEEE 1149.1), and built-in JTAG boundary-scan test circuitry on MAX 7000S devices with 128 or more macrocells. The 5-ns pin-to-pin logic delays and 175.4-MHz counter frequencies make the EPM7128SQC160-10N a strong fit for bus-interface bridging and address decoding in legacy 5V systems.
The MAX 7000 architecture employs a second-generation MAX fabric with a global interconnect matrix, programmable interconnect array (PIA), and per-macrocell flip-flops. CMOS EEPROM technology stores configuration non-volatilely, so the device powers up in a known state with no external boot PROM, a defining advantage over SRAM-based FPGAs in deterministic boot applications.
Typical applications include PCI/ISA bus interface logic, address decoding, glue logic for microprocessors, state-machine control, and 5V system prototyping. It is also used in industrial controllers, telecom backplane glue logic, and legacy system upgrades where 5V tolerance is mandatory.
When designing, note that this part is in the MAX 7000 family and shares the classic Altera ByteBlaster/USB-Blaster programming flow via JTAG. Decoupling: place 0.1 uF and 10 uF caps near each supply pin pair to keep the global interconnect matrix quiet during simultaneous switching.
This page synthesizes distributor pricing, same-family MAX 7000 drop-in alternatives (including speed-grade and temperature-grade variants), and practical design notes not found in the original manufacturer datasheet.
ドロップイン代替品: EPM7128SQC160-10N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM7128SQC160-10N （同一形状・フットプリント） — 相違点: Package, Usable Gates, Operating Temperature, Supply Voltage (VCCINT), Logic Array Blocks (LABs).
クイック比較ツール — 並列比較する代替部品を選択:
EPM7128SQC160-10
✅ ドロップイン✓ 在庫あり
$14.2 / 個
データシートを見る →EPM7128SQC160-10YY
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM7128SQC160-10ES
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM7128SQC160-10F
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM7128SQI160-10N
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM7128SQC160-10N 最大定格＆電気的特性
| Family | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| User I/Os | 100 |
| Logic Elements | 160 LE (per datasheet macrocell blocks) |
| Supply Voltage (VCCINT) | 5 V |
| Operating Frequency (Counter) | 100 MHz |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Counter Frequency (fCNT) | 175.4 MHz |
| Programming Technology | EEPROM (non-volatile) |
| JTAG Support | Yes (IEEE 1149.1 BST) |
| In-System Programmable | Yes |
| パッケージ | 160-pin PQFP |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (industrial, N suffix) |
| Speed Grade | -10 (10 ns pin-to-pin) |
EPM7128SQC160-10N ピン構成
| ピン 1 | INPUT/GCLK1 — Global clock 1 / dedicated input |
| ピン 2 | I/O — User I/O (bank 1) |
| ピン 3 | I/O — User I/O (bank 1) |
| ピン 4 | I/O — User I/O (bank 1) |
| ピン 5 | I/O — User I/O (bank 1) |
| ピン 6 | I/O — User I/O (bank 1) |
| ピン 7 | I/O — User I/O (bank 1) |
| ピン 8 | I/O — User I/O (bank 1) |
| ピン 9 | I/O — User I/O (bank 1) |
| ピン 10 | GND — Ground |
| ピン 11 | I/O — User I/O (bank 1) |
| ピン 12 | I/O — User I/O (bank 1) |
| ピン 13 | I/O — User I/O (bank 1) |
| ピン 14 | I/O — User I/O (bank 1) |
| ピン 15 | I/O — User I/O (bank 1) |
| ピン 16 | I/O — User I/O (bank 1) |
| ピン 17 | I/O — User I/O (bank 1) |
| ピン 18 | I/O — User I/O (bank 1) |
| ピン 19 | I/O — User I/O (bank 1) |
| ピン 20 | I/O — User I/O (bank 1) |
| ピン 21 | GND — Ground |
| ピン 22 | I/O — User I/O (bank 2) |
| ピン 23 | I/O — User I/O (bank 2) |
| ピン 24 | I/O — User I/O (bank 2) |
| ピン 25 | I/O — User I/O (bank 2) |
| ピン 26 | I/O — User I/O (bank 2) |
| ピン 27 | I/O — User I/O (bank 2) |
| ピン 28 | I/O — User I/O (bank 2) |
| ピン 29 | I/O — User I/O (bank 2) |
| ピン 30 | I/O — User I/O (bank 2) |
| ピン 31 | I/O — User I/O (bank 2) |
| ピン 32 | GND — Ground |
| ピン 33 | I/O — User I/O (bank 2) |
| ピン 34 | I/O — User I/O (bank 2) |
| ピン 35 | I/O — User I/O (bank 2) |
| ピン 36 | I/O — User I/O (bank 2) |
| ピン 37 | I/O — User I/O (bank 2) |
| ピン 38 | I/O — User I/O (bank 2) |
| ピン 39 | I/O — User I/O (bank 2) |
| ピン 40 | I/O — User I/O (bank 2) |
| ピン 41 | I/O — User I/O (bank 2) |
| ピン 42 | I/O — User I/O (bank 2) |
| ピン 43 | I/O — User I/O (bank 2) |
| ピン 44 | GND — Ground |
| ピン 45 | I/O — User I/O (bank 3) |
| ピン 46 | I/O — User I/O (bank 3) |
| ピン 47 | I/O — User I/O (bank 3) |
| ピン 48 | I/O — User I/O (bank 3) |
| ピン 49 | I/O — User I/O (bank 3) |
| ピン 50 | I/O — User I/O (bank 3) |
| ピン 51 | I/O — User I/O (bank 3) |
| ピン 52 | I/O — User I/O (bank 3) |
| ピン 53 | I/O — User I/O (bank 3) |
| ピン 54 | I/O — User I/O (bank 3) |
| ピン 55 | I/O — User I/O (bank 3) |
| ピン 56 | GND — Ground |
| ピン 57 | I/O — User I/O (bank 3) |
| ピン 58 | I/O — User I/O (bank 3) |
| ピン 59 | I/O — User I/O (bank 3) |
| ピン 60 | I/O — User I/O (bank 3) |
| ピン 61 | I/O — User I/O (bank 3) |
| ピン 62 | I/O — User I/O (bank 3) |
| ピン 63 | I/O — User I/O (bank 3) |
| ピン 64 | I/O — User I/O (bank 3) |
| ピン 65 | I/O — User I/O (bank 3) |
| ピン 66 | I/O — User I/O (bank 3) |
| ピン 67 | I/O — User I/O (bank 3) |
| ピン 68 | GND — Ground |
| ピン 69 | I/O — User I/O (bank 4) |
| ピン 70 | I/O — User I/O (bank 4) |
| ピン 71 | I/O — User I/O (bank 4) |
| ピン 72 | I/O — User I/O (bank 4) |
| ピン 73 | I/O — User I/O (bank 4) |
| ピン 74 | I/O — User I/O (bank 4) |
| ピン 75 | I/O — User I/O (bank 4) |
| ピン 76 | I/O — User I/O (bank 4) |
| ピン 77 | I/O — User I/O (bank 4) |
| ピン 78 | I/O — User I/O (bank 4) |
| ピン 79 | I/O — User I/O (bank 4) |
| ピン 80 | GND — Ground |
| ピン 81 | I/O — User I/O (bank 4) |
| ピン 82 | I/O — User I/O (bank 4) |
| ピン 83 | I/O — User I/O (bank 4) |
| ピン 84 | I/O — User I/O (bank 4) |
| ピン 85 | I/O — User I/O (bank 4) |
| ピン 86 | I/O — User I/O (bank 4) |
| ピン 87 | I/O — User I/O (bank 4) |
| ピン 88 | I/O — User I/O (bank 4) |
| ピン 89 | I/O — User I/O (bank 4) |
| ピン 90 | I/O — User I/O (bank 4) |
| ピン 91 | I/O — User I/O (bank 4) |
| ピン 92 | GND — Ground |
| ピン 93 | I/O — User I/O (bank 4) |
| ピン 94 | I/O — User I/O (bank 4) |
| ピン 95 | I/O — User I/O (bank 4) |
| ピン 96 | I/O — User I/O (bank 4) |
| ピン 97 | I/O — User I/O (bank 4) |
| ピン 98 | I/O — User I/O (bank 4) |
| ピン 99 | I/O — User I/O (bank 4) |
| ピン 100 | I/O — User I/O (bank 4) |
| ピン 101 | TCK — JTAG Test Clock (IEEE 1149.1) |
| ピン 102 | TDI — JTAG Test Data In |
| ピン 103 | TMS — JTAG Test Mode Select |
| ピン 104 | VCC — 5V supply |
| ピン 105 | GND — Ground |
| ピン 106 | TDO — JTAG Test Data Out |
| ピン 107 | I/O — User I/O (bank 1) |
| ピン 108 | I/O — User I/O (bank 1) |
| ピン 109 | I/O — User I/O (bank 1) |
| ピン 110 | I/O — User I/O (bank 1) |
| ピン 111 | I/O — User I/O (bank 1) |
| ピン 112 | I/O — User I/O (bank 1) |
| ピン 113 | I/O — User I/O (bank 1) |
| ピン 114 | I/O — User I/O (bank 1) |
| ピン 115 | I/O — User I/O (bank 1) |
| ピン 116 | I/O — User I/O (bank 1) |
| ピン 117 | I/O — User I/O (bank 1) |
| ピン 118 | VCC — 5V supply |
| ピン 119 | GND — Ground |
| ピン 120 | OE1 — Global Output Enable 1 |
| ピン 121 | OE2/GCLK2 — Global Output Enable 2 / Global Clock 2 |
| ピン 122 | INPUT/GCLRn — Dedicated input / Global Clear |
| ピン 123 | INPUT/OE2n — Dedicated input / Global OE2 |
| ピン 124 | I/O — User I/O (bank 1) |
| ピン 125 | I/O — User I/O (bank 1) |
| ピン 126 | I/O — User I/O (bank 1) |
| ピン 127 | I/O — User I/O (bank 1) |
| ピン 128 | I/O — User I/O (bank 1) |
| ピン 129 | I/O — User I/O (bank 1) |
| ピン 130 | I/O — User I/O (bank 1) |
| ピン 131 | I/O — User I/O (bank 1) |
| ピン 132 | I/O — User I/O (bank 1) |
| ピン 133 | I/O — User I/O (bank 1) |
| ピン 134 | I/O — User I/O (bank 1) |
| ピン 135 | I/O — User I/O (bank 1) |
| ピン 136 | GND — Ground |
| ピン 137 | I/O — User I/O (bank 1) |
| ピン 138 | I/O — User I/O (bank 1) |
| ピン 139 | I/O — User I/O (bank 1) |
| ピン 140 | I/O — User I/O (bank 1) |
| ピン 141 | I/O — User I/O (bank 1) |
| ピン 142 | I/O — User I/O (bank 1) |
| ピン 143 | I/O — User I/O (bank 1) |
| ピン 144 | I/O — User I/O (bank 1) |
| ピン 145 | I/O — User I/O (bank 1) |
| ピン 146 | I/O — User I/O (bank 1) |
| ピン 147 | I/O — User I/O (bank 1) |
| ピン 148 | VCC — 5V supply |
| ピン 149 | GND — Ground |
| ピン 150 | I/O — User I/O (bank 2) |
| ピン 151 | I/O — User I/O (bank 2) |
| ピン 152 | I/O — User I/O (bank 2) |
| ピン 153 | I/O — User I/O (bank 2) |
| ピン 154 | I/O — User I/O (bank 2) |
| ピン 155 | I/O — User I/O (bank 2) |
| ピン 156 | I/O — User I/O (bank 2) |
| ピン 157 | I/O — User I/O (bank 2) |
| ピン 158 | I/O — User I/O (bank 2) |
| ピン 159 | I/O — User I/O (bank 2) |
| ピン 160 | I/O — User I/O (bank 2) |
主な用途
EPM7128SQC160-10N の用途: 6 件s: ISA/PCI Bus Address Decoding, Glue Logic for Microprocessor Systems, State Machine Control, Industrial Control & 5V System Prototyping, Legacy System Upgrades & Drop-In Modernization, Telecom Backplane Glue Logic.
ISA/PCI Bus Address Decoding
The EPM7128SQC160-10N is widely used for ISA and PCI bus address decoding in 5V legacy motherboards and add-in cards. Its 128 macrocells are sufficient to decode 16-bit or 32-bit address ranges with multiple chip-select outputs, while the 100 MHz counter frequency and 10 ns tPD satisfy ISA bus timing with comfortable margin. Unlike SRAM-based FPGAs, the EEPROM-backed MAX 7000 fabric boots in microseconds with no external configuration PROM, which is critical for ISA cards where BIOS enumeration must complete before the bus controller releases RESET.
おすすめ
Glue Logic for Microprocessor Systems
The EPM7128SQC160-10N excels as glue logic between microprocessors, memory, and peripherals. With 128 macrocells, designers can implement wait-state generators, interrupt arbiters, and chip-select decoding in a single 5V device. The 100 user I/Os comfortably handle 32-bit data buses plus control signals, and the deterministic 10 ns pin-to-pin delay ensures no metastability surprises. Compared to discrete 74-series TTL, the MAX 7000 reduces board area by 50-70% while remaining 5V-tolerant for direct connection to legacy microprocessors.
おすすめ
State Machine Control
The EPM7128SQC160-10N is ideal for implementing complex Moore/Mealy state machines in industrial controllers. Each macrocell contains a programmable flip-flop, allowing 128 independent state registers, while the global interconnect matrix (PIA) routes control signals with deterministic 10 ns delays. The 175.4 MHz counter frequency supports high-speed sequencing, and the non-volatile EEPROM fabric means state machines power up in a known condition - critical for safety interlocks where an SRAM-based FPGA might initialize unpredictably.
おすすめ
Industrial Control & 5V System Prototyping
The EPM7128SQC160-10N is widely used in industrial controllers and 5V system prototyping where its -40C to +85C industrial temperature range and 5V tolerance are mandatory. It handles timing-critical functions such as PWM generation, quadrature decoding, and serial-protocol bridging (RS-232/485) without needing level shifters. Designers can iterate logic via JTAG without removing the chip from the board, and the 10 ns pin-to-pin delay provides margin for cable-driver skew compensation.
おすすめ
Legacy System Upgrades & Drop-In Modernization
The EPM7128SQC160-10N serves as a drop-in modernization path for end-of-life 5V discrete logic boards. Designers can replace dozens of 74LS/74FTTL packages with one MAX 7000 part while retaining the 5V interface to upstream microprocessors. The 160-pin PQFP footprint is compatible with existing PCB layouts, and the JTAG programming chain allows rapid firmware updates without hardware rework - particularly valuable in aerospace and military retrofit programs.
おすすめ
Telecom Backplane Glue Logic
The EPM7128SQC160-10N is deployed in telecom backplanes for clock distribution, bus arbitration, and protocol bridging between legacy TDM buses and newer packet fabrics. Its 100 user I/Os comfortably handle 32-bit parallel buses plus JTAG and global clock/clear signals, while 128 macrocells implement multi-channel state machines in a single device. The non-volatile EEPROM fabric is especially valuable in central-office environments where power-cycles must result in deterministic, instant-on behavior.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM7128SQC160-10N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM7128SQC160-10 | EPM7128SQC160-10YY | EPM7128SQC160-10ES | EPM7128SQC160-10F | EPM7128SQI160-10N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | PQFP-160 | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 100 | 100 | 100 | 100 | 100 | 100 |
| Pin-to-Pin Delay | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns |
| Counter Frequency | 175.4 MHz | 175.4 MHz | 175.4 MHz | 175.4 MHz | 175.4 MHz | 175.4 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | -40C to +85C (industrial, lead-free) | -40C to +85C (engineering sample) | -40C to +85C (industrial, lead-free) | -40C to +85C (industrial) |
| RoHS Compliant | No (legacy SnPb) | No (legacy SnPb) | Yes (lead-free) | No (engineering sample) | Yes (lead-free) | No (legacy SnPb) |
主な差別化要因
- Industrial temperature grade at the standard 10 ns speed （vs EPM7128SQC160-10)
- Non-volatile EEPROM fabric - instant deterministic boot （vs EPM7128AEFC100-10 (MAX 7000A))
- Higher logic density (128 macrocells) in the same MAX 7000 family （vs EPM7128SLC84-10)
設計ノート
Estimated: at 100 MHz toggle on 32 outputs at 5V, ICC is approximately 200 mA typical and can rise to 400 mA worst-case during simultaneous switching. Place 0.1 uF + 10 uF decoupling caps adjacent to each of the four VCC pins (104, 118, 148, plus pad 1) and four GND pins (10, 21, 32, plus pad 44) to keep the global interconnect matrix quiet. The MAX 7000 is a 5V-only family - do not apply 3.3V signals directly to user I/O; use external level shifters if interfacing to modern 3.3V logic.
Route JTAG signals (TCK/TDI/TMS/TDO) in a single daisy-chain with 10K pull-ups on TCK, TDI, TMS for proper boundary-scan operation per IEEE 1149.1. Place the EPM7128SQC160-10N away from switching power converters; the PQFP-160 lead pitch is 0.5 mm, so keep high-speed traces on inner layers with a continuous ground plane on layer 2 for controlled impedance and EMI suppression.
Do not confuse the EPM7128SQC160-10N (160-pin PQFP) with the EPM7128SQC100-10N (100-pin PQFP) or the EPM7128SLC84-10 (84-pin PLCC) - these are NOT pin-compatible despite the similar prefix. When migrating from older EPM7032/EPM7064 designs, re-validate the JTAG chain order because the -10N has a different boundary-scan ID than the smaller MAX 7000 variants. For new designs in 2026, prefer the MAX II EPM570 for 3.3V core voltages.
コンプライアンス情報
EPM7128SQC160-10N is the legacy SnPb (non-lead-free) variant. Choose EPM7128SQC160-10F or EPM7128SQC160-10YY for RoHS-compliant designs. AEC-Q100 is not applicable (CPLD is not an automotive-qualified part); MAX 7000 family is not formally AEC-Q100 qualified. No REACH/CFMI statements in retrieved data.
