EP910DM-40 vs EP910DI-35 比較
詳細な並列比較: EP910DM-40 メーカー: Altera および EP910DI-35 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910DM-40 | EP910DI-35 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.00 | $35.20 |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EP910 | Altera Classic EPLD |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | 10 |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 35 ns |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| パッケージ | 40-pin Ceramic DIP (Cerdip) with UV window | CDIP-40 (Ceramic DIP with UV window) |
| 実装タイプ | Through-Hole (DIP) | Through-Hole |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| 電源電圧 | 5 V | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Usable Gates | — | 450 |
| Maximum Toggle Frequency (fCNT) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Supply Current (ICC) | — | 40 mA typical |
| Bidirectional I/O Pins | — | 20 |
| Total Pins | — | 40 |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | EPROM programmer + JEDEC fuse map |
| Erasure Method | — | UV light through quartz window |
| Logic Family | — | PAL-type AND/OR array with D flip-flops |
| Manufacturer | — | Original Altera; long-term authorized by Rochester Electronics, LLC |