EP910DM-40 vs EP910DI-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DM-40 sa pamamagitan ng Altera at EP910DI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DM-40 EP910DI-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Aktibo
Product Type UV Erasable Programmable Logic Device (EPLD) EPLD (Erasable Programmable Logic Device)
Family Altera Classic EP910 Altera Classic EPLD
Architecture PAL-type AND/OR with global programmable interconnect bus —
Macrocells 24 24
Dedicated Inputs 36 10
Dedicated Outputs 24 —
Bidirectional I/O Lines 24 —
Product Terms 240 —
Propagation Delay (tPD) 40 ns 35 ns
External Clocks 2 —
Process Technology CMOS —
Packhaging 40-pin Ceramic DIP (Cerdip) with UV window CDIP-40 (Ceramic DIP with UV window)
Uri ng Pagpapasok Through-Hole (DIP) Through-Hole
Temperature na Operasyon [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
Volte ng Pagbibigay 5 V —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified]
Programming Interface JEDEC-standard fuse-map / UV erasure —
Usable Gates — 450
Maximum Toggle Frequency (fCNT) — 28.6 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
Supply Current (ICC) — 40 mA typical
Bidirectional I/O Pins — 20
Total Pins — 40
Technology — CMOS, UV-erasable EPROM
Programming Method — EPROM programmer + JEDEC fuse map
Erasure Method — UV light through quartz window
Logic Family — PAL-type AND/OR array with D flip-flops
Manufacturer — Original Altera; long-term authorized by Rochester Electronics, LLC

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