EP910PC-15T vs EP910LC-40 比較
詳細な並列比較: EP910PC-15T メーカー: Altera および EP910LC-40 メーカー: Rochester Electronics。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Rochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 Obsolete仕様比較
| パラメータ | EP910PC-15T | EP910LC-40 |
|---|---|---|
| ブランド | Altera | Rochester Electronics |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $14.20 | $52.00 |
| Product Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD | — |
| Macrocell Count | 24 | — |
| Dedicated Input Pins | 10 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Speed Grade | -15 (15 ns) | — |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (single supply) |
| Technology | CMOS, UV-erasable / OTP | CMOS EPROM |
| パッケージ | 40-pin PDIP (Plastic DIP) | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) |
| 実装タイプ | Through-hole (DIP) | — |
| Output Drive Current | [DATA_NEEDED: IOL per output] | — |
| 動作温度 | 0C to +70C (commercial) | — |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) | — |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II | Altera Logic Programmer (PLAD-J), 4-wire serial |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | Not applicable (legacy) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Security Bit | Yes (design protection) | — |
| Tape and Reel | Yes (suffix T) | — |
| Manufacturer | — | Rochester Electronics (Altera original) |
| Device Family | — | Altera Classic EPLD - EP910 |
| Usable Gates | — | 450 |
| Macrocells | — | 24 |
| Logic Array Blocks | — | 2 (12 macrocells each) |
| Propagation Delay (tPD) | — | 40 ns |
| Maximum Toggle Frequency (fMAX) | — | 25 MHz |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 4 |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| Lead-Free Status | — | Not applicable |