EP910PC-15T vs EP910LC-40 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-15T sa pamamagitan ng Altera at EP910LC-40 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910PC-15T EP910LC-40
Brand Altera Rochester Electronics
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type EPLD (Erasable Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Family Altera Classic EPLD —
Macrocell Count 24 —
Dedicated Input Pins 10 —
Pin-to-Pin Delay (tPD) 15 ns —
Speed Grade -15 (15 ns) —
Supply Voltage (VCC) 5 V (nominal) 5 V (single supply)
Technology CMOS, UV-erasable / OTP CMOS EPROM
Packhaging 40-pin PDIP (Plastic DIP) PQCC-44 (Plastic Leaded Chip Carrier, J-lead)
Uri ng Pagpapasok Through-hole (DIP) —
Output Drive Current [DATA_NEEDED: IOL per output] —
Temperature na Operasyon 0C to +70C (commercial) —
Logic Capacity 24 macrocells / 72 product terms (typical Classic architecture) —
Programming Method JEDEC fuse map via Altera LogicMap / MAX+PLUS II Altera Logic Programmer (PLAD-J), 4-wire serial
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] Not applicable (legacy)
Lead-Free [DATA_NEEDED: lead-free status] —
Security Bit Yes (design protection) —
Tape and Reel Yes (suffix T) —
Manufacturer — Rochester Electronics (Altera original)
Device Family — Altera Classic EPLD - EP910
Usable Gates — 450
Macrocells — 24
Logic Array Blocks — 2 (12 macrocells each)
Propagation Delay (tPD) — 40 ns
Maximum Toggle Frequency (fMAX) — 25 MHz
User I/O Pins — 36
Dedicated Inputs — 4
Operating Temperature (Commercial) — 0 C to +70 C
Lead-Free Status — Not applicable

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