EP910PC-15T vs EP910LC-40 比較
詳細並排比較 EP910PC-15T 由 Altera 與 EP910LC-40 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 Obsolete規格比較
| 參數 | EP910PC-15T | EP910LC-40 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD | — |
| Macrocell Count | 24 | — |
| Dedicated Input Pins | 10 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Speed Grade | -15 (15 ns) | — |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (single supply) |
| Technology | CMOS, UV-erasable / OTP | CMOS EPROM |
| 封裝 | 40-pin PDIP (Plastic DIP) | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) |
| 安裝類型 | Through-hole (DIP) | — |
| Output Drive Current | [DATA_NEEDED: IOL per output] | — |
| 工作溫度 | 0C to +70C (commercial) | — |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) | — |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II | Altera Logic Programmer (PLAD-J), 4-wire serial |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | Not applicable (legacy) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Security Bit | Yes (design protection) | — |
| Tape and Reel | Yes (suffix T) | — |
| Manufacturer | — | Rochester Electronics (Altera original) |
| Device Family | — | Altera Classic EPLD - EP910 |
| Usable Gates | — | 450 |
| Macrocells | — | 24 |
| Logic Array Blocks | — | 2 (12 macrocells each) |
| Propagation Delay (tPD) | — | 40 ns |
| Maximum Toggle Frequency (fMAX) | — | 25 MHz |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 4 |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| Lead-Free Status | — | Not applicable |