EPM5192LI-2 vs EPM5192LI-1 比較
詳細な並列比較: EPM5192LI-2 メーカー: Altera および EPM5192LI-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192LI-2 | EPM5192LI-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.90 | $16.40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable/OTP Complex PLD) | EPLD (UV-Erasable/OTP Complex PLD) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O | 64 | — |
| Total Inputs | 72 (7 dedicated + 64 I/O) | — |
| Propagation Delay (tpd) | 55 ns (max) | — |
| Maximum Internal Frequency | 100 MHz | — |
| 電源電圧 | 4.5 V to 5.5 V | 5 V |
| 動作温度 | -40 C to +85 C (industrial) | [DATA_NEEDED: industrial vs military range] |
| Typical Power Dissipation | 600 mW at 5 V / 25 C | — |
| Technology | CMOS, UV-erasable / OTP | — |
| パッケージ | 84-pin PLCC (J-lead), JEDEC S-PQCC-J84 | — |
| 実装タイプ | Surface Mount | Surface Mount (JLCC with J-leads) |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of ceramic LI variant] |
| Design Toolchain | Altera MAX+plus II | — |
| Usable Gates | — | 3,750 |
| Maximum Toggle Frequency | — | 40 MHz |
| Propagation Delay (tPD) | — | [DATA_NEEDED: tPD in ns at -1 grade] |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for JLCC variant] |
| Package Type | — | JLCC (windowed, ceramic, UV-erasable) |
| Process Technology | — | CMOS EPROM, UV-erasable |
| Speed Grade | — | -1 |
| ピン数 | — | [DATA_NEEDED: pin count of LI package] |
| MSLレベル | — | [DATA_NEEDED: MSL level] |
| Lead Free | — | [DATA_NEEDED: lead-free] |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Architecture | — | EEPROM/EPROM-based, non-volatile, instant-on |