EPM9320LC84-20N vs EPM9320ALI84-10N 比較
詳細な並列比較: EPM9320LC84-20N メーカー: Intel および EPM9320ALI84-10N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9320LC84-20N | EPM9320ALI84-10N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.25 | $21.95 |
| Series | MAX 9000 | — |
| Logic Family | CMOS (EEPROM-based) | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 to 12,000 |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| ピン数 | 84 | — |
| Package Type | Plastic Leaded Chip Carrier (PLCC-84, J-bend) | — |
| Package Code | QCCJ | — |
| Propagation Delay (tPD) | 16 ns | — |
| Internal Frequency | 118 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| 動作温度 | 0 C to +70 C (Commercial) | -40C to +85C (industrial) |
| Programming | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) | — |
| 実装タイプ | Surface Mount (J-bend) | Surface Mount (PLCC socket compatible) |
| Terminal Form | J BEND | — |
| MSLレベル | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | — |
| Family | — | MAX 9000 |
| Architecture | — | MAX (Multiple Array MatriX), 3rd generation |
| Process Technology | — | CMOS EEPROM |
| Logic Array Blocks (LABs) | — | 20 |
| User I/O Pins | — | 56 |
| Pin-to-Pin Delay | — | 10 ns |
| Maximum Counter Frequency | — | 144.9 MHz |
| VCCINT (Core Supply) | — | 5.0 V |
| VCCIO (I/O Supply) | — | 3.3 V or 5.0 V |
| Input Logic Levels | — | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |
| パッケージ | — | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| Configuration Memory | — | EEPROM, non-volatile |