EPM9400LC84-15 - MAX 9000 CPLD 8K Gates 400 Macros | Altera
部品番号: EPM9400LC84-15 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.8 | $2,980.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $23.1 | $23,100.00 |
EPM9400LC84-15 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like logic blocks with a central interconnect matrix, sitting in the broader programmable logic hierarchy: CPLD -> programmable logic -> logic IC -> integrated circuit -> semiconductor. Unlike SRAM-based FPGAs, MAX 9000 devices store their configuration in on-chip EEPROM, providing instant-on behavior without external boot memory and making them well suited for deterministic boot-critical applications.
Key features include 25 logic array blocks, 59 maximum user I/Os, 5.0 V VCCINT core supply with TTL-compatible input thresholds that are also 3.3 V tolerant, and a commercial 0C to 70C operating temperature range. The device is fabricated on a 0.35 um EEPROM process that retains configuration for at least 20 years and supports in-system programmability via the JTAG-compliant IEEE Std. 1149.1 boundary-scan interface. The PLCC-84 package offers a JEDEC-standard through-hole-style leaded footprint that simplifies prototyping and rework.
Architecturally, the MAX 9000 family uses a programmable interconnect array (PIA) that routes signals between LABs (Logic Array Blocks), each containing 16 macro cells with shared product-term expanders and I/O control blocks. The EPM9400LC84-15 supports per-pin slew-rate control, programmable ground pins, and JTAG-based in-system programming through dedicated JTAG pins, eliminating the need for a separate EPROM programmer.
Typical applications include bus-interface bridging, address decoding and glue logic for microprocessor systems, peripheral controllers (UART, FIFO, memory controllers), industrial control sequencing, and legacy 5V system replacement of discrete TTL/CMOS logic. The deterministic timing of the EEPROM-based architecture also makes it suitable for safety-critical or hard-real-time control where SRAM-FPGA configuration latency is unacceptable.
When designing with this device, ensure VCC rises monotonically during power-up and that all four dedicated input pins stay above -0.3 V DC. The 5 V VCCINT rail must remain stable; designers should place decoupling capacitors close to every VCC pin and observe the maximum I/O undershoot/overshoot limits stated in the Operating Requirements for Altera Devices Data Sheet.
This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design notes not assembled on any single manufacturer or distributor datasheet page.
ドロップイン代替品: EPM9400LC84-15 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9400LC84-15 （同一形状・フットプリント） — 相違点: Usable Gates, Mounting Type, Package, Family, Macrocells.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9400LC84-10
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM9320LC84-15
✅ ドロップイン✓ 在庫あり
$17.95 / 個
データシートを見る →EPM9320LC84-10
✅ ドロップイン✓ 在庫あり
$84.96 / 個
データシートを見る →EPM9400LC84-15 最大定格＆電気的特性
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 8,000 |
| Macro Cells | 400 |
| Logic Array Blocks | 25 |
| Maximum User I/Os | 59 |
| Maximum Operating Frequency | 117.6 MHz |
| Speed Grade | -15 (15 ns pin-to-pin delay) |
| Core Supply Voltage (VCCINT) | 5.0 V |
| Input Logic Compatibility | TTL, 3.3 V and 5.0 V tolerant |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | IEEE Std. 1149.1 compliant (ISP) |
| パッケージ | 84-pin PLCC |
| 実装タイプ | Surface Mount |
| 動作温度 | 0C to +70C (Commercial) |
| Minimum VCCINT | 4.75 V |
| Programming Method | In-System Programmable via JTAG |
EPM9400LC84-15 ピン構成
| ピン 1 | I/O — User I/O pin (function defined by user design) |
| ピン 2 | I/O — User I/O pin |
| ピン 3 | I/O — User I/O pin |
| ピン 4 | I/O — User I/O pin |
| ピン 5 | I/O — User I/O pin |
| ピン 6 | VCCINT — 5.0 V core supply |
| ピン 7 | I/O — User I/O pin |
| ピン 8 | I/O — User I/O pin |
| ピン 9 | I/O — User I/O pin |
| ピン 10 | I/O — User I/O pin |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O pin |
| ピン 13 | I/O — User I/O pin |
| ピン 14 | I/O — User I/O pin |
| ピン 15 | I/O — User I/O pin |
| ピン 16 | TDI — JTAG Test Data In (dedicated) |
| ピン 17 | TMS — JTAG Test Mode Select (dedicated) |
| ピン 18 | TCK — JTAG Test Clock (dedicated) |
| ピン 19 | I/O — User I/O pin |
| ピン 20 | I/O — User I/O pin |
| ピン 21 | VCCINT — 5.0 V core supply |
| ピン 22 | I/O — User I/O pin |
| ピン 23 | I/O — User I/O pin |
| ピン 24 | GND — Ground |
| ピン 25 | I/O — User I/O pin |
| ピン 26 | I/O — User I/O pin |
| ピン 27 | I/O — User I/O pin |
| ピン 28 | I/O — User I/O pin |
| ピン 29 | I/O — User I/O pin |
| ピン 30 | GND — Ground |
| ピン 31 | I/O — User I/O pin |
| ピン 32 | I/O — User I/O pin |
| ピン 33 | I/O — User I/O pin |
| ピン 34 | I/O — User I/O pin |
| ピン 35 | I/O — User I/O pin |
| ピン 36 | I/O — User I/O pin |
| ピン 37 | VCCINT — 5.0 V core supply |
| ピン 38 | I/O — User I/O pin |
| ピン 39 | I/O — User I/O pin |
| ピン 40 | I/O — User I/O pin |
| ピン 41 | I/O — User I/O pin |
| ピン 42 | GND — Ground |
| ピン 43 | I/O — User I/O pin |
| ピン 44 | I/O — User I/O pin |
| ピン 45 | I/O — User I/O pin |
| ピン 46 | I/O — User I/O pin |
| ピン 47 | I/O — User I/O pin |
| ピン 48 | I/O — User I/O pin |
| ピン 49 | GND — Ground |
| ピン 50 | I/O — User I/O pin |
| ピン 51 | I/O — User I/O pin |
| ピン 52 | I/O — User I/O pin |
| ピン 53 | I/O — User I/O pin |
| ピン 54 | I/O — User I/O pin |
| ピン 55 | I/O — User I/O pin |
| ピン 56 | VCCINT — 5.0 V core supply |
| ピン 57 | I/O — User I/O pin |
| ピン 58 | I/O — User I/O pin |
| ピン 59 | I/O — User I/O pin |
| ピン 60 | I/O — User I/O pin |
| ピン 61 | I/O — User I/O pin |
| ピン 62 | GND — Ground |
| ピン 63 | I/O — User I/O pin |
| ピン 64 | I/O — User I/O pin |
| ピン 65 | I/O — User I/O pin |
| ピン 66 | I/O — User I/O pin |
| ピン 67 | I/O — User I/O pin |
| ピン 68 | I/O — User I/O pin |
| ピン 69 | I/O — User I/O pin |
| ピン 70 | GND — Ground |
| ピン 71 | I/O — User I/O pin |
| ピン 72 | I/O — User I/O pin |
| ピン 73 | I/O — User I/O pin |
| ピン 74 | I/O — User I/O pin |
| ピン 75 | I/O — User I/O pin |
| ピン 76 | I/O — User I/O pin |
| ピン 77 | TDO — JTAG Test Data Out (dedicated) |
| ピン 78 | I/O — User I/O pin |
| ピン 79 | I/O — User I/O pin |
| ピン 80 | VCCINT — 5.0 V core supply |
| ピン 81 | I/O — User I/O pin |
| ピン 82 | I/O — User I/O pin |
| ピン 83 | I/O — User I/O pin |
| ピン 84 | I/O — User I/O pin |
主な用途
EPM9400LC84-15 の用途: 6 件s: Microprocessor Glue Logic and Bus Bridging, Address Decoding and Chip-Select Generation, Peripheral Controllers (UART, FIFO, Memory), Industrial Sequencing and Machine Control, Legacy 5V TTL Replacement and Board Refresh, JTAG-Based In-System Programming Test Platforms.
Microprocessor Glue Logic and Bus Bridging
The EPM9400LC84-15's 400 macro cells and 15 ns pin-to-pin delay make it well suited for microprocessor glue logic and bus-bridging applications such as address decoding, chip-select generation, and wait-state insertion between legacy 5V MCUs and peripheral ICs. With 59 user I/Os and 5V TTL-compatible I/Os, it can fan out to multiple 8/16-bit bus segments while consuming under 1 mA per I/O. Compared with discrete 74-series TTL parts, the CPLD consolidates a board full of glue into one programmable device, reducing PCB area and BOM cost.
おすすめ
Address Decoding and Chip-Select Generation
With 8,000 usable gates and 25 LABs, the EPM9400LC84-15 can decode wide memory address buses (24-32 bits) and generate chip-selects for banks of memory, peripheral controllers, and bus transceivers in a single device. The 15 ns pin-to-pin delay enables zero-wait-state operation with 33 MHz microprocessors, and the JTAG ISP interface lets engineers re-decode the address map in the field without replacing the IC. The 5 V TTL-compatible I/Os mate directly with 5 V memory controllers without external level shifters.
おすすめ
Peripheral Controllers (UART, FIFO, Memory)
The 117.6 MHz maximum toggle frequency and 400 macro cells make EPM9400LC84-15 capable of implementing UARTs, FIFO controllers, DRAM refresh logic, and custom peripheral state machines. Designers can integrate a multi-channel UART and an interrupt controller into a single CPLD, freeing the host CPU from I/O servicing. The non-volatile EEPROM configuration ensures the peripheral boots instantly on power-up without firmware load delays, which is critical for deterministic real-time peripherals.
おすすめ
Industrial Sequencing and Machine Control
Inside 0C to +70C control cabinets, the EPM9400LC84-15 implements sequencing logic for assembly lines, packaging machinery, and conveyor control with deterministic 15 ns step times. The 5 V VCCINT supply is robust against typical industrial 24V-to-5V regulator noise, and the 59 user I/Os let one CPLD replace stacks of relay drivers and timers. Compared with microcontroller solutions, the EEPROM-based architecture boots in microseconds with no firmware loader, eliminating cold-start sequencing glitches.
おすすめ
Legacy 5V TTL Replacement and Board Refresh
When refreshing legacy boards built around discrete 74LS/74HC TTL, the EPM9400LC84-15 with 5 V TTL-compatible I/Os and 400 macro cells can replace dozens of small-scale logic ICs with a single in-system programmable device. Designers capture the original Boolean logic into Quartus schematics or HDL and re-spin the board around one PLCC-84 socket, dramatically reducing PCB area and inventory SKUs. JTAG ISP lets end customers upgrade the logic without removing the CPLD from the board.
おすすめ
JTAG-Based In-System Programming Test Platforms
The EPM9400LC84-15's JTAG (IEEE Std. 1149.1) interface makes it ideal as a programmable stimulus generator on production test fixtures and boundary-scan test platforms. Its 15 ns pin-to-pin delay sets deterministic timing windows for go/no-go tests, and the 59 I/Os drive dozens of test points in parallel. Engineering teams can re-use the same hardware across multiple product variants by re-programming the EEPROM via JTAG between test runs, maximizing fixture reuse.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9400LC84-15 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9400LC84-10 | EPM9320LC84-15 | EPM9320LC84-10 |
|---|---|---|---|---|
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Brand | Altera | Altera | Altera | Altera |
| Family | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 |
| Macro Cells | 400 | 400 | 320 | 320 |
| Pin-to-Pin Delay | 15 ns | 10 ns (faster) | 15 ns | 10 ns (faster) |
| VCCINT | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
主な差別化要因
- Higher macro-cell density than EPM9320LC84 family （vs EPM9320LC84-15)
- Industry-standard 5 V TTL-compatible I/Os （vs MAX II / MAX V CPLDs)
- EEPROM non-volatile configuration = instant-on （vs SRAM-based FPGAs (e.g., Cyclone, Spartan))
設計ノート
The EPM9400LC84-15 requires a monotonic 5.0 V VCCINT supply with a minimum operating voltage of 4.75 V. Place a 0.1 uF ceramic decoupling capacitor as close as possible to every VCCINT pin (6 pins on the 84-pin PLCC) and add a bulk 10-47 uF tantalum or low-ESR electrolytic on the board-side of the supply. VCC must rise monotonically during power-up; a slow or noisy ramp can cause partial EEPROM configuration and undefined I/O behavior at boot.
The 84-pin PLCC package uses a JEDEC-standard 1.27 mm pitch leaded footprint with a central thermal/exposed cavity. Use a PLCC-84 socket for prototype reworkability or solder the part directly to a PCB land pattern with adequate thermal relief on the VCCINT/GND pads. Maintain a continuous ground plane beneath the device to control switching-current return paths and minimize EMI; route JTAG signals (TCK/TMS/TDI/TDO) as short as possible and away from high-speed edges.
Input pins must not undershoot below -0.5 V DC or below -2.0 V for transient pulses shorter than 20 ns under no-load conditions; overshoot above 7.0 V is likewise prohibited. Do not drive the four dedicated inputs (and user I/Os) below -0.3 V. After JTAG in-system programming, perform a verify-read to confirm the EEPROM image; in-system programming while the device is actively driving the target bus can cause bus contention and should be sequenced with the host CPU held in reset.
Estimated: at maximum toggle rate (117.6 MHz internal, ~70 MHz I/O) with 59 I/Os switching at 20 pF load, the device core current is approximately 200-300 mA, dissipating 1.0-1.5 W. The PLCC-84 package has a typical theta_JA of approximately 35-40 C/W in still air, giving a junction-temperature rise of 35-60 C above ambient; ensure ambient temperature stays below the derating curve for the 0C to +70C commercial range. Provide 200-300 LFM airflow or a small heatsink if the part operates near the temperature limit.
コンプライアンス情報
RoHS, REACH, lead-free, and halogen-free statuses were not present in the verified web data; the part is obsolete and pre-dates many modern compliance disclosures. AEC-Q100 is not applicable as the part is specified for commercial 0C to +70C operation, not automotive grade.
