10AX115H2F34I2SG - Arria 10 GX 1.15M Logic Elements FPGA | Altera | Intel
部品番号: 10AX115H2F34I2SG ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $4850 | $4,850.00 |
| 10 | $4530 | $45,300.00 |
| 50 | $4220 | $211,000.00 |
| 100 | $3990 | $399,000.00 |
| 500 | $3640 | $1,820,000.00 |
10AX115H2F34I2SG 概要
A Field-Programmable Gate Array (FPGA) is a programmable logic device whose architecture comprises an array of configurable logic blocks (CLBs), programmable interconnect, dedicated DSP blocks, Block RAM (BRAM), clock management tiles (PLLs), and - on transceiver variants - multi-gigibit transceivers (MGTs) and high-speed serial interface hard IP. Within the broader taxonomy, FPGAs sit inside the Programmable Logic category of Integrated Circuits, alongside CPLDs and SPLDs; the Arria 10 family is positioned between Intel Cyclone (low-power/cost) and Intel Stratix (high-performance) lines. The Arria 10 GX variant specifically adds transceiver channels for protocols such as PCIe Gen3, 10GbE, CPRI, and Serial RapidIO.
Key differentiating specifications for the Arria 10 GX 115 include 1,150,000 logic elements, 68.86 Mbit embedded memory, integrated 14.1 Gbps transceivers, a hardened IEEE 754-compliant single-precision floating-point DSP block (up to ~1.5 TFLOPs), and SmartVID dynamic voltage scaling between 0.85 V and 0.9 V. The H2 speed grade balances timing margin against power; the I2 temperature grade supports industrial ambient operation (-40C to +100C Tj) suitable for base-station, broadcast, and ruggedized embedded deployments. The F34 package is the 1152-ball FCBGA used for the 115 density tier.
Architecturally, the device combines an ARM Cortex-A9 MPCore hard processor system option (in SoC variants) with a tightly coupled coherent interconnect, dual PCIe Gen3 hard IP blocks with on-die termination, and 24 transceiver channels. The 20 nm Tri-Gate process delivers 60% lower power than the prior 28 nm Arria V generation at equivalent performance, with SmartVID allowing each die to operate at its lowest viable Vcc while maintaining performance guarantees.
Typical applications for the Arria 10 GX 115 include 4K/UHD video processing and broadcast contribution encoders, wireless baseband (LTE-A/5G NR small-cell digital front-end), military and avionics signal processing, test and measurement instrumentation, high-performance computing accelerators, and PCIe Gen3 add-in cards. The combination of integrated transceivers and hardened floating-point DSP removes the need for an external PHY or software-emulated floating point, simplifying board layout and lowering bill-of-materials cost.
When designing with this device, ensure that PCB substrate meets the loss budget for 14.1 Gbps serial channels (typically >6 GHz Nyquist), power delivery nets support the SmartVID dynamic range, and the JTAG/Active Serial configuration path is accessible for in-system reprogramming. Quartus Prime is the required development toolchain. Designers should also budget thermal headroom for SmartVID peak current transients during dynamic reconfiguration.
This page synthesizes Arria 10 family datasheet parameters, drop-in 1152-ball FCBGA alternatives, industrial-grade operating conditions, and practical Quartus Prime design notes not consolidated in the manufacturer datasheet.
ドロップイン代替品: 10AX115H2F34I2SG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10AX115H2F34I2SG （同一形状・フットプリント） — 相違点: Package, DSP Blocks, Transceivers, Embedded Memory, Operating Temperature.
クイック比較ツール — 並列比較する代替部品を選択:
10AX115H2F34I2LG
✅ ドロップイン✓ 在庫あり
$4995 / 個
データシートを見る →10AX115H2F34I1SG
✅ ドロップイン✓ 在庫あり
$3700 / 個
データシートを見る →10AX115H2F34E2SG
✅ ドロップイン✓ 在庫あり
$5500 / 個
データシートを見る →10AX115H2F34E2LG
✅ ドロップイン✓ 在庫あり
$5950 / 個
データシートを見る →10AX115H2F34E1SG
✅ ドロップイン✓ 在庫あり
$3300 / 個
データシートを見る →10AX115H1F34I1SG
✅ ドロップイン✓ 在庫あり
$6500 / 個
データシートを見る →10AX115H1F34E1SG
✅ ドロップイン✓ 在庫あり
$2895 / 個
データシートを見る →10AX115H2F34I2SG 最大定格＆電気的特性
| Family | Arria 10 GX |
| Logic Elements | 1,150,000 |
| Adaptive Logic Modules (ALMs) | 427,200 |
| Embedded Memory | 68.86 Mbit |
| DSP Blocks | 1,518 (variable precision, hardened FP32) |
| Transceiver Channels | 24 (max up to 14.1 Gbps) |
| PCIe Hard IP | 2x PCIe Gen3 |
| Process Technology | 20 nm Tri-Gate |
| Core Voltage (SmartVID) | 0.85 V to 0.9 V |
| Speed Grade | H2 |
| Temperature Grade | Industrial (I2, -40C to +100C Tj) |
| パッケージ | 1152-ball FC-FBGA (F34) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
10AX115H2F34I2SG ピン構成
| ピン B1 | REFCLK_p — Transceiver reference clock, bank L0 |
| ピン B2 | REFCLK_n — Transceiver reference clock complement, bank L0 |
| ピン AF14 | VCC — Core power supply (SmartVID 0.85-0.9 V) |
| ピン GND | VSS — Ground ball (multiple positions) |
主な用途
10AX115H2F34I2SG の用途: 6 件s: 4K/UHD Broadcast Video Processing, 5G NR Small-Cell Baseband Processing, Military & Aerospace Signal Processing, Test & Measurement Instrumentation, High-Performance Computing Accelerator Card, ASIC Prototyping & Emulation.
4K/UHD Broadcast Video Processing
The 10AX115H2F34I2SG is well-matched to 4K/UHD broadcast contribution encoders and IPTV media gateways. With 1,150,000 logic elements, 68.86 Mbit embedded memory, and 1,518 hardened floating-point DSP blocks (up to ~1.5 TFLOPs FP32), the FPGA can run real-time HEVC/H.265 4:2:2 10-bit encoding for multiple 4K streams without external ASIC co-processors. The integrated 14.1 Gbps transceivers support 12G-SDI, SMPTE 2022, and 10GbE network aggregation with deterministic latency. Placed as the central processing device alongside a TI LMK03328 clock conditioner and Micron DDR4 external memory, the 115 LE budget allows line-rate processing at UHD p60.
おすすめ
5G NR Small-Cell Baseband Processing
The 10AX115H2F34I2SG is suitable for 5G NR small-cell and LTE-A baseband digital front-end designs. The 1.15M LE density supports full PHY-layer processing for 4T4R 100 MHz 5G NR small cells with LDPC/Polar encoding at sub-1 ms latency. The 24 transceiver channels at up to 14.1 Gbps handle CPRI 9.8 Gbps or eCPRI fronthaul, plus JEDEC JESD204B/C links to RF ADCs/DACs. The I2 industrial temperature grade supports outdoor sealed-enclosure deployments (-40C to +100C Tj). Pairing with a TI AFE7950 RF transceiver and Intel eASIC SoC host, the Arria 10 delivers PHY-layer density previously requiring ASICs.
おすすめ
Military & Aerospace Signal Processing
The 10AX115H2F34I2SG is widely deployed in ruggedized MIL-spec signal-processing systems, including electronic-warfare receivers, radar preprocessing, and avionics video/graphics pipelines. The 20 nm Tri-Gate Arria 10 architecture provides radiation-tolerant latch-up immunity and SmartVID dynamic power scaling for thermal envelopes in conduction-cooled ATR enclosures. Industrial-grade I2 temperature and a 1152-ball FCBGA with controlled CTE substrate support MIL-STD-810 thermal cycling. Combined with the hardened IEEE 754 single-precision floating-point DSP, the device accelerates FFT, FIR, and matrix arithmetic without sacrificing precision in EW and SAR processing workloads.
おすすめ
Test & Measurement Instrumentation
The 10AX115H2F34I2SG suits high-end test and measurement instruments, including arbitrary waveform generators, real-time oscilloscopes, and protocol analyzers. Its 1,518 hardened FP32 DSP blocks enable multi-GS/s arbitrary waveform synthesis with on-the-fly waveform mathematics, while the integrated 14.1 Gbps transceivers capture or drive PCIe Gen3, USB 3.1, SATA, and 10GbE data streams. The 68.86 Mbit embedded memory provides deep real-time sample buffers. Used alongside a TI ADC12DJ5200 RF ADC and an external DDR4 capture buffer, the FPGA delivers sample rates beyond 5 GS/s with deterministic trigger latency.
おすすめ
High-Performance Computing Accelerator Card
The 10AX115H2F34I2SG is an effective PCIe Gen3 add-in-card accelerator for HPC workloads such as genomics, computational finance, and machine-learning inference. Two hardened PCIe Gen3 IP blocks support x8 endpoint configuration with bus-master DMA to host memory at >6 GB/s. The 1,518 hardened FP32 DSPs deliver >1 TFLOPs of single-precision throughput for HFT, FFT, and OpenCL kernels. With 1.15M LEs the FPGA supports substantial on-chip data-flow graphs without external co-processors. The industrial temperature grade fits rack-mounted server inlet air up to ~65C with appropriate airflow design.
おすすめ
ASIC Prototyping & Emulation
The 10AX115H2F34I2SG is widely used as an ASIC prototyping platform, with multiple FPGAs commonly partitioned via dedicated multi-FPGA interconnect bridges. The 1.15M LE density provides enough logic capacity to map medium-complexity ASIC blocks (typically ~5-10M ASIC gates) into a single device for fast bring-up and software-development hardware. The industrial temperature grade supports prototype bring-up in thermally modest lab enclosures. Used alongside an Arria 10 SoC for control-plane services and external DDR4 emulation memory, it accelerates RTL validation and pre-silicon firmware development.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10AX115H2F34I2SG — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10AX115H2F34I2LG | 10AX115H2F34I1SG | 10AX115H2F34E2SG | 10AX115H2F34E2LG |
|---|---|---|---|---|---|
| Package | 1152-ball FC-FBGA (F34) | 1152-ball FC-FBGA (F34) - same | 1152-ball FC-FBGA (F34) - same | 1152-ball FC-FBGA (F34) - same | 1152-ball FC-FBGA (F34) - same |
| Brand | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Embedded Memory | 68.86 Mbit | 68.86 Mbit | 68.86 Mbit | 68.86 Mbit | 68.86 Mbit |
| Speed Grade | H2 | H2 | H2 | H2 | H2 |
| Temperature Grade | Industrial I2 (-40C to +100C Tj) | Industrial I2 (-40C to +100C Tj) | Extended-industrial I1 (-40C to +125C Tj) | Extended E2 (0C to +100C Tj) | Extended E2 (0C to +100C Tj) |
| Transceiver Rate | 14.1 Gbps | 14.1 Gbps | 14.1 Gbps | 14.1 Gbps | 14.1 Gbps |
| RoHS / Lead-Free | Compliant / Yes | Compliant / Yes (LG suffix = Pb-free) | Compliant / Yes | Compliant / Yes | Compliant / Yes (LG suffix = Pb-free) |
| Process / Core Voltage | 20 nm / 0.85-0.9 V SmartVID | 20 nm / 0.85-0.9 V SmartVID | 20 nm / 0.85-0.9 V SmartVID | 20 nm / 0.85-0.9 V SmartVID | 20 nm / 0.85-0.9 V SmartVID |
主な差別化要因
- Largest Arria 10 GX density (1.15M LE) in the F34 FCBGA （vs 10AX066H2F34I2SG)
- Integrated 14.1 Gbps transceivers with hardened PCIe Gen3 （vs 10AX115N3F40E2SG (non-GX variant))
- Hardened IEEE 754 single-precision floating-point DSP （vs Cyclone 10 GX FPGAs)
設計ノート
At typical Arria 10 GX 115 utilization (60-70% logic, full transceiver rate), worst-case power dissipation can reach 20-25 W. The 1152-ball FC-FBGA F34 package requires a high-performance thermal solution - 4-6 layer PCB with at least 1 oz copper and a heatsink with airflow of 1-2 m/s. Compute T_j_max using the SmartVID-specific thermal resistance from the Arria 10 GX Thermal Modeling User Guide. Always measure T_j in a populated system using the on-die temperature sensor via JTAG before final qualification.
PCB substrate for the 1152-ball FCBGA must be designed for >6 GHz Nyquist to support 14.1 Gbps transceiver operation. Use a low-loss dielectric (Megtron 6, Rogers RO4350B, or similar with Dk <3.5, Df <0.005 at 5 GHz). Stack-up must maintain 50 ohm single-ended and 90 ohm differential impedances for the transceiver channels with <0.5 dB/inch loss at 7 GHz. Reference the Arria 10 GX Transceiver Layout Guidelines for via pattern, length matching, and AC-coupling capacitor placement.
SmartVID requires a programmable PMIC such as the Intel Enpirion EM11x0 or equivalent with 10-20 mV VID step resolution. The VID bus (4 wires: VID0-VID3) connects from the configuration image source (typically an external SPI flash) to the PMIC. Bulk decoupling requires 22 uF + 0.1 uF ceramic + 470 uF polymer tantalum per VCC and VCCP rails. Verify transient response of the PMIC for >10 A/us load steps during dynamic reconfiguration - undershoot below 0.83 V can cause SmartVID undervoltage lockout.
Common pitfalls include (1) failing to disable unused transceivers via Quartus Prime configuration to save 1-2 W per channel, (2) using LVCMOS 1.8 V I/O standards without configuring the HPS_IO or general-purpose I/O bank voltage reference, which can damage I/O banks, (3) ignoring PCIe Gen3 link-training requirements - both 100 MHz and 125 MHz reference clocks must be clean and routed with 90 ohm differential impedance, and (4) forgetting to instantiate the JTAG IDCODE in the design, which prevents subsequent configuration via JTAG.
コンプライアンス情報
RoHS and REACH compliant per Altera/Intel FPGA product environmental compliance documentation. AEC-Q100 not applicable (FPGA is not an automotive-qualified discrete). Lead-free across all variants. Conflict-minerals declaration per Intel supplier-responsibility policy.
