10AX115H3F34E2LG - Arria 10 GX FPGA, 1.15M LE, 1152-FCBGA | Intel
部品番号: 10AX115H3F34E2LG ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $7371.55 | $7,371.55 |
| 10 | $7100 | $71,000.00 |
| 25 | $6900 | $172,500.00 |
| 50 | $6750 | $337,500.00 |
| 100 | $6550 | $655,000.00 |
10AX115H3F34E2LG 概要
An FPGA (Field-Programmable Gate Array) is a semiconductor device whose digital logic, interconnect, and I/O behaviour can be reconfigured after manufacture by loading a user-defined bitstream. FPGAs occupy the middle ground between fixed-function ASICs and software-driven processors: they offer hardware-timed parallelism and protocol acceleration, and they belong to the broader family of programmable logic devices (PLDs). The Arria 10 family sits in Intel's mid-range line, below Stratix 10 but above Cyclone 10, balancing transceiver performance, logic density, and power efficiency for communications, broadcast, and compute-acceleration workloads.
Key features of the 10AX115H3F34E2LG include up to 1,150,000 logic elements (LEs), 67.7 Mbits of embedded SRAM, integrated transceivers supporting data rates up to 17.4 Gbps (per the Arria 10 device datasheet), hard PCI Express Gen3 x8 controllers, hard memory controllers for DDR4/DDR3/QDR-IV, and 504 user I/Os distributed across 12 I/O banks. The 'E2' speed grade targets commercial-grade timing closure, while the F34 package designation defines a 1152-ball flip-chip BGA with 1.0 mm ball pitch, optimised for high-speed serial channel escape.
The architecture combines a core fabric of adaptive logic modules (ALMs), embedded DSP blocks, embedded M20K memory blocks, and a variable-precision DSP engine. Per the Intel Arria 10 device datasheet, hard IP blocks implement PCIe Gen3, 10/25/100G Ethernet MACs, and high-speed serial interfaces, offloading these functions from soft logic and improving timing closure. The 20nm process enables higher logic density at lower core power compared with the prior 28nm Arria V generation.
Typical applications include 4K/8K video broadcast and contribution encoders, radar and electronic-warfare signal processing in defense systems, 100G line-card data-path processing, 4G/5G baseband preprocessing, medical imaging accelerators (CT, MRI, ultrasound beamforming), and high-performance computing test and measurement platforms. The integrated 17.4 Gbps transceivers are commonly paired with CFP2/CFP4 optical modules or direct-attached copper cable assemblies.
When designing with the 10AX115H3F34E2LG, allocate sufficient PCB layers (minimum 12, recommended 16+) for transceiver channel breakout, simulate channel loss with the Intel Quartus Prime Signal Integrity Toolkit, and respect the F34 ballmap recommended decoupling strategy. The 'E2' speed grade trades maximum Fmax for lower static power and is acceptable for most commercial deployment profiles.
This page synthesises distributor pricing, parametric data, and cross-references to same-package Arria 10 family variants that are not consolidated on a single manufacturer datasheet table, providing drop-in alternatives and design notes useful during sourcing decisions.
ドロップイン代替品: 10AX115H3F34E2LG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10AX115H3F34E2LG （同一形状・フットプリント） — 相違点: Package, DSP Blocks, Embedded Memory, Speed Grade, Transceivers.
クイック比較ツール — 並列比較する代替部品を選択:
10AX115H2F34E2SG
✅ ドロップイン✓ 在庫あり
$5500 / 個
データシートを見る →10AX115H2F34I2SG
✅ ドロップイン✓ 在庫あり
$3640 / 個
データシートを見る →10AX115H2F34I2LG
✅ ドロップイン✓ 在庫あり
$4995 / 個
データシートを見る →10AX115H2F34E2LG
✅ ドロップイン✓ 在庫あり
$5950 / 個
データシートを見る →10AX115H1F34I1SG
✅ ドロップイン✓ 在庫あり
$6500 / 個
データシートを見る →10AX115H3F34E2LG 最大定格＆電気的特性
| Family | Arria 10 GX |
| Series | 10AX115 |
| Logic Elements (LE) | 1,150,000 |
| Embedded Memory | 68,857,856 bits (67.7 Mbit) |
| User I/O Count | 504 |
| Transceivers | Up to 17.4 Gbps (per Arria 10 datasheet) |
| Hard IP | PCIe Gen3 x8, 10/25/100G Ethernet MAC, DDR4 controller |
| DSP Blocks | Variable-precision DSP (per Arria 10 datasheet) |
| Process Technology | 20 nm TSMC |
| Core Voltage | 0.9 V |
| Speed Grade | E2 (commercial, mid-speed) |
| パッケージ | 1152-ball FCBGA (F34), 1.0 mm pitch |
| 動作温度 | 0C to +100C (commercial) |
| 実装タイプ | Surface Mount (BGA, reflow) |
| RoHS ステータス | Compliant |
| MSLレベル | MSL3 (per JEDEC J-STD-020) |
10AX115H3F34E2LG 1152-ball fcbga (f34), 1.0 mm pitch ピン配置ガイド
10AX115H3F34E2LG (1152-ball fcbga (f34), 1.0 mm pitch パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: 10AX115H3F34E2LG.
詳細は データシート をご参照ください。
主な用途
10AX115H3F34E2LG の用途: 6 件s: 100G Ethernet Line-Card Processing, 4K/8K Video Broadcast Contribution Encoder, 4G/5G Baseband Preprocessing & Fronthaul, Medical Imaging Accelerator (CT / MRI / Ultrasound), Radar / Electronic Warfare Signal Processing, Test & Measurement Instrumentation.
100G Ethernet Line-Card Processing
The 10AX115H3F34E2LG is purpose-built for 100G line-card data-path processing on edge routers and OTN switches. Its hard 100G Ethernet MAC and four integrated 17.4 Gbps transceivers directly drive CFP2/CFP4 optical modules without consuming soft-logic resources, leaving the 1.15M-LE fabric available for packet classification, QoS scheduling, and traffic management. Designers typically instantiate two MAC+PCS instances to support redundant fabric uplinks, achieving deterministic latency below 1 microsecond. The hard PCIe Gen3 x8 IP simplifies direct-attachment to a co-located host CPU or network processor, eliminating an external bridge. With DDR4 hard memory controllers, line-rate deep packet buffers (multi-MB) are implemented without FPGA fabric RAM, freeing DSP and ALM resources for pipeline logic.
おすすめ
4K/8K Video Broadcast Contribution Encoder
The 10AX115H3F34E2LG's 1.15M logic elements and abundant DSP blocks drive real-time HEVC/H.265 4K60p or 8K encoding and multi-channel contribution codec workloads. Per the Arria 10 datasheet, the device delivers >3 TFLOPS of DSP throughput, sufficient for parallel motion-estimation engines and CABAC entropy coding pipelines. The 12 high-performance I/O banks accommodate quad-channel SDI (3G/6G/12G-SDI) interfaces, and the 17.4 Gbps transceivers feed SMPTE 2022/2110 IP-based studio transport. Designers benefit from hard PCIe Gen3 to host blade servers for ancillary data and low-latency preview streams. The E2 speed grade is acceptable for video-frame timing budgets of ~16.7 ms at 60 Hz.
おすすめ
4G/5G Baseband Preprocessing & Fronthaul
The 10AX115H3F34E2LG is widely used as a CPRI/eCPRI fronthaul hub between baseband units and remote radio heads. Its transceivers support CPRI line rates up to option 9 (12.165 Gbps), and the hard 100G Ethernet MAC aggregates multiple CPRI streams onto a single 100G uplink. Designers implement channel estimation, FFT/iFFT pre-processing, and digital predistortion (DPD) in the FPGA's variable-precision DSP blocks, reducing ASIC-equivalent latency by 30-50%. The 504 user I/Os interface to ADC/DAC front ends (e.g., JESD204B/C), and hard DDR4 controllers buffer I/Q samples. With ~7,072 pieces distributor-stocked as of 2026-09-05, lead times for new base-station deployments are manageable.
おすすめ
Medical Imaging Accelerator (CT / MRI / Ultrasound)
In CT and MRI reconstruction pipelines, the 10AX115H3F34E2LG's 1.15M logic elements and >3 TFLOPS DSP throughput execute iterative reconstruction algorithms (e.g., FBP, ART, model-based) at sub-second frame rates. The 504 user I/Os interface to multi-channel high-speed ADCs over JESD204B/C links, and the 17.4 Gbps transceivers backhaul reconstructed image data to host workstations via 10/25/40G Ethernet. Hard PCIe Gen3 enables low-latency DMA into the host CPU for post-processing. Designers pair this device with an external DDR4 SODIMM bank (16-32 GB) controlled by the FPGA's hard memory controllers for sinogram buffering, achieving 2-4x speedup over CPU-only reconstruction at lower system cost than GPU alternatives.
おすすめ
Radar / Electronic Warfare Signal Processing
Defense and aerospace integrators deploy the 10AX115H3F34E2LG in phased-array radar and electronic-warfare subsystems requiring real-time FFT, beamforming, and pulse compression. Its 17.4 Gbps transceivers accept multi-channel ADC outputs (e.g., 16x 250 MSPS ADCs via JESD204B) and the variable-precision DSP blocks implement multi-tap FIR filters and 4096-point FFTs per microsecond. The hard 100G Ethernet MAC backhauls processed tracks/detections to mission processors. While the E2 commercial-grade variant suits bench/integration testing, the I2 industrial variant is preferred for flight-line hardware. Note that extended-temperature and MIL-STD-810 screening require the -1.0V core screening variant; consult Intel Aerospace/DO-254 documentation.
おすすめ
Test & Measurement Instrumentation
The 10AX115H3F34E2LG underpins high-end oscilloscopes, BERTs, and protocol analysers requiring deep trace memory and deterministic sample-rate conversion. Its 504 user I/Os drive parallel LVDS front-end digitisation channels, and the 67.7 Mbit embedded SRAM provides sub-microsecond trigger-event storage before DMA to external DDR4 buffers. Hard PCIe Gen3 streams captured waveforms to host software at line rate, while the 17.4 Gbps transceivers support 100G Ethernet test heads for network-equipment validation. Designers can rapidly customise trigger logic, protocol decoders, and measurement routines via Quartus Prime, achieving time-to-market advantages over fixed-function ASIC alternatives. Commercial E2 speed grade suffices for ambient laboratory conditions.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10AX115H3F34E2LG — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10AX115H2F34E2SG | 10AX115H2F34I2SG | 10AX115H2F34I2LG | 10AX115H2F34E2LG | 10AX115H1F34I1SG |
|---|---|---|---|---|---|---|
| Package | 1152-FCBGA (F34), 1.0 mm pitch | 1152-FCBGA (F34), 1.0 mm pitch | 1152-FCBGA (F34), 1.0 mm pitch | 1152-FCBGA (F34), 1.0 mm pitch | 1152-FCBGA (F34), 1.0 mm pitch | 1152-FCBGA (F34), 1.0 mm pitch |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Speed Grade | E2 (commercial) | E2 | I2 | I2 | E2 | I1 |
| Operating Temperature | 0C to +100C (commercial) | 0C to +100C | -40C to +100C | -40C to +100C | 0C to +100C | -40C to +100C |
| Embedded Memory | 67.7 Mbit | 67.7 Mbit | 67.7 Mbit | 67.7 Mbit | 67.7 Mbit | 67.7 Mbit |
| Transceiver Speed (max) | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps |
| Ball Finish Suffix | LG | SG | SG | LG | LG | SG |
主な差別化要因
- F34 footprint drop-in across the entire Arria 10 1.15M-LE family （vs 10AX115R2F40I2SG)
- Pin-compatible industrial-temp upgrade path （vs 10AX115H2F34I2SG)
- Hard PCIe Gen3 + 100G Ethernet IP reduces soft-logic consumption （vs Cyclone 10 GX 10CX150YF672E5G)
設計ノート
The 1152-ball FCBGA (F34) dissipates up to ~25 W under full transceiver utilisation. Apply a thermal management strategy with a heatsink and 200-300 LFM airflow, or integrate a heat-spreader lid per the Arria 10 device datasheet thermal guidelines. Junction temperature must stay below 100C for the E2 commercial-grade variant - derate the design at 12 W core power if enclosed in a chassis with no airflow.
Use a minimum 12-layer PCB stack-up (16+ recommended) with dedicated ground and 0.9V core power planes. Per Intel's Arria 10 PCB design guidelines, route transceiver channels on the top/bottom layers over a continuous reference ground plane, and keep AC-coupling capacitors within 100 mil of the BGA breakout. Implement the recommended decoupling network with 0402/0201 capacitors placed as close as possible to the package balls, as the in-package capacitance of the F34 is insufficient alone.
For 17.4 Gbps transceiver channels, perform 3D EM simulation of the breakout region with the Quartus Prime Signal Integrity Toolkit or ANSYS HFSS. Pre-emphasis and equaliser tap settings must be validated across process-voltage-temperature corners using the Intel Transceiver Toolkit with BERT pattern generation. Reserve at least 8 dB of link margin for production tolerance over the PCB lifetime.
Avoid mixing E2 and I2 speed grades on the same PCB if timing closure is performed against a single SDC file - the Fmax margin differs by 10-15% between grades. Also, do not assume SG and LG ball-finish variants are identical for reflow profile purposes: verify the moisture sensitivity level (MSL) label on the reel/tray before bake-out per JEDEC J-STD-033, especially if a 12-month storage interval has elapsed.
コンプライアンス情報
RoHS and REACH compliant per Intel product page; lead-free (LG/SG) ball finish only. Not AEC-Q100 qualified (this is a commercial/industrial FPGA, not automotive). Conflict-minerals reporting per Intel's CMRT filings.
