10AX115H2F34I1SG - Arria 10 GX FPGA, 1.15M LE, 1152-FBGA | Intel / Altera
MPN: 10AX115H2F34I1SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4850 | $4,850.00 |
| 10 | $4550 | $45,500.00 |
| 100 | $4200 | $420,000.00 |
| 250 | $3950 | $987,500.00 |
| 500 | $3700 | $1,850,000.00 |
Drop-in alternatives for 10AX115H2F34I1SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX115H1F34I1SG
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View Datasheet →10AX115H2F34E2SG
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View Datasheet →10AX115H2F34E1SG
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$3300 / Unit
View Datasheet →10AX115H2F34E2LG
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View Datasheet →10AX115H2F34I1SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 1,150,000 |
| Embedded Memory Bits | 68,857,856 bits |
| Process Technology | TSMC 20 nm |
| User I/O Count | 504 |
| Package | 1152-ball FCBGA (F34) |
| Package Body Size | 35 mm x 35 mm |
| Mounting Type | Surface Mount |
| Operating Temperature Grade | Industrial (-40 C to +100 C) |
| Core Voltage (SmartVID) | 0.85 V to 0.95 V |
| Max Transceiver Data Rate | 17.4 Gbps |
| Speed Grade | 1 |
| External Memory Interface | DDR4, DDR3, QDR II+, RLDRAM III up to 933 MHz |
| RoHS Status | Compliant (SG suffix) |
| Lead-Free | Yes |
10AX115H2F34I1SG 35 mm x 35 mm Pin Configuration Guide
Complete pinout information for 10AX115H2F34I1SG (35 mm x 35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115H2F34I1SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115H2F34I1SG is suitable for 6 applications: 100G Optical Transport Line Card, ASIC Prototyping Platform, 25G/50G Ethernet NIC, High-Frequency-Trading Accelerator, Military Radar Baseband Processor, 4K/8K Video Broadcast Encoder.
100G Optical Transport Line Card
The 10AX115H2F34I1SG is well-suited to 100G optical transport line cards because its Arria 10 GX fabric exposes transceivers up to 17.4 Gbps per channel and integrates 4x10G, 2x25G, or 4x25G PHY groupings that map natively to OTU4 and CAUI-4. With 1.15 M logic elements and 68.8 Mbit of embedded block memory, the part can host a MAC, framermapper (GFP/OTN), and a soft FEC layer on a single device, removing the need for a companion mux/demux ASIC. SmartVID trims core power when the link is in ODU overhead processing. The F34 FCBGA keeps the PCB footprint compact enough for a CFP2/CFP4 line-card front panel.
Recommended
ASIC Prototyping Platform
ASIC prototyping platforms use the 10AX115H2F34I1SG because its 1.15 M logic-element budget accommodates ASICS of roughly 25-30 M gates when partitioned across multiple FPGA instances, and the 68.8 Mbit of embedded memory plus external DDR4 interface provides abundant state capacity. The 17.4 Gbps transceivers support high-speed TDM-style time-multiplexed ASIC-to-FPGA I/O for chip-to-chip bridging. Partial reconfiguration lets designers swap hardware blocks in seconds without rebooting the prototype. Engineers should use Intel's Quartus Prime Pro for synthesis and consult application note AN 698 for configuration planning.
Recommended
25G/50G Ethernet NIC
Low-latency 25G and 50G Ethernet network interface cards are a primary target for the 10AX115H2F34I1SG. The integrated 10-Gbps Ethernet MAC hard IP combined with 17.4 Gbps transceivers supports 25G Ethernet (IEEE 802.3by) and 50G Ethernet (802.3cd) PHY directly, with PCIe Gen3 x8 hard IP for host connectivity. The 504 user I/Os provide ample budget for front-panel ports, DDR4 packet buffer memory, and additional side-band interfaces. Designers must pay close attention to PCB layer stack-up and transceiver analog supply filtering per Intel application note AN 711 (transceiver board design).
Recommended
High-Frequency-Trading Accelerator
High-frequency trading (HFT) accelerators use the 10AX115H2F34I1SG to drive deterministic sub-microsecond packet-to-trade latency in market-data feed handlers and order-routing engines. The 17.4 Gbps transceivers support SFP+ and QSFP+ market-data taps; the 1.15 M LE fabric provides the throughput to keep the matching engine's state in on-chip memory, eliminating off-chip latency jitter. Industrial temperature grade allows deployment in cooling-efficient density-optimized server racks. SmartVID keeps core power down so that more FPGA compute fits in the same thermal envelope, which matters when packing multiple accelerators per PCIe slot.
Recommended
Military Radar Baseband Processor
Defense radar baseband-processing cards use the 10AX115H2F34I1SG because the industrial temperature grade (-40 C to +100 C) suits land-based and shipboard installations, while the 17.4 Gbps transceivers aggregate ADC outputs from RF front-ends at full aperture bandwidth. The 1.15 M LE fabric hosts the FFT, beamforming, pulse compression, and MTI stages in parallel, exploiting the Arria 10 GX hardened floating-point DSP blocks for IEEE-754 single/double-precision math. The F34 FCBGA package enables dense board stacking required in compact phased-array chassis. Designers should harden the FPGA configuration (e.g., remote update) for field deployment.
Recommended
4K/8K Video Broadcast Encoder
4K and 8K video broadcast encoders and contribution links leverage the 10AX115H2F34I1SG because the 1.15 M logic elements can host multiple JPEG XS or H.265 intra-frame encoders in parallel, while the 68.8 Mbit of embedded memory holds multiple line buffers without external SRAM. The 17.4 Gbps transceivers accept uncompressed SDI (SMPTE 2022-6) or SMPTE 2110 IP essence from multiple cameras, while the 504 user I/Os provide ample channels for HDMI/DisplayPort monitor outputs and control panel GPIOs. Industrial temperature grade supports the relatively warm broadcast-rack environment.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115H2F34I1SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115H1F34I1SG | 10AX115H2F34E2SG | 10AX115H2F34E1SG | 10AX115H2F34E2LG |
|---|---|---|---|---|---|
| Package | 1152-ball FCBGA (F34) | 1152-ball FCBGA (F34) | 1152-ball FCBGA (F34) | 1152-ball FCBGA (F34) | 1152-ball FCBGA (F34) |
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Embedded Memory | 68,857,856 bits | 68,857,856 bits | 68,857,856 bits | 68,857,856 bits | 68,857,856 bits |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Extended / Automotive | Extended / Automotive | Extended / Automotive |
| Speed Grade | -2 | -1 | -2 | -1 | -2 |
| Transceiver Configuration Tier | H2 (higher channel count) | H1 (lower channel count) | H2 (higher channel count) | H2 (higher channel count) | H2 (higher channel count) |
| Max Transceiver Rate | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps |
Key Differentiators
- Same F34 footprint, lower-channel variant (vs 10AX115H1F34I1SG)
- Same F34 footprint, extended temperature grade (vs 10AX115H2F34E2SG)
- Same F34 footprint, speed grade -1 option (vs 10AX115H2F34E1SG)
Design Notes
Estimated power budgeting: at SmartVID 0.9 V nominal core, plan for ~25-40 W of core power at full utilization with transceivers active; at static 0.95 V SmartVID max, plan for 50-60 W. Decouple the 0.85-0.95 V VCC core rail with 22 uF + 2.2 uF + 0.1 uF ceramic capacitors per the Intel Arria 10 power distribution application note AN 736, and route the SmartVID sense lines (VCC_SENSE / GND_SENSE) directly to the regulator feedback pins for accurate telemetry.
Transceiver analog rails (VCCH, VCCR, VCCL) require isolated filtering from the digital core; place a ferrite bead or filter cap network within 5 mm of each transceiver bank pin and isolate the analog plane with a moat, per Intel application note AN 711. Differential pair lengths must be matched to within 150 um (TX) and 250 um (RX) at 17.4 Gbps to avoid deterministic jitter degradation, and the AC-coupling capacitor footprint should support 0402 size with a stub length under 200 um.
The 35 mm x 35 mm F34 FCBGA has a typical theta_JA of 4-6 C/W with a 25-30 C/W heatsink plus 200 LFM airflow. At 50 W total power, junction temperature rise is ~5 C above ambient with proper heatsink and airflow - within the industrial 100 C ambient limit. Without a heatsink, the same 50 W would push the junction to ~250 C above ambient, exceeding the limit; never operate at full utilization without thermal management.
Do not assume all 1152 balls are user I/O - only 504 are user I/O, the rest are supply, ground, configuration, and JTAG. Attempting to use transceiver balls as general-purpose I/O will fail. Also confirm the MSL (Moisture Sensitivity Level) from the device label or datasheet before reflow; the FCBGA is typically MSL3 or MSL4, requiring bake-out and controlled-floor life.
Compliance Information
RoHS and REACH compliance indicated by the SG suffix in the ordering code. AEC-Q100 automotive qualification is not_applicable for this FPGA (not an automotive-qualified part per the ordering code 'I' = industrial temperature grade).
