ADC1610S080HN/C1 - 16-bit 80Msps Pipelined ADC | NXP
部品番号: ADC1610S080HN/C1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.65 | $346.50 |
| 100 | $30.2 | $3,020.00 |
| 500 | $26.8 | $13,400.00 |
| 1,000 | $23.95 | $23,950.00 |
| 3,000 | $21.4 | $64,200.00 |
ADC1610S080HN/C1 概要
An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous analog signals into discrete digital codes for processing by microcontrollers, DSPs, or FPGAs. The pipelined ADC architecture, used in the ADC1610S080HN/C1, is favored for high-speed sampling at 10-250 Msps because it balances speed, resolution, and power efficiency: each pipeline stage resolves a subset of bits while the next sample is acquired, enabling sub-microsecond conversion latencies with 14-16 bit resolution.
Key features of the ADC1610S080HN/C1 include a 16-bit resolution, 80 Msps sampling rate (one of four speed grades in the family: 65/80/105/125 Msps), configurable LVDS DDR or CMOS digital outputs for host interface flexibility, low-latency pipelined architecture, and a wide analog input bandwidth suitable for IF-sampling communications and high-speed instrumentation.
The pipelined core architecture uses multi-bit-per-stage residue amplification with foreground calibration to maintain linearity across temperature. The LVDS DDR interface delivers output data at twice the sample clock rate to simplify board-level timing closure, while the CMOS interface allows direct connection to lower-cost FPGAs and ASICs at reduced sample rates.
Typical applications include communications infrastructure (multi-carrier base-station receivers, radar IF sampling), industrial imaging and test instrumentation, medical ultrasound front-ends, and high-speed data acquisition. The 16-bit/80 Msps combination makes it well-suited to software-defined radio (SDR) and spectrum analyzer digitizers where dynamic range and sampling bandwidth must coexist.
Designers should pay attention to the front-end analog input network: a transformer-coupled or differential amplifier drives the ADC inputs while the LVDS/CMOS output mode must be configured via the SPI control interface. Decoupling and PCB layout around the 40-pin HVQFN exposed pad is critical to maintain SNR above datasheet minimums.
This page synthesizes distributor pricing from NXP-channel sources, drop-in same-package alternatives from the ADC161x family, and PCB/analog-input design notes not duplicated in the manufacturer datasheet.
ドロップイン代替品: ADC1610S080HN/C1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC1610S080HN/C1 （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Data Interface, Number of Channels, Sampling Rate.
クイック比較ツール — 並列比較する代替部品を選択:
ADC1610S065HN/C1
✅ ドロップイン✓ 在庫あり
$21.6 / 個
データシートを見る →ADC1610S105HN/C1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1610S125HN/C1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1610S080HN/C1;5
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1410S105HN-C1
✅ ドロップイン✓ 在庫あり
$17.8 / 個
データシートを見る →ADC1610S080HN/C1 最大定格＆電気的特性
| 分解能 | 16 bit |
| Number of Channels | 1 Input |
| サンプリングレート | 80 Msps |
| Architecture | Pipelined |
| Digital Output Interface | CMOS or LVDS DDR (configurable) |
| Input Configuration | Differential (typical) |
| Data Interface | Serial, SPI (control) |
| パッケージ | 40-HVQFN (6x6 mm, 0.85 mm height) |
| Package Outline | SOT618-1 / MO-220 (plastic, exposed pad) |
| ピン数 | 40 |
| 動作温度 | -40C to +85C (Industrial) |
| 実装タイプ | Surface Mount |
| Terminal Form | No Lead (HVQCCN) |
| Screening Level | Industrial |
| RoHS ステータス | Compliant |
ADC1610S080HN/C1 ピン構成
| ピン 1 | AVSS — Analog ground (sense) |
| ピン 2 | AVDD — Analog supply voltage |
| ピン 3 | VIN+ — Differential analog input positive |
| ピン 4 | VIN- — Differential analog input negative |
| ピン 5 | CMOUT — Common-mode output for input amplifier |
| ピン 6 | REF — Reference voltage decoupling |
| ピン 7 | REFP — Reference positive output (decoupling) |
| ピン 8 | REFN — Reference negative output (decoupling) |
| ピン 9 | REFSENSE — Reference sense |
| ピン 10 | AVSS — Analog ground |
| ピン 11 | AVDD — Analog supply |
| ピン 12 | DVDD — Digital supply |
| ピン 13 | DVSS — Digital ground |
| ピン 14 | OE/SDIO — Output enable / SPI data |
| ピン 15 | SCAN_EN — Built-in test enable |
| ピン 16 | RESET — Hardware reset (active low) |
| ピン 17 | CLK+ — Differential clock positive |
| ピン 18 | CLK- — Differential clock negative |
| ピン 19 | DRVDD — Output driver supply |
| ピン 20 | D0_OB — Data output / Out of Range flag |
| ピン 21 | D1/NC — Data bit or no-connect depending on interface mode |
| ピン 22 | D2 — LVDS/CMOS data output |
| ピン 23 | D3 — LVDS/CMOS data output |
| ピン 24 | D4 — LVDS/CMOS data output |
| ピン 25 | D5 — LVDS/CMOS data output |
| ピン 26 | D6 — LVDS/CMOS data output |
| ピン 27 | D7 — LVDS/CMOS data output |
| ピン 28 | D8 — LVDS/CMOS data output |
| ピン 29 | D9 — LVDS/CMOS data output |
| ピン 30 | D10 — LVDS/CMOS data output |
| ピン 31 | D11 — LVDS/CMOS data output |
| ピン 32 | D12 — LVDS/CMOS data output |
| ピン 33 | D13 — LVDS/CMOS data output |
| ピン 34 | D14 — LVDS/CMOS data output |
| ピン 35 | D15 — LSB data output |
| ピン 36 | DRVSS — Output driver ground |
| ピン 37 | DDRCLK+ — DDR LVDS clock positive |
| ピン 38 | DDRCLK- — DDR LVDS clock negative |
| ピン 39 | CS/SCLK — SPI chip select / clock |
| ピン 40 | SDOUT — SPI serial data output |
| ピン 41 | EP — Exposed thermal pad (solder to PCB ground) |
主な用途
ADC1610S080HN/C1 の用途: 6 件s: Multi-Carrier Communications Receiver, Software Defined Radio (SDR) Front-End, Radar IF Sampling, Test & Measurement Instrumentation, Medical Ultrasound Front-End, Industrial Imaging / High-Speed Data Acquisition.
Multi-Carrier Communications Receiver
The ADC1610S080HN/C1 is well-suited for multi-carrier base-station receivers where a single RF/IF channel must be digitized at high dynamic range. Its 16-bit resolution gives ~96 dB theoretical SNR, while the 80 Msps sample rate comfortably covers a 30+ MHz IF bandwidth with margin for transition-band filter design. The LVDS DDR output mode simplifies clock-domain crossing into the FPGA baseband processor; unlike slower CMOS-output 16-bit ADCs, this part is typically paired with a transformer-coupled differential AFE for best second-order distortion suppression.
おすすめ
Software Defined Radio (SDR) Front-End
For narrowband SDR platforms the ADC1610S080HN/C1 delivers 80 Msps of 16-bit conversion directly to an FPGA signal-processing pipeline. This gives the demodulator a 40 MHz Nyquist limit, sufficient for HF/VHF bands and many UHF channels. Compared with 12-bit alternatives (e.g. ADC1213S125HN-C1), the 16-bit data preserves more headroom against spurs and intermodulation products, critical for amateur-radio, defense, and cognitive-radio products. Typical designs use a balun-driven differential input and capture the 80 Msps stream into a 16-bit DDR LVDS port of a mid-range FPGA.
おすすめ
Radar IF Sampling
The ADC1610S080HN/C1's wide analog front-end bandwidth makes it a strong match for digitizing intermediate-frequency stages of pulsed and FMCW radar. The 16-bit dynamic range resolves small targets superimposed on clutter and ground return, while the 80 Msps rate samples the IF cleanly above its modulation bandwidth. Designers typically pair this ADC with an FPGA radar signal processor; the LVDS DDR output bus keeps the digital capture path low EMI compared to CMOS. Compared with flash-ADCs at this resolution, the pipelined approach scales better to higher channel counts where multiple receivers share a baseband board.
おすすめ
Test & Measurement Instrumentation
In benchtop spectrum analyzers, transient digitizers and oscilloscope front-ends the ADC1610S080HN/C1 offers a useful compromise of 16-bit vertical resolution and 80 Msps throughput. The part captures modulated waveforms and transient pulses with ENOB that exceeds typical 14-bit instrumentation ADCs in the same price tier. The SPI control port allows hardware-trigger synchronization to other measurement paths. Compared with successive-approximation ADCs (e.g. AD7983BCPZ), the pipelined architecture here samples continuously rather than per-conversion, enabling non-stop waveform capture in imaging and process control.
おすすめ
Medical Ultrasound Front-End
Beamformer digital receivers in mid-tier ultrasound carts use 16-bit ADCs like the ADC1610S080HN/C1 per channel. Here, the -40C to +85C industrial grade, the 16-bit resolution for tissue-harmonic imaging, and the 80 Msps rate supporting 40 MHz RF-modulated bandwidth all align with the application. The exposed-pad HVQFN package allows dense PCB layout in densely-populated 64-128 channel probe boards. Unlike B-mode front-ends built with 12-bit converters, the 16-bit data preserves fine grayscale motion-discrimination for cardiac imaging.
おすすめ
Industrial Imaging / High-Speed Data Acquisition
Machine-vision frame-grabbers and high-accuracy data-acquisition systems for vibration analysis, sonar and seismic equipment rely on 16-bit ADCs at 65-105 Msps to capture fast but precise analog events. The ADC1610S080HN/C1 provides the resolution needed to digitize small sensor signals from accelerometers or hydrophones while its 80 Msps rate guarantees capture of acoustic and vibration frequencies without aliasing. The LVDS DDR digital output and compact HVQFN footprint simplify multi-board stack-ups compared with older TSSOP-packaged ADCs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC1610S080HN/C1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC1610S065HN/C1 | ADC1610S105HN/C1 | ADC1610S125HN/C1 | ADC1610S080HN/C1;5 | ADC1410S105HN-C1 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors (Renesas-channel stock) | NXP Semiconductors |
| Package | 40-HVQFN (6x6) | 40-HVQFN (6x6) - same | 40-HVQFN (6x6) - same | 40-HVQFN (6x6) - same | 40-HVQFN (6x6) - same | 40-HVQFN (6x6) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 14 bit |
| Sampling Rate | 80 Msps | 65 Msps (-19%) | 105 Msps (+31%) | 125 Msps (+56%) | 80 Msps | 105 Msps (+31%) |
| Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Digital Output | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主な差別化要因
- Wide sample-rate flexibility in same package （vs Cross-brand 16-bit ADCs (e.g. AD9268XCPZ-125))
- Configurable CMOS or LVDS DDR output in a single part （vs ADC1410S105HN-C1)
- Industrial temperature range across the entire ADC1610S family （vs Consumer-grade cross-brand ADCs of similar speed)
設計ノート
The exposed thermal pad (pin 41 of the 40-HVQFN outline) is the primary heat path: solder it to a continuous PCB ground plane with thermal vias (recommend a 3x3 array of 0.3 mm vias tied to inner/inner copper layers). Without adequate grounding and thermal conduction the part can lose ~0.5 LSB of linearity and several dB of spurious-free dynamic range. Estimated: with 4-layer 1 oz FR-4 board and 2 cm square of copper area, theta_JA is ~25 C/W.
Estimated: separate analog AVDD and digital DVDD supplies with a ferrite-bead or pi-filter (10 ohm + 10 uF + 10 uF) for noise isolation. Place 100 nF X7R ceramic decoupling as close as possible to each supply pin; add 10 uF bulk ceramic on AVSS-AVDD and DVSS-DVDD pairs. LVDS output DRVDD should also be filtered separately - failing to do so couples switching noise back into the analog reference path, visible as elevated noise floor in the ADC FFT plot.
Differential analog inputs (VIN+/VIN-) require a front-end transformer or differential amplifier (e.g. fully-differential op-amp driver) - never drive the ADC single-ended, since common-mode noise will degrade SNR by >10 dB. The DDRCLK+/- lines are the most critical: route them as 100 ohm differential microstrip with length matching to within 150 mil of the corresponding data bits. Avoid routing LVDS above or near noisy digital regions such as the FPGA SERDES lanes.
Many designers overlook the SPI configuration - the output mode (CMOS vs LVDS DDR), the output format (offset binary vs two's complement) and the internal reference (internal vs external) MUST be set via SPI at start-up, otherwise the part defaults to an internal test or low-power mode. Always issue a hardware reset on power-up and confirm reading back status register 0x00 via the SDOUT pin before enabling the clock; otherwise the ADC may not deliver data on the LVDS bus.
コンプライアンス情報
RoHS-compliant per NXP manufacturer page for the SOT618-1 (HVQFN-40) package family. Not AEC-Q100 qualified - this part is designed for industrial -40C/+85C use, not automotive. Halogen-free status not specifically stated in the verified web data so marked unknown.
