ADS6129IRGZ25 - 12-Bit 250MSPS Low-Power ADC | Texas Instruments
部品番号: ADS6129IRGZ25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $29.8 | $2,980.00 |
| 500 | $26.5 | $13,250.00 |
| 1,000 | $23.1 | $23,100.00 |
ADS6129IRGZ25 概要
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that processes the analog input through a cascade of low-resolution sub-ADC stages, each performing a coarse quantization followed by a residue amplification to the next stage. This architecture trades latency for throughput and dominates the >100 MSPS speed class because it scales efficiently with process technology. Pipelined ADCs sit hierarchically under successive-approximation (SAR) and flash ADCs in the high-speed converter tree, with sub-categories such as low-power pipelined, high-SFDR pipelined, and pipelined-with-LVDS-output families.
Key features include 70 dBFS SNR at 100 MHz input, 85 dBc SFDR, an integrated high-bandwidth track-and-hold, internal reference, and programmable digital output modes. The LVDS DDR interface allows a single data-rate clock while emitting data on both rising and falling edges, simplifying FPGA capture at 250 MSPS. The CMOS mode permits direct 12-bit parallel bus connection to ASICs and DSPs. Internal register programming supports gain, offset, and test-pattern modes for board-level diagnostics.
The ADS6129 uses a switched-capacitor front-end optimized for differential transformer-coupled inputs of 2 Vpp full-scale, with common-mode voltage set by the internal reference. The architecture achieves 1.5 GHz usable analog input bandwidth, enabling undersampling of IF signals up to 400 MHz. Power scales roughly linearly with fS, dropping to ~330 mW at 210 MSPS for power-constrained designs.
Typical applications include multi-carrier wireless infrastructure (LTE, MC-GSM), software-defined radio (SDR), power amplifier linearization feedback paths, 802.16d/e WiMAX base stations, radar systems, medical imaging digitizers, and high-definition video capture. The combination of low power and high SFDR makes it especially attractive for dense multi-channel receiver cards.
When designing with this part, ensure the analog input is AC-coupled through a 1:1 or 1:2 transformer and that the LVDS/CMOS termination matches the receiver impedance. Decouple AVDD and DRVDD separately and keep the exposed thermal pad soldered to a continuous ground plane for the rated thermal performance.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes for the ADS6129IRGZ25 not found in the manufacturer datasheet alone.
ドロップイン代替品: ADS6129IRGZ25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS6129IRGZ25 （同一形状・フットプリント） — 相違点: Package, Operating Temperature Range, Resolution, Input Type, Number of Channels.
クイック比較ツール — 並列比較する代替部品を選択:
ADS6149IRGZ25
✅ ドロップイン✓ 在庫あり
$20.85 / 個
データシートを見る →ADS6128IRGZ25
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS6148IRGZ25
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$52.1 / 個
データシートを見る →ADS6129IRGZT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS6149IRGZT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS6129IRGZ25 最大定格＆電気的特性
| 分解能 | 12 bit |
| Sample Rate | 250 MSPS |
| Number of Input Channels | 1 |
| Architecture | Pipelined |
| Input Type | Differential |
| Data Output Interface | LVDS DDR / Parallel CMOS |
| Analog Supply Voltage | 1.8 V to 3.3 V |
| Digital Supply Voltage | 1.8 V to 3.3 V |
| Power Dissipation (CMOS, 250 MSPS) | 430 mW |
| SNR | 70 dBFS (typ at 100 MHz input) |
| SFDR | 85 dBc (typ) |
| Analog Input Bandwidth | 1.5 GHz (typ) |
| Full-Scale Input | 2 Vpp differential |
| 動作温度範囲 | -40 °C to +85 °C |
| パッケージ | 48-VQFN (7x7 mm) with thermal pad |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
ADS6129IRGZ25 ピン構成
| ピン 1 | AVDD — Analog supply, 1.8-3.3 V |
| ピン 2 | INP — Differential analog input positive |
| ピン 3 | INM — Differential analog input negative |
| ピン 4 | VCM — Common-mode voltage output |
| ピン 5 | REFT — Top reference decoupling |
| ピン 6 | REFB — Bottom reference decoupling |
| ピン 7 | AVDD — Analog supply, 1.8-3.3 V |
| ピン 8 | AVSS — Analog ground |
| ピン 9 | SENSE — Reference configuration / external reference input |
| ピン 10 | RESET — Hardware reset, active low |
| ピン 11 | SCLK — Serial interface clock |
| ピン 12 | SDENB — Serial interface enable, active low |
| ピン 13 | SDIO — Serial interface data |
| ピン 14 | PDN — Power-down mode, active high |
| ピン 15 | AVDD — Analog supply, 1.8-3.3 V |
| ピン 16 | AVSS — Analog ground |
| ピン 17 | NC — Not connected (per datasheet) |
| ピン 18 | NC — Not connected (per datasheet) |
| ピン 19 | DRVDD — Digital output supply, 1.8-3.3 V |
| ピン 20 | DRVSS — Digital ground |
| ピン 21 | D11 — CMOS data output bit 11 (MSB) / LVDS data |
| ピン 22 | D10 — CMOS data output bit 10 / LVDS data |
| ピン 23 | D9 — CMOS data output bit 9 / LVDS data |
| ピン 24 | D8 — CMOS data output bit 8 / LVDS data |
| ピン 25 | D7 — CMOS data output bit 7 / LVDS data |
| ピン 26 | D6 — CMOS data output bit 6 / LVDS data |
| ピン 27 | D5 — CMOS data output bit 5 / LVDS data |
| ピン 28 | D4 — CMOS data output bit 4 / LVDS data |
| ピン 29 | DRVDD — Digital output supply, 1.8-3.3 V |
| ピン 30 | DRVSS — Digital ground |
| ピン 31 | D3 — CMOS data output bit 3 / LVDS data |
| ピン 32 | D2 — CMOS data output bit 2 / LVDS data |
| ピン 33 | D1 — CMOS data output bit 1 / LVDS data |
| ピン 34 | D0 — CMOS data output bit 0 (LSB) / LVDS data |
| ピン 35 | DRVDD — Digital output supply, 1.8-3.3 V |
| ピン 36 | CLKOUT — Output clock / DDR clock |
| ピン 37 | DRVSS — Digital ground |
| ピン 38 | CLKP — Differential input clock positive |
| ピン 39 | CLKM — Differential input clock negative |
| ピン 40 | AVDD — Analog supply, 1.8-3.3 V |
| ピン 41 | AVSS — Analog ground |
| ピン 42 | AVSS — Analog ground |
| ピン 43 | AVDD — Analog supply, 1.8-3.3 V |
| ピン 44 | NC — Not connected (per datasheet) |
| ピン 45 | NC — Not connected (per datasheet) |
| ピン 46 | AVDD — Analog supply, 1.8-3.3 V |
| ピン 47 | AVSS — Analog ground |
| ピン 48 | AVDD — Analog supply, 1.8-3.3 V |
主な用途
ADS6129IRGZ25 の用途: 8 件s: Multi-Carrier Wireless Infrastructure, Software Defined Radio (SDR), Power Amplifier Linearization (DPD), 802.16d/e WiMAX Base Stations, Test and Measurement Instrumentation, Medical Imaging and Ultrasound, Radar and Defense Signal Chains, High-Definition Video Capture.
Multi-Carrier Wireless Infrastructure
The ADS6129IRGZ25 is widely deployed in multi-carrier wireless base-station receivers where it digitizes the IF output of the analog down-conversion chain. With 70 dBFS SNR, 85 dBc SFDR, and a 1.5 GHz analog input bandwidth, the converter comfortably handles multi-carrier GSM, LTE, and MC-GSM aggregation, where the in-band signal density demands low spurious content. Operated at the full 250 MSPS rate with LVDS DDR output to a Virtex-6 or Kintex-7 FPGA, the part draws ~430 mW - lower than competing 14-bit converters - making it ideal for dense receiver cards. The wide 1.8-3.3 V supply tolerance lets the same PCB drive both 1.8 V FPGAs and 3.3 V ASICs without redesign, reducing platform NRE.
おすすめ
Software Defined Radio (SDR)
In software-defined radio platforms the ADS6129IRGZ25 acts as the front-end digitizer directly sampling IF or low-RF signals up to several hundred MHz, eliminating analog mixing and filtering stages. Its 1.5 GHz input bandwidth supports undersampling of 70-400 MHz IF blocks, while the 250 MSPS throughput preserves Nyquist margin for wideband digital down-conversion in the FPGA. The pin-to-pin 14-bit sibling (ADS6149) lets the same PCB re-use the digital backend across SDR tiers. Lower power (~430 mW vs ~750 mW for older 14-bit ADCs) extends battery life in manpack radios, and the LVDS DDR interface simplifies FPGA capture at full rate.
おすすめ
Power Amplifier Linearization (DPD)
Cellular base-station power amplifiers require digital pre-distortion feedback paths with high SFDR to capture intermodulation products cleanly. The ADS6129IRGZ25's 85 dBc SFDR and 70 dBFS SNR make it well-suited for sampling the PA output coupler signal at IF, feeding the DPD engine that linearizes the PA. The 250 MSPS throughput captures up to 100 MHz of observation bandwidth, sufficient for 5G NR and LTE carriers. The 48-VQFN footprint lets OEM platform designers maintain a single PCB layout across multiple PA power tiers, choosing the 14-bit ADS6149 for higher-end macro radios and the 12-bit ADS6129 for small cells.
おすすめ
802.16d/e WiMAX Base Stations
Legacy 802.16d/e WiMAX base-station receivers remain in production across several emerging-market operators. The ADS6129IRGZ25 was designed into this segment because its 250 MSPS rate covers the full WiMAX channel bandwidth with margin, and its low power dissipation allows multi-sector base-station chassis to be densely populated without thermal redesign. AC-coupled transformer input (1:2 turns ratio) feeds the differential front-end while the LVDS DDR output streams data into the baseband processor. The industrial -40 to +85 °C temperature range supports outdoor cabinet deployment.
おすすめ
Test and Measurement Instrumentation
Bench-top spectrum analyzers, oscilloscopes, and arbitrary waveform digitizers benefit from the ADS6129IRGZ25's combination of high SFDR and wide analog input bandwidth. The 12-bit resolution and 250 MSPS sample rate produce clean acquisitions up to 125 MHz Nyquist, while the 1.5 GHz input bandwidth supports harmonic and intermodulation analysis well beyond Nyquist. The CMOS parallel output mode simplifies connection to mid-range FPGAs and microcontrollers without an LVDS deserializer. Designers building modular instrumentation platforms choose the 14-bit ADS6149 as a drop-in pin-compatible option for higher-precision SKUs.
おすすめ
Medical Imaging and Ultrasound
Cart-based and point-of-care ultrasound systems use multi-channel ADC arrays to digitize beamformed RF signals after the TGC stage. The ADS6129IRGZ25's 70 dBFS SNR preserves the dynamic range needed to detect low-contrast tissue boundaries, while its 250 MSPS rate captures 50-100 MHz RF with margin. The 48-VQFN footprint lets designers place one ADC per channel in a small PCB area - a typical 32-channel system fits into a single PCIE card. Lower power per channel reduces thermal load on the imaging probe head. The pin-compatible 14-bit ADS6149 serves high-end radiography and CT gantry sampling SKUs.
おすすめ
Radar and Defense Signal Chains
Phased-array radar and electronic-warfare receivers use the ADS6129IRGZ25 to digitize wideband IF after down-conversion, leveraging its 85 dBc SFDR for clean spectral captures. The 1.5 GHz input bandwidth supports direct IF sampling at L-band, S-band, and C-band downconverters, while the 250 MSPS throughput preserves Nyquist margin for full-bandwidth recording. The industrial -40 to +85 °C temperature range supports outdoor and vehicle-mounted platforms. The same PCB layout can be reused with the pin-compatible 14-bit ADS6149 for higher-resolution surveillance receivers.
おすすめ
High-Definition Video Capture
High-definition video broadcast equipment (SDI capture cards, video routing equipment) uses the ADS6129IRGZ25 to digitize wideband analog component video. The 250 MSPS rate oversamples the 1080p / 148.5 MHz pixel clock and supports 4:4:4 and 4:2:2 component video formats with low noise. The CMOS parallel output mode simplifies connection to video processing ASICs without an LVDS deserializer. The wide 1.8-3.3 V supply range allows integration with both legacy 3.3 V video ASICs and modern low-power video FPGAs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS6129IRGZ25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS6149IRGZ25 | ADS6128IRGZ25 | ADS6148IRGZ25 | ADS6129IRGZT | ADS6149IRGZT |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (7x7) | 48-VQFN (7x7) - same | 48-VQFN (7x7) - same | 48-VQFN (7x7) - same | 48-VQFN (7x7) - same | 48-VQFN (7x7) - same |
| Resolution | 12 bit | 14 bit | 12 bit | 14 bit | 12 bit | 14 bit |
| Sample Rate | 250 MSPS | 250 MSPS | 210 MSPS | 210 MSPS | 250 MSPS | 250 MSPS |
| Power Dissipation (CMOS, max fS) | 430 mW | 490 mW | 330 mW | 390 mW | 430 mW | 490 mW |
| SNR (typ, 100 MHz) | 70 dBFS | 74 dBFS | 70 dBFS | 74 dBFS | 70 dBFS | 74 dBFS |
| SFDR (typ) | 85 dBc | 85 dBc | 85 dBc | 85 dBc | 85 dBc | 85 dBc |
| Output Interface | LVDS DDR / Parallel CMOS | LVDS DDR / Parallel CMOS | LVDS DDR / Parallel CMOS | LVDS DDR / Parallel CMOS | LVDS DDR / Parallel CMOS | LVDS DDR / Parallel CMOS |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Approx. Unit Price (qty 1000, as of 2026-10-11) | $23.10 | $35-40 | $20-22 | $32-36 | $23.10 | $35-40 |
主な差別化要因
- Lowest power in 12-bit/250 MSPS class with full pin-compatibility to 14-bit ADS6149 （vs ADS6149IRGZ25)
- Drop-in compatible with 210 MSPS ADS6128 for system-level speed tiering （vs ADS6128IRGZ25)
- Wide 1.8-3.3 V supply range supports both legacy and modern logic interfaces （vs AD9633BCPZ-250)
設計ノート
Use a continuous, unbroken ground plane on layer 2 directly under the ADS6129IRGZ25 to provide a low-impedance return path for the high-speed analog and clock currents. Decouple each AVDD pin with a 0.1 µF X7R 0402B/0603 chip cap placed within 2 mm of the pin, and add a 10 µF bulk tantalum or ceramic bypass at the device side of the ferrite bead that isolates AVDD from DRVDD. Failure to isolate AVDD and DRVDD supplies with a ferrite bead typically degrades SFDR by 5-8 dB due to digital switching noise coupling into the analog front-end.
The exposed thermal pad (EP) of the 48-VQFN package must be soldered to a 7x7 mm copper pad on the top layer, stitched with at least nine thermal vias (0.3 mm drill, 0.6 mm pitch) to the internal ground plane. Without proper EP soldering, theta_JA rises from ~30 °C/W to over 60 °C/W, which can cause the device to enter thermal shutdown at full 250 MSPS CMOS operation in still air. Estimated: at 430 mW dissipation the junction rises 13 °C above ambient with the EP properly soldered versus 26 °C without.
Drive CLKP/CLKM with a low-jitter differential source (typically a dedicated clock jitter cleaner such as the LMK04828) to achieve sub-200 fs RMS aperture jitter required for 70 dBFS SNR at 250 MSPS. The CLKP/CLKM traces must be length-matched within 1 mm and routed as a 100 ohm differential pair on the top layer over a continuous ground plane; avoid via transitions on these critical nets. Skew between CLKP and CLKM directly translates to aperture jitter, which degrades SNR at high input frequencies.
Do not operate the analog input outside 0.5-2.5 V common-mode range - violation causes permanent damage or latch-up. When using parallel CMOS output mode, place a 100 ohm series termination resistor at each D0-D11 output within 5 mm of the ADC to dampen reflections on the bus to the FPGA/ASIC. Pull PDN high only after AVDD and DRVDD have stabilized; pulling PDN high while supplies are ramping can put the device into an undefined state that requires a RESET pulse to recover.
コンプライアンス情報
RoHS compliant and lead-free per TI product page and datasheet ordering information. AEC-Q100 not applicable - this is a commercial/industrial-grade ADC; for automotive ADCs from TI see the ADS7xxx-Q1 family.
