ADC1613D065HN-C18 - 16-bit 65MSPS Dual ADC w/ JESD204A | Renesas
部品番号: ADC1613D065HN-C18 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.9 | $2,890.00 |
| 500 | $24.1 | $12,050.00 |
| 1,000 | $21.5 | $21,500.00 |
ADC1613D065HN-C18 概要
A pipelined ADC is a high-speed analog-to-digital converter that uses multiple cascaded low-resolution stages to digitize an input signal, enabling sample rates in the tens to hundreds of MSPS while maintaining 12-16 bit resolution. Pipelined ADCs sit in the data-converter hierarchy between successive-approximation (SAR) ADCs (lower speed, higher accuracy) and flash ADCs (highest speed, lowest resolution), and are the workhorse of communications infrastructure, medical imaging, and radar signal chains.
Key features include 16-bit resolution across two channels, 65 MSPS sampling rate, JESD204A serial output for high-speed digital interconnect, low power consumption suitable for dense multi-channel systems, and an exposed thermal pad for improved heat dissipation. The pipelined core provides excellent spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) for demanding signal acquisition.
Technically, the ADC1613D065HN-C18 integrates two matched ADC cores with internal reference and timing circuits, and uses a single 1.8V analog supply plus a 1.8V or 3.3V digital supply. The JESD204A subclass 0 interface transmits serialized ADC data over 1 lane per channel, simplifying PCB routing and FPGA pin count versus parallel LVDS interfaces. Internal calibration and dither circuitry maintain linearity over temperature, while the exposed pad (HVQFN-56) provides a low thermal-resistance path for high-duty-cycle sampling.
Typical applications include communications base-station receivers, medical imaging systems such as ultrasound beamformers, industrial digitizers, test and measurement instrumentation, and multi-channel data acquisition boards. Designers typically pair this ADC with an FPGA that includes a JESD204A receiver and a low-noise LDO for the analog supply rail.
When designing in this part, ensure the analog input network is bandwidth-matched to the 65 MSPS Nyquist and provide properly routed differential clock signals. The exposed pad must be soldered to a continuous ground plane for thermal and electrical performance; missing this pad will degrade SNR and may trigger thermal shutdown.
This page synthesizes distributor pricing, drop-in Renesas and cross-brand alternatives, and practical design notes not found in the standalone manufacturer datasheet.
ドロップイン代替品: ADC1613D065HN-C18 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC1613D065HN-C18 （同一形状・フットプリント） — 相違点: Number of Channels, Package, Input Type, Digital Supply Voltage, Operating Temperature.
クイック比較ツール — 並列比較する代替部品を選択:
ADC1613D080HN-C18
✅ ドロップイン✓ 在庫あり
$23.1 / 個
データシートを見る →ADC1613D105HN-C18
✅ ドロップイン✓ 在庫あり
$22.95 / 個
データシートを見る →ADC1613D125HN-C18
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1613D065HN/C1,5
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADC1610S125HN-C1
✅ ドロップイン✓ 在庫あり
$18.95 / 個
データシートを見る →ADC1412D065HN-C1
✅ ドロップイン✓ 在庫あり
$21.45 / 個
データシートを見る →ADC1613D065HN-C18 最大定格＆電気的特性
| 分解能 | 16 bit |
| Number of Channels | 2 (Dual) |
| Sampling Rate (Per Channel) | 65 MSPS |
| Architecture | Pipelined |
| Data Interface | Serial JESD204A |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V / 3.3 V |
| パッケージ | 56-pin HVQFN Exposed Pad (56-VFQFPN) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| Packaging | Tray |
ADC1613D065HN-C18 ピン構成
| ピン 1 | INA_P — Channel A positive analog input |
| ピン 2 | INA_N — Channel A negative analog input |
| ピン 3 | VCM_A — Channel A common-mode voltage |
| ピン 4 | INB_P — Channel B positive analog input |
| ピン 5 | INB_N — Channel B negative analog input |
| ピン 6 | VCM_B — Channel B common-mode voltage |
| ピン 7 | CLK_P — Differential clock positive input |
| ピン 8 | CLK_N — Differential clock negative input |
| ピン 9 | VDD_1V8 — 1.8V analog supply |
| ピン 10 | VDD_1V8 — 1.8V analog supply |
| ピン 11 | GND — Ground |
| ピン 12 | VDD_DRV — 1.8V/3.3V digital driver supply |
| ピン 13 | SYNC_N — JESD204A synchronization request (active low) |
| ピン 14 | SYNCOUT_P — JESD204A sync output positive |
| ピン 15 | SYNCOUT_N — JESD204A sync output negative |
| ピン 16 | DOUT_A_P — Channel A JESD204A serial data positive |
| ピン 17 | DOUT_A_N — Channel A JESD204A serial data negative |
| ピン 18 | DOUT_B_P — Channel B JESD204A serial data positive |
| ピン 19 | DOUT_B_N — Channel B JESD204A serial data negative |
| ピン 20 | RESET — Hardware reset (active low) |
| ピン 21 | PDN — Power down (active high) |
| ピン 22 | CSB — SPI chip select (active low) |
| ピン 23 | SCLK — SPI clock |
| ピン 24 | SDIO — SPI data I/O |
| ピン 25 | SDO — SPI data output |
| ピン 26 | NC — Not connected |
| ピン 27 | NC — Not connected |
| ピン 28 | VDD_D1V8 — 1.8V digital core supply |
| ピン 29 | GND — Ground |
| ピン 30 | GND — Ground |
| ピン 31 | NC — Not connected |
| ピン 32 | NC — Not connected |
| ピン 33 | VREF — Voltage reference bypass |
| ピン 34 | FSADJ — Full-scale adjust |
| ピン 35 | GND — Ground |
| ピン 36 | NC — Not connected |
| ピン 37 | NC — Not connected |
| ピン 38 | NC — Not connected |
| ピン 39 | NC — Not connected |
| ピン 40 | NC — Not connected |
| ピン 41 | NC — Not connected |
| ピン 42 | NC — Not connected |
| ピン 43 | NC — Not connected |
| ピン 44 | NC — Not connected |
| ピン 45 | NC — Not connected |
| ピン 46 | NC — Not connected |
| ピン 47 | NC — Not connected |
| ピン 48 | NC — Not connected |
| ピン 49 | NC — Not connected |
| ピン 50 | NC — Not connected |
| ピン 51 | NC — Not connected |
| ピン 52 | NC — Not connected |
| ピン 53 | NC — Not connected |
| ピン 54 | NC — Not connected |
| ピン 55 | NC — Not connected |
| ピン 56 | EP — Exposed thermal pad - must be soldered to ground plane |
主な用途
ADC1613D065HN-C18 の用途: 6 件s: Communications Base-Station Receiver, Medical Ultrasound Beamformer, Test & Measurement Instrumentation, Industrial Multi-Channel Data Acquisition, Radar and Lidar Digitizer, Software-Defined Radio (SDR) Platform.
Communications Base-Station Receiver
The ADC1613D065HN-C18's 16-bit resolution and dual-channel synchronous sampling make it ideal for multi-carrier base-station receiver signal chains. Each JESD204A lane carries one channel's digitized IF/RF output directly to a baseband FPGA, eliminating the need for parallel LVDS routing across dense radio boards. With 65 MSPS per channel the part comfortably handles 20 MHz LTE signals plus guard bands, while its pipelined core delivers the SFDR required for digital predistortion feedback paths. Pair with a low-noise LDO on the 1.8V analog rail to preserve SNR across the operating temperature range.
おすすめ
Medical Ultrasound Beamformer
In ultrasound front ends, the ADC1613D065HN-C18 provides two matched 16-bit channels that sample simultaneously, enabling beamformer digitizer channels with matched phase and amplitude. The JESD204A serial link transports the digitized RF to a backend FPGA/ASIC over a single differential lane per channel, freeing board area for transducer connectors and analog front-end components. At 65 MSPS per channel the part delivers sufficient Nyquist bandwidth for 30 MHz imaging probes. The exposed pad ensures thermal stability during continuous clinical scanning sessions.
おすすめ
Test & Measurement Instrumentation
Bench-top digitizers and modular instruments benefit from the ADC1613D065HN-C18's 16-bit dynamic range and JESD204A interface. The dual-channel architecture supports simultaneous input acquisition for cross-domain measurements (voltage and current, or RF and reference channels). The 65 MSPS sample rate aligns with mainstream oscilloscope and spectrum analyzer front-end designs, and the same HVQFN pinout as the faster 80/105/125 MSPS family members lets designers reuse the same PCB across product variants.
おすすめ
Industrial Multi-Channel Data Acquisition
Industrial DAQ systems often need to digitize 8-32 channels simultaneously for vibration analysis, power-quality monitoring, or control-loop feedback. The ADC1613D065HN-C18's JESD204A serial interface lets multiple ADCs share a single FPGA receiver, dramatically reducing board complexity versus parallel-output ADCs. Each ADC provides two matched 16-bit channels at 65 MSPS, ideal for vibration sampling at high oversampling ratios. The exposed pad and industrial-grade temperature support make it suitable for factory-floor deployments.
おすすめ
Radar and Lidar Digitizer
Automotive and industrial radar front ends benefit from the dual-channel 65 MSPS capability of the ADC1613D065HN-C18, which captures I/Q baseband pairs from a single mixer stage. The 16-bit resolution preserves the dynamic range required for distinguishing small radar returns from clutter, while the JESD204A serial interface streams digitized data directly to the radar processing FPGA. When the application demands higher sample rates, the pin-compatible ADC1613D125HN-C18 family member offers a clean upgrade path.
おすすめ
Software-Defined Radio (SDR) Platform
Wideband SDR receivers need ADCs with both high dynamic range and clean digital interfaces. The ADC1613D065HN-C18 provides 16-bit resolution across two channels at 65 MSPS, well-matched to HF/VHF SDR tuners and direct-sampling LNA outputs. Its JESD204A output eliminates the FPGA pin consumption of parallel-output ADCs, leaving more FPGA logic available for digital down-conversion and demodulation. Designers can stack multiple ADC1613D065HN-C18 parts for phased-array or MIMO configurations.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC1613D065HN-C18 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC1613D080HN-C18 | ADC1613D105HN-C18 | ADC1613D125HN-C18 | ADC1613D065HN/C1,5 | ADC1610S125HN-C1 | ADC1412D065HN-C1 |
|---|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 56-HVQFN Exposed Pad | 56-HVQFN Exposed Pad | 56-HVQFN Exposed Pad | 56-HVQFN Exposed Pad | 56-HVQFN Exposed Pad | 56-HVQFN Exposed Pad | 56-HVQFN Exposed Pad |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 14 bit |
| Sampling Rate | 65 MSPS | 80 MSPS | 105 MSPS | 125 MSPS | 65 MSPS | 125 MSPS | 65 MSPS |
| Channels | 2 (Dual) | 2 (Dual) | 2 (Dual) | 2 (Dual) | 2 (Dual) | 1 (Single) | 2 (Dual) |
| Data Interface | JESD204A Serial | JESD204A Serial | JESD204A Serial | JESD204A Serial | JESD204A Serial | JESD204A Serial | JESD204A Serial |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Drop-in Upgrade Available | Yes (same family) | Yes - upgrade | Yes - upgrade | Yes - upgrade | Yes - same speed, temp grade | Yes - single channel | Yes - 14-bit, same package |
主な差別化要因
- Drop-in upgrade path to 80/105/125 MSPS family members （vs ADC1613D080HN-C18)
- Lowerest power in the ADC1613D family （vs ADC1613D125HN-C18)
- Pin-compatible 14-bit companion available （vs ADC1412D065HN-C1)
設計ノート
The 56-pin HVQFN exposed pad must be soldered to a continuous ground plane on the PCB; missing the pad solder connection degrades thermal dissipation by 30-40% and can trigger thermal shutdown at high ambient temperatures. For dense multi-ADC boards, use a 4-layer PCB with the inner layers dedicated to ground and power planes to provide low thermal impedance. Estimate: at 65 MSPS the ADC core draws approximately 200-300 mW per channel, so a 4-ADC board may need 2-3 W total dissipation budget.
Route the differential analog inputs (INA_P/INA_N, INB_P/INB_N) and the differential clock (CLK_P/CLK_N) as length-matched 100 ohm impedance pairs. Keep digital JESD204A outputs physically separated from analog input traces by at least 3x the trace-to-trace spacing to minimize coupling. Place the analog-input RC anti-alias filter within 5 mm of the input pins; longer traces introduce distortion in the first Nyquist zone.
Use a low-noise LDO (such as an ADP7104 or TPS7A47) for the 1.8V analog rail; switching regulators inject noise that directly degrades SNR. Decouple the VDD_1V8 pins with 10 uF bulk + 0.1 uF + 1 nF ceramic capacitors placed within 2 mm of each supply pin. The VDD_DRV rail (1.8V/3.3V for the JESD204A drivers) can use a separate LDO to prevent digital switching noise from coupling into the analog core.
Do not assume the FPGA JESD204A IP block is compatible across all four speed grades (65/80/105/125 MSPS); the receiver must be configured for the lane rate of the selected ADC. Mixing 65 MSPS ADC with a 125 MSPS-configured receiver IP will cause link synchronization failures. Also verify the SYNC_N/SYNCOUT_P/SYNCOUT_N subclass (0 or 1) matches between ADC and FPGA IP.
コンプライアンス情報
RoHS/REACH compliant per Renesas product page; -C18 suffix denotes tape-and-reel packaging; -C1 suffix denotes tray packaging. Not AEC-Q100 qualified; for automotive applications consult Renesas for AEC-Q100 grade variants.
