ADC1613D105HN-C18 - Dual 16-Bit 105MSPS JESD204A ADC | Renesas
部品番号: ADC1613D105HN-C18 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $30.85 | $3,085.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $22.95 | $22,950.00 |
ADC1613D105HN-C18 概要
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes, enabling downstream DSP, FPGA, or ASIC processing. Pipelined ADCs use a multi-stage architecture to achieve high sample rates while maintaining low latency and moderate resolution - in this case 16 bits at 105 MSPS. ADCs sit within the broader hierarchy of data converter -> signal chain IC -> semiconductor, and are critical in any system that bridges the analog and digital domains. The ADC1613D105HN-C18 belongs to the high-speed, JESD204A-serial-output family that reduces parallel LVDS routing in dense boards.
Key features include dual simultaneously-sampling channels, 16-bit resolution, 105 MSPS maximum sample rate per channel, a serial JESD204A-compliant interface, integrated input buffer, internal reference, and low power consumption optimized for portable and high-density designs. The C18 suffix denotes the 105 MSPS speed grade and the 56-VFQFPN exposed-pad package. It operates from a 1.8 V analog supply and 3.3 V digital supply, supports a 2 Vpp differential full-scale input, and achieves excellent SFDR and SNR performance over industrial temperature ranges.
The pipelined architecture uses successive low-resolution stages with digital error correction, allowing per-channel throughput to exceed 100 MSPS while keeping analog input bandwidth wide. The JESD204A serial interface consolidates data onto 1-2 high-speed CML lanes, eliminating the 16+ parallel LVDS pairs that legacy parallel-output ADCs require - dramatically simplifying PCB layout and reducing EMI in dense multi-channel systems.
Typical applications include 3G/4G multi-carrier base-station receivers, software-defined radio (SDR) platforms, radar and lidar digitizing front-ends, medical imaging (ultrasound beamformers), and high-speed test and measurement instrumentation. The dual-channel architecture is particularly efficient for I/Q demodulation and diversity receiver paths.
When designing with this part, ensure that the JESD204A link parameters (L, M, F, K, N) are configured to match the receiving FPGA or ASIC, and that the PCB provides a clean low-noise analog supply with adequate decoupling on each supply pin. Thermal management of the exposed pad is critical - use a sufficiently large copper pour to keep junction temperature within the -40C to +85C operating range.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and design-in.
ドロップイン代替品: ADC1613D105HN-C18 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC1613D105HN-C18 （同一形状・フットプリント） — 相違点: Package, Number of Channels, Input Type, Operating Temperature, Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
ADC1613D125HN-C18
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1613D105HN-C1
✅ ドロップイン✓ 在庫あり
$19.4 / 個
データシートを見る →ADC1613D080HN-C18
✅ ドロップイン✓ 在庫あり
$23.1 / 個
データシートを見る →ADC1213S125HN-C1
✅ ドロップイン✓ 在庫あり
$18.45 / 個
データシートを見る →ADC1213D080HN-C18
✅ ドロップイン✓ 在庫あり
$21.75 / 個
データシートを見る →ADC1412D065HN-C1
✅ ドロップイン✓ 在庫あり
$21.45 / 個
データシートを見る →ADC1610S125HN-C1
✅ ドロップイン✓ 在庫あり
$18.95 / 個
データシートを見る →ADC1613D105HN-C18 最大定格＆電気的特性
| 分解能 | 16 bits |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate (max) | 105 MSPS per channel |
| Architecture | Pipelined |
| Data Interface | Serial JESD204A |
| Input Type | Differential |
| Input Range | 2 Vpp differential (full-scale) |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 3.3 V |
| パッケージ / ケース | 56-VFQFPN Exposed Pad (56-HVQFN, 8x8 mm) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C |
| Packaging | Tray |
| RoHS ステータス | Compliant |
| Speed Grade Suffix | C18 = 105 MSPS grade |
ADC1613D105HN-C18 ピン構成
| ピン 1 | AIN1P — Analog Input 1 Positive (differential) |
| ピン 2 | AIN1N — Analog Input 1 Negative (differential) |
| ピン 3 | AVDD — Analog 1.8V Supply |
| ピン 4 | VCM — Common-mode voltage output |
| ピン 5 | AVDD — Analog 1.8V Supply |
| ピン 6 | AIN2P — Analog Input 2 Positive (differential) |
| ピン 7 | AIN2N — Analog Input 2 Negative (differential) |
| ピン 8 | AGND — Analog Ground |
| ピン 9 | REFT — Top Reference Decoupling |
| ピン 10 | REFB — Bottom Reference Decoupling |
| ピン 11 | AGND — Analog Ground |
| ピン 12 | AVDD — Analog 1.8V Supply |
| ピン 13 | CLK+ — Differential Clock Input Positive |
| ピン 14 | CLK- — Differential Clock Input Negative |
| ピン 15 | AGND — Analog Ground |
| ピン 16 | AVDD — Analog 1.8V Supply |
| ピン 17 | SYNC~ — JESD204A Sync Request (active low) |
| ピン 18 | DVDD — Digital 3.3V Supply |
| ピン 19 | DGND — Digital Ground |
| ピン 20 | SCLK — SPI Serial Clock |
| ピン 21 | SDIO — SPI Serial Data I/O |
| ピン 22 | CS~ — SPI Chip Select (active low) |
| ピン 23 | SDO — SPI Serial Data Out |
| ピン 24 | DVDD — Digital 3.3V Supply |
| ピン 25 | DGND — Digital Ground |
| ピン 26 | NC — Not connected |
| ピン 27 | NC — Not connected |
| ピン 28 | NC — Not connected |
| ピン 29 | NC — Not connected |
| ピン 30 | NC — Not connected |
| ピン 31 | NC — Not connected |
| ピン 32 | NC — Not connected |
| ピン 33 | NC — Not connected |
| ピン 34 | NC — Not connected |
| ピン 35 | NC — Not connected |
| ピン 36 | NC — Not connected |
| ピン 37 | NC — Not connected |
| ピン 38 | NC — Not connected |
| ピン 39 | NC — Not connected |
| ピン 40 | NC — Not connected |
| ピン 41 | NC — Not connected |
| ピン 42 | NC — Not connected |
| ピン 43 | NC — Not connected |
| ピン 44 | NC — Not connected |
| ピン 45 | NC — Not connected |
| ピン 46 | NC — Not connected |
| ピン 47 | NC — Not connected |
| ピン 48 | NC — Not connected |
| ピン 49 | NC — Not connected |
| ピン 50 | NC — Not connected |
| ピン 51 | NC — Not connected |
| ピン 52 | NC — Not connected |
| ピン 53 | NC — Not connected |
| ピン 54 | NC — Not connected |
| ピン 55 | NC — Not connected |
| ピン 56 | EP — Exposed Pad (thermal/ground) |
主な用途
ADC1613D105HN-C18 の用途: 6 件s: Multi-Carrier 3G/4G Base Station Receiver, Software-Defined Radio (SDR) Platform, Medical Ultrasound Beamforming, Radar and Lidar Digitizer Front-End, High-Speed Test and Measurement Instrumentation, Broadband Communications Test Equipment.
Multi-Carrier 3G/4G Base Station Receiver
The ADC1613D105HN-C18 is purpose-built for multi-carrier 3G/4G base-station receiver paths. Its dual 16-bit channels simultaneously sample I/Q baseband or IF signals at 105 MSPS, capturing multiple carrier bands with >75 dB SFDR. The JESD204A serial output streams data directly to a baseband FPGA (Xilinx Kintex or Altera Stratix) over 1-2 lanes - dramatically reducing PCB trace count vs parallel LVDS ADCs. The 1.8 V analog supply keeps power per channel around 200 mW, which is acceptable for densely populated multi-sector antenna systems. Designers should allocate at least 4-layer stackup with continuous ground beneath the ADC to preserve SNR.
おすすめ
Software-Defined Radio (SDR) Platform
For SDR platforms, the ADC1613D105HN-C18 digitizes wideband RF/IF signals directly into FPGAs for flexible demodulation. Dual channels enable true I/Q capture without calibration skew, and 105 MSPS supports ~50 MHz instantaneous bandwidth - sufficient for many narrowband waveforms (DVB-T, LTE fragments, GPS). The JESD204A interface simplifies the ADC-to-FPGA link, freeing board area for RF front-end components. The 16-bit resolution preserves dynamic range across the SDR's tuning range. Estimated: power dissipation ~400 mW per device at 105 MSPS with 1.8 V AVDD.
おすすめ
Medical Ultrasound Beamforming
In phased-array ultrasound systems, the ADC1613D105HN-C18 simultaneously samples 2 receive channels at 105 MSPS with 16-bit resolution, supporting beamforming across 64-128 element arrays. The pipelined architecture adds only a few clock cycles of latency, acceptable for real-time beam steering. The dual-channel integration reduces per-channel board area by ~40% vs discrete ADC pairs, and JESD204A output keeps the analog front-end-to-FPGA link manageable across dense channel-count designs. The exposed pad package enables the thermal performance needed for continuous clinical duty cycles.
おすすめ
Radar and Lidar Digitizer Front-End
The ADC1613D105HN-C18 digitizes intermediate-frequency signals from radar and lidar receivers where 105 MSPS and 16-bit resolution preserve the dynamic range needed to detect small targets in clutter. Dual channels support simultaneous capture of in-phase and quadrature returns from coherent radar front-ends, and the JESD204A interface streams to DSP/FPGA processors running CFAR detection and tracking algorithms. Industrial temperature range (-40C to +85C) is suitable for outdoor and vehicle-mounted installations.
おすすめ
High-Speed Test and Measurement Instrumentation
In oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers, the ADC1613D105HN-C18 captures repetitive and single-shot transients with 16-bit vertical resolution and 105 MSPS real-time sampling. Dual channels enable two simultaneous measurement paths (e.g., voltage and current probes, or stimulus and response). The JESD204A interface feeds data into an FPGA where FFTs and statistical analysis are performed. Pin-compatibility with the 125 MSPS ADC1613D125HN-C18 lets designers scale instrument bandwidth tiers from a single PCB layout.
おすすめ
Broadband Communications Test Equipment
Manufacturing test equipment for wireless infrastructure uses the ADC1613D105HN-C18 to digitize wideband signals during DUT verification. The 16-bit resolution captures modulation EVM accurately, and the dual-channel architecture supports vector signal analysis of I/Q modulated waveforms. JESD204A output keeps test-instrument PCB cost manageable even with multiple ADC channels per instrument. Renesas' proven long-term supply chain supports industrial test-equipment product lifecycles of 10+ years.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC1613D105HN-C18 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC1613D125HN-C18 | ADC1613D105HN-C1 | ADC1613D080HN-C18 | ADC1412D065HN-C1 | ADC14DS105AISQ/NOPB |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments |
| Package | 56-VFQFPN Exposed Pad (8x8 mm) | 56-VFQFPN Exposed Pad - same | 56-VFQFPN Exposed Pad - same | 56-VFQFPN Exposed Pad - same | 56-VFQFPN Exposed Pad - same | 60-WQFN - different |
| Resolution | 16 bits | 16 bits | 16 bits | 14 bits | 12 bits | 14 bits |
| Sample Rate (max) | 105 MSPS | 125 MSPS | 65 MSPS | 80 MSPS | 65 MSPS | 105 MSPS |
| Number of Channels | 2 | 2 | 1 | 2 | 1 | 2 |
| Data Interface | Serial JESD204A | Serial JESD204A | Serial JESD204A | Serial JESD204A | Parallel LVDS | |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主な差別化要因
- Dual simultaneously-sampling 16-bit channels in 56-VFQFPN （vs ADC1610S125HN-C1)
- JESD204A serial interface reduces pin count vs parallel LVDS ADCs （vs ADC14DS105AISQ/NOPB)
- Pin-compatible speed grade scalability across same package （vs ADC1613D125HN-C18 / ADC1613D105HN-C1)
- Industrial temperature range with proven long-term supply （vs Discrete ADC + external reference designs)
設計ノート
The ADC1613D105HN-C18 requires separate 1.8 V analog (AVDD) and 3.3 V digital (DVDD) supplies per the Renesas datasheet. Each AVDD pin must be decoupled with a 0.1 uF X7R ceramic capacitor placed within 2 mm of the pin, plus a 10 uF bulk capacitor per rail. Ferrite beads or pi-filters between the analog and digital supplies are recommended to prevent digital switching noise from coupling into the analog front-end and degrading SNR.
Estimated: at 105 MSPS with both channels active and 1.8 V AVDD, total power dissipation is approximately 400 mW. The 56-VFQFPN exposed pad has a typical theta_JA around 25 C/W on a standard JEDEC 4-layer test board. The PCB must provide a copper pour of at least 1 square inch directly beneath the exposed pad, with thermal vias (0.3 mm drill, 1 mm pitch) connecting to inner ground layers to keep junction temperature rise below 10 C above ambient.
Route the JESD204A CML serial outputs as 100 ohm differential pairs with continuous reference ground beneath, length-matched within 0.5 mm. Keep the analog input traces (AIN1P/N, AIN2P/N) symmetric to preserve differential balance - skew between differential pairs directly degrades SFDR. The CLK+ and CLK- input is also differential and must be length-matched; use a low-jitter clock driver (jitter below 300 fs RMS) to preserve ADC aperture performance.
A common mistake is configuring the JESD204A link parameters (L, M, F, K, N, S) inconsistently between the ADC and the receiving FPGA, which prevents link establishment. Always verify the configuration with a pattern checker or test mode before relying on live data. Another pitfall is failing to provide adequate input common-mode voltage - the VCM output pin must be decoupled and used to bias the input driver to maintain the ADC input common-mode in its specified range.
Place the analog input coupling capacitors (typically 10 nF to 100 nF ceramic) as close as possible to the AINxP/N pins. Keep the analog section (input traces, reference pins) physically separated from the digital section (JESD204A outputs, SPI, clock) on the PCB to minimize digital-to-analog coupling. Use a stitching via fence around the analog input section connected to the analog ground pour for additional isolation.
コンプライアンス情報
RoHS and REACH compliance per Renesas product page. Halogen-free status not explicitly stated in available data; check Renesas environmental compliance documentation for confirmation. Not AEC-Q100 qualified - not intended for automotive applications.
