ADS574JEG4 - 12-Bit 40kSPS SAR ADC, Parallel, 28-DIP | TI
部品番号: ADS574JEG4 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $23.5 | $23.50 |
| 10 | $21.2 | $212.00 |
| 100 | $18.9 | $1,890.00 |
| 500 | $16.75 | $8,375.00 |
| 1,000 | $14.6 | $14,600.00 |
ADS574JEG4 概要
An SAR ADC is a type of data converter that uses a binary-search algorithm implemented with a capacitive digital-to-analog converter (CDAC) and a single high-speed comparator, producing one conversion result per successive approximation cycle. The ADS574's CMOS CDAC architecture yields low power dissipation, deterministic latency, and excellent DC linearity (typical 0.0244% linearity error). Within the converter hierarchy, SAR ADCs sit between flash converters (fastest, lowest resolution) and sigma-delta ADCs (highest resolution, lower bandwidth), making them ideal for industrial process control, instrumentation, and data-acquisition systems where 12-bit accuracy and 40 kSPS throughput are sufficient.
Key features include ±5 V analog input range, 0.0244% linearity error, 25 µs maximum acquisition-plus-conversion time, and an operating temperature range of -40 °C to +85 °C. The integrated track-and-hold eliminates the need for an external sample-and-hold amplifier, while on-chip voltage reference and clock generation reduce the external bill of materials. The 8+4 parallel output bus is bus-interfaced for direct connection to 8-bit and 16-bit microprocessors without glue logic.
The ADS574's internal reference, capacitor-array CDAC, and CMOS control logic are designed for low-power continuous operation at 40 kSPS. The successive-approximation engine completes a 12-bit conversion in 12 clock cycles after acquisition, delivering deterministic latency for multiplexed input switching. The -40 °C to +85 °C industrial operating range allows deployment in factory-floor, automotive test, and laboratory instrumentation without derating.
Typical applications include industrial process control loops, multi-channel data-acquisition front ends, medical instrumentation front ends, weigh-scale and load-cell signal chains, and legacy microprocessor-based board upgrades. The DIP-28 package supports through-hole assembly, simplifying prototyping, repair, and educational lab use where sockets are preferred.
When designing with the ADS574, ensure the analog input is buffered and the digital supply is decoupled with a 0.1 µF ceramic cap close to the IC. The 25 µs conversion time means that throughput, not analog bandwidth, is the dominant speed constraint; for continuous streaming, a 40 kSPS rate applies. A higher-resolution successor (ADS7804, ADS8517) is recommended when 16-bit performance is required.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet. Compared to the OEM product page, the alternatives matrix and design_notes here consolidate the engineering trade-offs for a designer selecting a 12-bit, parallel-interface SAR ADC in a DIP package.
ドロップイン代替品: ADS574JEG4 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS574JEG4 （同一形状・フットプリント） — 相違点: Architecture, Mounting Type, RoHS Status, Operating Temperature, Package.
クイック比較ツール — 並列比較する代替部品を選択:
ADS574KP
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS574KE
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS574JE
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$16.95 / 個
データシートを見る →ADS574JP
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MAX174BCPI
✅ ドロップイン✓ 在庫あり
$14.2 / 個
データシートを見る →AD574AJN
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS574JEG4 最大定格＆電気的特性
| Number of Bits | 12 |
| Sampling Rate (Per Second) | 40 kSPS |
| Number of Inputs | 1 |
| Input Type | Single-Ended |
| Data Interface | Parallel |
| Architecture | SAR (Successive Approximation) |
| Configuration | S/H-ADC |
| パッケージ / ケース | 28-DIP (0.300 in, 7.62 mm) |
| 実装タイプ | Through-Hole |
| Packaging | Tube |
| 動作温度 | -40 °C to +85 °C |
| Nominal Supply Voltage (Digital) | 5 V |
| Nominal Negative Supply | -15 V (per partstack listing) |
| Linearity Error (typical) | 0.0244 % |
| Maximum Acquisition + Conversion Time | 25 µs |
| RoHS ステータス | Compliant |
ADS574JEG4 ピン構成
| ピン 1 | VCC (+5V) — +5 V digital supply |
| ピン 2 | DB11 — Data bit 11 (MSB) |
| ピン 3 | DB10 — Data bit 10 |
| ピン 4 | DB9 — Data bit 9 |
| ピン 5 | DB8 — Data bit 8 |
| ピン 6 | DB7 — Data bit 7 |
| ピン 7 | DB6 — Data bit 6 |
| ピン 8 | DB5 — Data bit 5 |
| ピン 9 | AGND — Analog ground |
| ピン 10 | VREF — Internal reference voltage (2.5 V) |
| ピン 11 | DGND — Digital ground |
| ピン 12 | DB4 — Data bit 4 |
| ピン 13 | DB3 — Data bit 3 |
| ピン 14 | VIN — Analog input |
| ピン 15 | DB2 — Data bit 2 |
| ピン 16 | DB1 — Data bit 1 |
| ピン 17 | DB0 — Data bit 0 (LSB) |
| ピン 18 | STS — Status output (conversion complete) |
| ピン 19 | R/C — Read/Convert input |
| ピン 20 | CE — Chip enable (active low) |
| ピン 21 | CS — Chip select (active low) |
| ピン 22 | A0 — Byte select (high byte / low byte / 12-bit) |
| ピン 23 | NC — Not connected (per datasheet) |
| ピン 24 | BIP OFF — Bipolar offset adjustment |
| ピン 25 | GAIN — Gain adjustment |
| ピン 26 | VEE (-15V) — -15 V analog supply |
| ピン 27 | NC — Not connected (per datasheet) |
| ピン 28 | NC — Not connected (per datasheet) |
主な用途
ADS574JEG4 の用途: 6 件s: Industrial Process Control Loop, Multi-Channel Data-Acquisition Front End, Medical Instrumentation Front End, Weigh-Scale and Load-Cell Signal Chain, Legacy Microprocessor Board Upgrade, Educational and Laboratory Prototyping.
Industrial Process Control Loop
The ADS574JEG4 fits industrial process-control loops with its 12-bit resolution (0.0244% linearity) and 40 kSPS throughput, which capture typical 4-20 mA loop signals after gain conditioning. The 28-DIP through-hole package simplifies retrofit and field-service replacement on legacy PLC and DCS boards. Designers place the ADC after a 4-20 mA-to-voltage conversion stage; the 25 µs conversion time supports 200 Hz loop bandwidth. Compared to modern sigma-delta ADCs, the SAR's deterministic latency avoids filter group delay, simplifying PID tuning. The -40 °C to +85 °C range covers factory-floor temperatures without derating.
おすすめ
Multi-Channel Data-Acquisition Front End
For multi-channel data-acquisition (DAQ) boards, the ADS574JEG4's parallel 8+4 output bus interfaces directly to 8-bit and 16-bit microprocessors without glue logic, simplifying FIFO design. The 40 kSPS throughput supports 4-8 multiplexed channels at 5-10 kSPS each, common in vibration and temperature monitoring. The 28-DIP package suits prototype boards and educational labs where socketed parts ease debugging. The internal reference and clock reduce external components, saving PCB area compared to earlier-generation ADCs. A common design uses an analog MUX (e.g., DG508) feeding the ADS574JEG4, with the host CPU sequencing channel selection.
おすすめ
Medical Instrumentation Front End
The ADS574JEG4 suits medical instrumentation such as patient monitors and benchtop analyzers where 12-bit resolution is sufficient for parameters like SpO2, respiration, and temperature. The 40 kSPS rate captures physiological bandwidths (typically <100 Hz) with substantial oversampling headroom for digital filtering. The CMOS CDAC architecture delivers low power, important for battery-powered portable monitors. The 28-DIP package supports through-hole assembly on medical-grade PCBs, simplifying test and rework. Designers add a low-pass anti-alias filter before the ADC input; the SAR's deterministic latency simplifies medical-algorithm timing budgets.
おすすめ
Weigh-Scale and Load-Cell Signal Chain
Weigh scales and load-cell signal chains benefit from the ADS574JEG4's 12-bit resolution and 0.0244% linearity, which yield 0.4 g resolution on a 1 kg scale after appropriate signal conditioning. The 40 kSPS rate supports fast settling time after load application, reducing measurement latency. The internal reference provides stable excitation, though designers typically add a precision external reference for highest-accuracy scales. The 28-DIP package is well-suited to compact scale electronics where socketed parts ease field service. Compared to sigma-delta ADCs, the SAR's lack of digital filter group delay is advantageous in fast weighing cycles.
おすすめ
Legacy Microprocessor Board Upgrade
The ADS574JEG4 is the modern CMOS replacement for the obsolete ADC574, fitting legacy 8085, 8051, and Z80 microprocessor boards where the original ADC574 was specified. The 8+4 parallel interface and 28-pin DIP package match the original footprint, enabling drop-in upgrade without PCB rework. Power consumption drops significantly (CMOS vs bipolar), extending battery life in portable instruments. The 25 µs conversion time matches legacy timing assumptions, preserving software compatibility. This makes the ADS574JEG4 ideal for end-of-life support of industrial control, scientific instruments, and military test equipment where redesign costs are prohibitive.
おすすめ
Educational and Laboratory Prototyping
The ADS574JEG4 is widely used in university EE labs and R&D prototyping because the 28-DIP through-hole package accepts IC sockets, enabling repeated insertion and replacement during student lab exercises. The integrated reference, clock, and sample-and-hold let students focus on SAR-algorithm theory rather than analog front-end design. The 12-bit resolution and 40 kSPS throughput provide measurable results on low-bandwidth signals (audio, temperature, light) with simple microcontroller readout via the parallel bus. The 25 µs conversion time is fast enough to demonstrate real-time sampling at audible frequencies, making it a teaching staple for digital signal processing courses.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS574JEG4 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS574KP | ADS574KE | ADS574JE | MAX174BCPI | AD574AJN |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Maxim Integrated | Analog Devices |
| Package | 28-DIP | 28-DIP - same | 28-DIP - same | 28-DIP - same | 28-DIP - same | 28-DIP - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Architecture | SAR (CMOS CDAC) | SAR (CMOS CDAC) | SAR (CMOS CDAC) | SAR (CMOS CDAC) | SAR | SAR (bipolar) |
| Data Interface | Parallel (8+4) | Parallel (8+4) | Parallel (8+4) | Parallel (8+4) | Parallel | Parallel (8+4) |
| Operating Temperature | -40 °C to +85 °C | 0 °C to +70 °C | -40 °C to +85 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C |
| Internal Reference | Yes (2.5 V) | Yes (2.5 V) | Yes (2.5 V) | Yes (2.5 V) | No (external required) | Yes (10 V) |
主な差別化要因
- Wide industrial temperature range in a DIP package （vs ADS574KP)
- Modern CMOS low-power replacement for legacy bipolar ADC574 （vs AD574AJN)
- Integrated reference and clock （vs MAX174BCPI)
設計ノート
Decouple the +5 V digital supply (pin 1) and the -15 V analog supply (pin 26) with 0.1 µF ceramic capacitors placed within 5 mm of the IC pins, plus a 10 µF tantalum bulk cap. The analog and digital grounds (AGND pin 9, DGND pin 11) should be connected at a single point under the IC, with a low-impedance ground pour to avoid digital switching noise coupling into the analog input. The 25 µs conversion time at 40 kSPS draws ~50 mW; no special thermal management is required for the DIP-28 package in still air.
Place the analog input trace (pin 14) over a continuous ground pour and away from digital outputs (pins 2-8, 12-13, 15-17) and digital control lines (CE, CS, R/C, A0) to minimize digital-to-analog crosstalk. Keep the analog input trace short (under 30 mm) and use a guard trace tied to AGND if high-impedance source. The reference pin (pin 10) connects to the internal 2.5 V reference; if an external reference is used, connect it to pin 10 with a 1 µF bypass capacitor. The BIP OFF and GAIN pins (24, 25) need 50 kΩ trim pots in series with 100 kΩ resistors to VREF and AGND for ±5 V input range calibration.
Do not connect the analog input (pin 14) directly to high-impedance sources without a buffer amplifier - the ADS574's input capacitance (~30 pF) and switched-capacitor input will load the source and cause gain errors. Use an op-amp buffer (e.g., OPA2277) with <1 mV offset and low noise. Do not exceed the absolute maximum analog input of ±15 V, or the input ESD cells may be damaged. When using the internal reference, avoid driving pin 10 with an external source; if external reference is required, decouple with 1 µF and bypass the internal reference. Ensure the host microprocessor waits for STS (status) low before reading the parallel data bus, or use the CE/R/C handshake for proper timing.
コンプライアンス情報
RoHS compliant per TrustCompo listing. Lead-free per DigiKey listing. Halogen-free status not explicitly stated in data - set to 'unknown'. AEC-Q100 not applicable for industrial-grade through-hole ADCs.
