ADS58C28IRGC25 - Dual 11-Bit 200MSPS ADC | Texas Instruments
部品番号: ADS58C28IRGC25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $36.5 | $36.50 |
| 10 | $32.85 | $328.50 |
| 100 | $28.9 | $2,890.00 |
| 500 | $25.4 | $12,700.00 |
| 1,000 | $22.1 | $22,100.00 |
ADS58C28IRGC25 概要
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous analog voltages into binary digital codes. High-speed pipeline ADCs such as the ADS58C28 use a switched-capacitor pipeline architecture, sampling the input on a track-and-hold stage and propagating the residue through successive low-resolution stages. In the system hierarchy the ADS58C28 sits as: pipeline ADC -> ADC -> data converter -> mixed-signal IC -> integrated circuit. It is a foundational building block for digitizing IF/RF signals in software-defined radio, base stations, and instrumentation.
Key specifications include 200 MSPS maximum sample rate, 83 dBc SFDR, 72.5 dBFS SNR with 60 MHz bandwidth using TI's third-generation SNRBoost3G technology, 1.8 V analog/digital supply, and CMOS-compatible LVDS outputs. The SNRBoost3G feature supports wide-bandwidth multi-carrier reception by allowing digital post-processing to remove in-band spurs, dramatically improving effective dynamic range in dense carrier environments.
Architecturally, the ADS58C28 uses a differential input buffer, a wide-bandwidth track-and-hold, a digital gain and offset correction loop, and dual parallel LVDS output buses. Per-channel digital decimation filters can be applied to relax anti-alias requirements and reduce out-of-band noise. The 64-pin VQFN package with exposed thermal pad enables compact PCB layouts suitable for mezzanine cards and densely populated base-station line cards.
Typical applications include wireless infrastructure receivers (multi-standard 2G/3G/4G/5G base stations), software-defined radio (SDR) and wideband IF sampling, test and measurement instrumentation, radar and EW signal acquisition, and medical imaging front-ends. The dual-channel integration halves the PCB footprint versus two discrete ADCs while preserving channel-to-channel matching.
A key design consideration is that the SNRBoost3G mode requires an external FPGA or DSP to perform digital spur cancellation. Designers must allocate LVDS output lanes (DDR) and provide matched-length PCB routing. The 1.8 V supply requires low-noise LDO regulators (e.g., TPS7A4701 family) for the analog AVDD rail to avoid coupling switching noise into the ADC.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the standalone manufacturer datasheet, providing engineering context beyond the factory datasheet alone.
ドロップイン代替品: ADS58C28IRGC25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS58C28IRGC25 （同一形状・フットプリント） — 相違点: Number of Channels, Resolution, Package, Architecture, Input Type.
クイック比較ツール — 並列比較する代替部品を選択:
ADS58C28IRGCT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS62P23IRGC25
✅ ドロップイン✓ 在庫あり
$18.85 / 個
データシートを見る →ADS62P22IRGC25
✅ ドロップイン✓ 在庫あり
$15.5 / 個
データシートを見る →ADS62P48IRGC25
✅ ドロップイン✓ 在庫あり
$49.2 / 個
データシートを見る →ADC14DS105AISQ/NOPB
✅ ドロップイン✓ 在庫あり
$25.11 / 個
データシートを見る →ADS58C28IRGC25 最大定格＆電気的特性
| 分解能 | 11 bit |
| Number of Channels | 2 |
| Architecture | Pipelined |
| Maximum Sample Rate | 200 MSPS |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V |
| Input Type | Differential |
| SFDR | 83 dBc |
| SNR (60 MHz BW, SNRBoost3G) | 72.5 dBFS |
| Output Interface | LVDS (DDR) |
| Technology | CMOS |
| パッケージ | VQFN-64 (RGC) 9x9 mm with exposed thermal pad |
| 動作温度 | -40 C to +85 C |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| ピン数 | 64 |
ADS58C28IRGC25 ピン構成
| ピン 1 | AVDD — Analog 1.8V supply |
| ピン 2 | AVDD — Analog 1.8V supply |
| ピン 3 | GND — Ground |
| ピン 4 | INP_A — Channel A positive differential input |
| ピン 5 | INN_A — Channel A negative differential input |
| ピン 6 | VCM_A — Channel A common-mode voltage |
| ピン 7 | GND — Ground |
| ピン 8 | AVDD — Analog 1.8V supply |
| ピン 9 | AVDD — Analog 1.8V supply |
| ピン 10 | GND — Ground |
| ピン 11 | INP_B — Channel B positive differential input |
| ピン 12 | INN_B — Channel B negative differential input |
| ピン 13 | VCM_B — Channel B common-mode voltage |
| ピン 14 | GND — Ground |
| ピン 15 | AVDD — Analog 1.8V supply |
| ピン 16 | CLKP — Differential clock input positive |
| ピン 17 | CLKN — Differential clock input negative |
| ピン 18 | GND — Ground |
| ピン 19 | AVDD — Analog 1.8V supply |
| ピン 20 | AVDD — Analog 1.8V supply |
| ピン 21 | SEN — Serial enable |
| ピン 22 | SDATA — Serial data input |
| ピン 23 | SCLK — Serial clock |
| ピン 24 | RESET — Hardware reset (active low) |
| ピン 25 | PDN — Power-down (active high) |
| ピン 26 | GND — Ground |
| ピン 27 | DRVDD — Digital output 1.8V supply |
| ピン 28 | DRVDD — Digital output 1.8V supply |
| ピン 29 | GND — Ground |
| ピン 30 | D0P_A — Channel A LVDS data output 0 positive |
| ピン 31 | D0N_A — Channel A LVDS data output 0 negative |
| ピン 32 | D1P_A — Channel A LVDS data output 1 positive |
| ピン 33 | D1N_A — Channel A LVDS data output 1 negative |
| ピン 34 | D2P_A — Channel A LVDS data output 2 positive |
| ピン 35 | D2N_A — Channel A LVDS data output 2 negative |
| ピン 36 | D3P_A — Channel A LVDS data output 3 positive |
| ピン 37 | D3N_A — Channel A LVDS data output 3 negative |
| ピン 38 | D4P_A — Channel A LVDS data output 4 positive |
| ピン 39 | D4N_A — Channel A LVDS data output 4 negative |
| ピン 40 | D5P_A — Channel A LVDS data output 5 positive |
| ピン 41 | D5N_A — Channel A LVDS data output 5 negative |
| ピン 42 | DRVDD — Digital output 1.8V supply |
| ピン 43 | DCLKOUTP — LVDS clock output positive |
| ピン 44 | DCLKOUTN — LVDS clock output negative |
| ピン 45 | GND — Ground |
| ピン 46 | D0P_B — Channel B LVDS data output 0 positive |
| ピン 47 | D0N_B — Channel B LVDS data output 0 negative |
| ピン 48 | D1P_B — Channel B LVDS data output 1 positive |
| ピン 49 | D1N_B — Channel B LVDS data output 1 negative |
| ピン 50 | D2P_B — Channel B LVDS data output 2 positive |
| ピン 51 | D2N_B — Channel B LVDS data output 2 negative |
| ピン 52 | D3P_B — Channel B LVDS data output 3 positive |
| ピン 53 | D3N_B — Channel B LVDS data output 3 negative |
| ピン 54 | D4P_B — Channel B LVDS data output 4 positive |
| ピン 55 | D4N_B — Channel B LVDS data output 4 negative |
| ピン 56 | D5P_B — Channel B LVDS data output 5 positive |
| ピン 57 | D5N_B — Channel B LVDS data output 6 negative |
| ピン 58 | DRVDD — Digital output 1.8V supply |
| ピン 59 | NC — Not connected |
| ピン 60 | NC — Not connected |
| ピン 61 | GND — Ground |
| ピン 62 | AVDD — Analog 1.8V supply |
| ピン 63 | GND — Ground |
| ピン 64 | EP — Exposed thermal pad - connect to ground |
主な用途
ADS58C28IRGC25 の用途: 6 件s: Wireless Base Station Receiver, Software Defined Radio (SDR), Test and Measurement Instrumentation, Radar and Electronic Warfare Signal Acquisition, Medical Imaging Front-End, Industrial Multi-Carrier Communications.
Wireless Base Station Receiver
The ADS58C28IRGC25's dual 200 MSPS sampling channels and 72.5 dBFS SNR over 60 MHz bandwidth make it well-matched to multi-carrier wireless base station IF receivers. Its SNRBoost3G digital spur cancellation feature allows receivers to handle dense carrier allocations in 4G LTE and 5G NR systems where adjacent channel blocker tolerance is critical. The LVDS DDR digital interface simplifies FPGA capture and clock-domain crossing. Compared to discrete single-channel ADC pairs, the ADS58C28 halves PCB footprint and improves channel-to-channel gain/phase matching for diversity and MIMO architectures.
おすすめ
Software Defined Radio (SDR)
In wideband SDR platforms the ADS58C28IRGC25 digitizes wide IF bandwidths up to 60 MHz per carrier at 200 MSPS, enabling reception of multiple simultaneous waveforms from a single antenna chain. The 83 dBc SFDR ensures that strong in-band signals do not mask weaker signals of interest, a key requirement for cognitive radio and spectrum-monitoring applications. The 1.8 V low-power operation extends battery life in portable SDR test gear and manpack radios. The dual-channel integration enables direct I/Q sampling at IF, eliminating analog quadrature mixers and reducing total system cost and complexity.
おすすめ
Test and Measurement Instrumentation
The ADS58C28IRGC25 is well-suited to digitizing oscilloscope, spectrum analyzer, and signal-analyzer input stages where 11-bit vertical resolution and 200 MSPS capture rate support characterization of signals up to 60 MHz bandwidth. The dual channel allows simultaneous sampling of two test channels for time-interleaved measurement. SNRBoost3G allows the analyzer to dynamically cancel internal spur sources, improving effective dynamic range by 5-10 dB. Compared to oscilloscope ASICs, the ADS58C28 provides a low-risk COTS path to instrumentation designs requiring IF-sampling architectures with predictable AC performance.
おすすめ
Radar and Electronic Warfare Signal Acquisition
The ADS58C28IRGC25's 83 dBc SFDR is essential for radar and EW receivers that must detect weak returns in the presence of strong jamming or clutter signals. The 200 MSPS sampling supports IF bandwidths typical of pulse-Doppler and SAR radar systems. The dual-channel integration enables simultaneous capture of sum and delta channels in monopulse radar antennas, simplifying beam steering and target tracking. SNRBoost3G can be used to notch out narrow-band jammer signals in software, improving effective SNR in contested RF environments without analog filtering.
おすすめ
Medical Imaging Front-End
In ultrasound and MRI receiver front-ends the ADS58C28IRGC25 provides low-noise digitization of received IF signals with 72.5 dBFS SNR, supporting the wide dynamic range needed to capture both strong specular reflections and weak scattered signals. The dual channel supports parallel receive paths for beamformed imaging arrays. The 1.8 V supply simplifies compliance with patient-safety leakage current budgets in medical equipment. Low power consumption (~480 mW per channel) enables dense channel-count probe designs with minimal heat dissipation.
おすすめ
Industrial Multi-Carrier Communications
Industrial wireless systems including private LTE, 5G NR campus networks, and broadband PMR benefit from the ADS58C28IRGC25's 200 MSPS dual-channel sampling and SNRBoost3G digital spur rejection. The wide 60 MHz IF bandwidth per carrier supports aggregated carrier reception in licensed and unlicensed spectrum. The -40 to +85 C industrial temperature range enables deployment in outdoor base stations, factory automation cells, and mining or oilfield sites. Compared to consumer-grade ADCs, the ADS58C28's robust ESD and latch-up immunity per TI datasheet testing simplifies qualification for industrial environments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS58C28IRGC25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS58C28IRGCT | ADS62P23IRGC25 | ADS62P22IRGC25 | ADS62P48IRGC25 | ADC14DS105AISQ/NOPB |
|---|---|---|---|---|---|---|
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 - same family |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 11 bit | 11 bit - same | 12 bit | 12 bit | 14 bit | 14 bit |
| Maximum Sample Rate | 200 MSPS | 200 MSPS - same | 125 MSPS | 65 MSPS | 210 MSPS | 105 MSPS |
| Number of Channels | 2 | 2 - same | 2 | 2 | 2 | 2 |
| Supply Voltage | 1.8 V | 1.8 V - same | 3.3 V | 3.3 V | 3.3 V | 1.8 V |
| Output Interface | LVDS DDR | LVDS DDR - same | LVDS | LVDS | LVDS | JESD204B |
| SFDR | 83 dBc | 83 dBc - same | 85 dBc | 85 dBc | 85 dBc | 85 dBc |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C - same | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
主な差別化要因
- SNRBoost3G digital spur cancellation （vs ADS62P23IRGC25)
- Higher sample rate per channel at 1.8 V （vs ADS62P22IRGC25)
- Dual-channel integration in compact VQFN-64 （vs ADS62P48IRGC25)
設計ノート
The ADS58C28IRGC25 requires low-noise regulation on AVDD and DRVDD. A switch-mode supply's ripple directly degrades SFDR; per the TI datasheet, use an LDO such as TPS7A4701 with at least 10 uF ceramic output capacitance. Place the LDO within 25 mm of the ADC supply pins and route separate power pours for analog and digital rails to prevent digital switching noise from coupling into the analog supply. Estimated: AVDD current draw at 200 MSPS is approximately 280 mA per channel, requiring an LDO rated at 1 A continuous.
LVDS DDR output traces must be impedance-controlled to 100 ohm differential with matched lengths within 0.5 mm. Per TI application notes, route the 12 LVDS data lanes + 1 clock pair on an inner stripline layer with continuous reference ground plane. Avoid routing LVDS signals across plane splits or noisy digital regions; this causes Common-Mode noise and degrades bit-error rate. AC-couple the LVDS outputs with 100 nF capacitors if the receiving FPGA uses CML or HSTL, otherwise DC-couple directly when FPGA supports LVDS.
The differential analog inputs (INP_A/INN_A, INP_B/INN_B) require 100 ohm differential routing and a common-mode capacitor to VCM pin. Per TI layout guidelines, keep analog input traces short and symmetric to minimize channel-to-channel skew. The exposed thermal pad (pin 64) must be soldered to a 5x5 mm minimum ground copper pour for thermal dissipation; ground stitching vias on 1 mm pitch connect the EP to the internal ground layer for both thermal and electrical reference.
Do not leave the SNRBoost3G mode disabled if multi-carrier spurs are present in the IF spectrum - the digital post-processing provides 5-10 dB of effective dynamic range improvement. Ensure the FPGA captures the 6-bit LVDS data per channel in DDR mode at the rising and falling edges of DCLKOUT. SPI configuration (SCLK/SDATA/SEN) must be initialized at power-up before any data is captured; failing to do so leaves the ADC in an undefined state.
コンプライアンス情報
RoHS compliant per TI product page. Industrial temperature range -40 to +85 C. Not AEC-Q100 qualified (this is an industrial/communications part).
