ADS61B23 - 12-Bit 80MSPS ADC, Buffered Inputs | TI
部品番号: ADS61B23 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $25.5 | $25.50 |
| 10 | $22.95 | $229.50 |
| 100 | $20.4 | $2,040.00 |
| 500 | $18.36 | $9,180.00 |
| 1,000 | $16.52 | $16,520.00 |
ADS61B23 概要
An ADC (analog-to-digital converter) is a data converter that converts continuous analog signals into discrete digital values, enabling digital processing of real-world signals. The ADS61B23 is a high-speed, low-power pipelined ADC within the broader data-converter hierarchy: data converters -> ADCs -> high-speed pipelined ADCs -> mixed-signal building blocks. Its buffered inputs isolate the sampling capacitor from the source, reducing kickback and easing front-end amplifier drive requirements.
Key features include 12-bit resolution, a maximum sampling rate of 80 MSPS, and a buffered differential input accepting a wide common-mode range. Dynamic performance is excellent: SNR of 69.5 dBFS and SFDR of 84 dBc at 70 MHz input frequency. The device includes an internal voltage reference, a programmable gain amplifier (PGA) option, and a flexible digital output interface with LVDS or CMOS options.
Architecturally, the ADS61B23 uses a pipelined core with digital error correction, achieving high throughput at approximately 380 mW power consumption. The buffered inputs reduce the need for external drive amplifiers and simplify the analog front-end. The device also features sleep and power-down modes and an internal reference buffer that provides a stable reference voltage without external components.
Typical applications include wireless base stations, software-defined radios, radar receivers, medical ultrasound, and high-speed data acquisition. Buffered inputs and high dynamic range suit direct IF sampling in communication receivers, digitizing intermediate-frequency signals with high fidelity.
When designing with the ADS61B23, decouple the analog and digital supplies properly and use a low-jitter sampling clock to achieve the specified SNR. Set the input common-mode voltage to the datasheet-recommended level to optimize AC performance.
ドロップイン代替品: ADS61B23 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
ADS61B23IRHBT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS6149IRHBT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS6129IRHBT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS6135IRHBT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS61B23 最大定格＆電気的特性
| 分解能 | 12 bit |
| Maximum Sampling Rate | 80 MSPS |
| Architecture | Pipelined |
| Number of Inputs | 1 (differential, buffered) |
| SNR | 69.5 dBFS at 70 MHz input |
| SFDR | 84 dBc at 70 MHz input |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 1.8 V |
| Power Consumption | 380 mW (typical) |
| Digital Output Interface | LVDS or CMOS |
| Reference Modes | Internal and external |
| PGA Option | Yes (programmable gain) |
| パッケージ | 32-VQFN (5x5 mm) RHB |
| 実装タイプ | Surface Mount |
| Control Interface | Serial (SCL/SDA) and parallel config pins |
ADS61B23 ピン構成
| ピン 1 | INP — Non-inverting buffered analog input |
| ピン 32 | INN — Inverting buffered analog input |
| ピン 10 | CLKP — Sampling clock, positive |
| ピン 11 | CLKN — Sampling clock, negative |
| ピン 24 | AVDD — 3.3V analog supply |
| ピン 15 | DRVDD — 1.8V digital output driver supply |
| ピン 17 | GND — Ground |
| ピン 27 | SCL — Serial interface clock |
| ピン 28 | SDA — Serial interface data |
| ピン 26 | RESET — Register reset (active low) |
| ピン 20 | OUTP/OUTN (LVDS bus) — 12-bit digital output data pair(s) |
| ピン 8 | CFG parallel pins — Power-up mode configuration pins |
主な用途
ADS61B23 の用途: 6 件s: Wireless Base Station Receivers, Software-Defined Radio, Medical Ultrasound, Radar Receivers, Test and Measurement Instrumentation, High-Speed Data Acquisition Systems.
Wireless Base Station Receivers
In wireless base station receive paths, the ADS61B23 digitizes downconverted or direct-IF signals with 12-bit resolution at up to 80 MSPS. Its 69.5 dBFS SNR and 84 dBc SFDR at 70 MHz preserve channel linearity for QAM modulation schemes, while buffered differential inputs tolerate front-end amplifier mismatch. LVDS outputs at 80 MSPS keep digital edge rates manageable across the FPGA interface, and 380 mW total power eases thermal budgeting in dense radio cards.
おすすめ
Software-Defined Radio
Software-defined radios benefit from the ADS61B23's direct IF sampling capability: the buffered input allows digitizing intermediate-frequency signals up to tens of MHz with high dynamic range, shifting filtering into the digital domain. Internal reference mode removes external reference components, and serial or parallel configuration pins let firmware select gain, output format, and power modes at boot. At 380 mW it fits portable and embedded SDR platforms where battery life and conduction cooling are constraints.
おすすめ
Medical Ultrasound
Medical ultrasound receive chains require high dynamic range to capture weak echo returns adjacent to transmit leakage. The ADS61B23's 84 dBc SFDR suppresses harmonic spurs that would otherwise mask low-amplitude tissue echoes, and its buffered input reduces sampling-kickback distortion of the time-gain-compensated signal. The 12-bit, 80-MSPS conversion supports 10-15 MHz probe bandwidths, while sleep and power-down modes reduce dissipation in continuous-wave Doppler modes.
おすすめ
Radar Receivers
Pulse-Doppler and short-range radar receivers use the ADS61B23 to digitize IF returns at up to 80 MSPS with consistent 69.5 dBFS noise floor, improving detection of small targets near strong clutter. Buffered inputs simplify matching to the mixer output across temperature, and the pipelined architecture guarantees fixed one-cycle latency critical for coherent processing. LVDS output format keeps electromagnetic emissions low in compact radar front-end modules.
おすすめ
Test and Measurement Instrumentation
Bench instruments, digitizer cards, and automated test equipment leverage the ADS61B23's flat AC performance and buffered input, which tolerates varying source impedances from relays, probes, and front-end attenuators. The PGA option adapts full-scale range to different input amplitudes, and CMOS output mode eases interfacing with legacy logic. The ADS61B23EVM evaluation board provides a proven reference design for characterizing custom signal-conditioning front ends.
おすすめ
High-Speed Data Acquisition Systems
Industrial and scientific data acquisition modules use the ADS61B23 to capture transient and periodic signals up to 80 MSPS with 12-bit accuracy. Internal reference mode plus power-down capability simplify multi-board designs, and the serial interface register map allows remote calibration of gain and offset. At 380 mW the converter can be passively cooled in conduction-cooled or sealed enclosures typical of field-deployed DAQ hardware.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS61B23 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS61B23IRHBT | ADS6149IRHBT | ADS6129IRHBT |
|---|---|---|---|---|
| Package | 32-VQFN (RHB) 5x5 mm | 32-VQFN (RHB) 5x5 mm - same | 32-VQFN (RHB) 5x5 mm - same | 32-VQFN (RHB) 5x5 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit |
| Maximum Sampling Rate | 80 MSPS | 80 MSPS | 250 MSPS | 250 MSPS |
| Input Type | Buffered differential | Buffered differential | Buffered differential | Unbuffered differential |
| Output Interface | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
主な差別化要因
- Buffered analog inputs reduce drive requirements （vs ADS6129IRHBT)
- Lowest power in the pin-compatible family at 80 MSPS （vs ADS6149IRHBT)
- Integrated internal reference eliminates reference pins （vs ADS61B23IRHBT (external-reference mode))
設計ノート
Sampling-clock jitter directly limits SNR: for 69.5 dBFS-class performance at 70 MHz input, keep total clock aperture jitter below approximately 200 fs rms. Use a dedicated low-noise synthesizer (e.g., LMX2572LP family) and route the clock as a 100-ohm differential pair away from LVDS output lines. According to TI datasheet guidance, jitter-dominated SNR equals -20*log10(2*pi*fin*tjitter).
Provide separate 3.3V analog and 1.8V output-driver supplies with star grounding to the exposed pad. Decouple each AVDD and DRVDD pin with 0.1 uF ceramics placed within 2 mm, plus 10 uF bulk per rail. Avoid sharing the DRVDD rail with other high-switching-load logic; CMOS output mode at high sample rates injects significant switching current compared to LVDS.
Solder the 32-VQFN exposed pad to a grounded thermal via array (typically 3x3, 0.3 mm vias) - it is the primary ground return and heat path. Keep the analog input traces (INP/INN) as a matched 100-ohm differential pair, short and shielded by ground. Keep configuration pins (parallel mode straps) away from clock and LVDS routing to prevent power-up state corruption.
Set the input common-mode voltage to the datasheet-recommended level (typically mid-supply via the internal buffer bias); an incorrect common-mode degrades SFDR by several dB. Also verify LVDS termination: each LVDS pair needs a 100-ohm differential termination at the receiver, and floating unterminated pairs cause bit errors that mimic ADC noise problems.
コンプライアンス情報
Compliance data was not present in the provided verified web data; consult the TI.com product page environmental section for RoHS/REACH certificates.
