BSG0813NDIATMA1 - 25V 19A/33A OptiMOS 5 Power Block | Infineon
部品番号: BSG0813NDIATMA1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $1.85 | $1.85 |
| 10 | $1.66 | $16.60 |
| 100 | $1.48 | $148.00 |
| 500 | $1.32 | $660.00 |
| 1,000 | $1.18 | $1,180.00 |
| 3,000 | $1.05 | $3,150.00 |
BSG0813NDIATMA1 概要
A Power Block is a multi-chip semiconductor module that integrates two MOSFETs (typically one high-side and one low-side switch) plus an optional gate-driver or bootstrap circuitry into a single package. The architecture belongs to the broader hierarchy of power management ICs and discrete MOSFET modules, specifically the synchronous buck converter building block used in voltage regulator modules (VRMs) and point-of-load (POL) converters. By co-packaging the high-side and low-side switches, the Power Block minimizes the high-current switching loop, which directly reduces switching losses and voltage overshoot.
Key features include very low on-state resistance for high-efficiency synchronous rectification, integrated gate drivers optimized for the internal FET pair, a 25 V drain-source voltage rating suitable for 12 V bus systems, and a 5.0 x 6.0 mm PG-TISON-8 footprint that is footprint-compatible with the industry-standard DrMOS area. The leadless package also provides superior thermal performance compared to traditional SO-8 or TSSOP-8 discrete pairs, allowing higher continuous current without external heatsinking.
The OptiMOS 5 technology generation provides an optimized figure of merit (RDS(on) x Qg) for high-frequency buck topologies. The internal low-side FET is optimized for low RDS(on) to minimize conduction loss, while the high-side FET is balanced for both low gate charge and low RDS(on) to manage switching loss and thermal rise at high duty cycles. Together these optimize the synchronous buck regulator efficiency curve across the typical 10-90% load range.
Typical applications include voltage regulator modules for servers and datacenters, telecom base-station POL converters, industrial 24V-bus buck regulators, USB-PD and Type-C laptop adapters, and graphics-card core VRs. The integrated Power Block format reduces the bill of materials and PCB real-estate required versus a discrete half-bridge plus gate-driver approach.
When designing with this part, verify that the maximum drain current of the high-side FET (33 A) is sufficient for the worst-case peak current of the buck converter under load-transient conditions. Designers should also confirm that the bootstrap capacitor and bootstrap diode external component values match the application note's recommended network, and that the exposed pad is soldered to a sufficiently large copper pour to stay within the 2.5 W package dissipation limit.
This page synthesizes distributor pricing tiers, drop-in Power Block alternatives, and practical design notes not found in the manufacturer datasheet, enabling faster BOM selection and second-source validation.
ドロップイン代替品: BSG0813NDIATMA1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: BSG0813NDIATMA1 （同一形状・フットプリント） — 相違点: Package, Drain-Source Voltage (VDS), MSL Level, Operating Temperature Range, Technology.
クイック比較ツール — 並列比較する代替部品を選択:
BSG0811NDIATMA1
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
BSG0815NDIATMA1
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
BSZ0901NSIATMA1
✅ ドロップイン✓ 在庫あり
$0.34 / 個
データシートを見る →BSC050N04LSGATMA1
✅ ドロップイン✓ 在庫あり
$0.41 / 個
データシートを見る →BSC019N04LSTATMA1
✅ ドロップイン✓ 在庫あり
$1.21 / 個
データシートを見る →BSG0813NDIATMA1 最大定格＆電気的特性
| Manufacturer | Infineon Technologies |
| Series | OptiMOS 5 Power Block |
| FET Type | N-Channel MOSFET Array (half-bridge / synchronous buck) |
| Configuration | High-side + Low-side, integrated |
| Drain-Source Voltage (VDS) | 25 V |
| Low-Side Continuous Drain Current (ID) | 19 A |
| High-Side Continuous Drain Current (ID) | 33 A |
| Power Dissipation (PD) | 2.5 W |
| パッケージ | PG-TISON-8 (5.0 x 6.0 mm) |
| 実装タイプ | Surface Mount |
| Technology Generation | OptiMOS 5 |
| RoHS ステータス | Compliant |
| MSLレベル | 1 (per JEDEC J-STD-020) |
| トポロジー | Synchronous buck half-bridge |
BSG0813NDIATMA1 ピン構成
| ピン 1 | HSG — High-side gate (drive input) |
| ピン 2 | HSD — High-side drain (power input) |
| ピン 3 | BOOT — Bootstrap supply for high-side driver |
| ピン 4 | SW — Switch node (phase output) |
| ピン 5 | LSD — Low-side drain (connected to SW internally) |
| ピン 6 | LSS — Low-side source (power ground) |
| ピン 7 | LSG — Low-side gate (drive input) |
| ピン 8 | PGND — Power ground / thermal pad |
安全動作領域 (High-Side FET)
主な用途
BSG0813NDIATMA1 の用途: 6 件s: Server CPU/GPU Voltage Regulator Module (VRM), Telecom and Datacom Point-of-Load (POL) Converter, Industrial 24V-Bus Buck Regulator, USB-PD and Laptop Adapter Buck Stage, Graphics Card and GPU Core VR, Automotive Infotainment and ADAS Power Rails.
Server CPU/GPU Voltage Regulator Module (VRM)
The BSG0813NDIATMA1 fits server and high-end desktop VRMs as the synchronous buck half-bridge for 12 V to 0.8-1.8 V core conversion. Its 25 V VDS rating gives ample margin on a 12 V bus, the 33 A high-side / 19 A low-side continuous ratings cover typical single-phase VRM currents up to ~15 A, and the PG-TISON-8 Power Block minimizes switching-loop inductance versus a discrete pair. Designers typically switch at 500 kHz to 1 MHz; efficiency in this topology benefits directly from the low Rds(on) x Qg figure of merit of OptiMOS 5 silicon, reducing both conduction and switching loss in multi-phase VRMs.
おすすめ
Telecom and Datacom Point-of-Load (POL) Converter
In telecom base-station and Ethernet-switch POL converters, the BSG0813NDIATMA1 serves as the half-bridge switch pair for stepping a 12 V or 24 V intermediate bus down to 3.3 V, 2.5 V, or 1.8 V rails. The integrated Power Block footprint reduces PCB area versus a discrete FET pair plus driver, which is critical in dense line-card layouts. The 25 V VDS accommodates 24 V industrial bus transients, and the 2.5 W package dissipation allows continuous operation at moderate load currents without external heatsinking.
おすすめ
Industrial 24V-Bus Buck Regulator
The BSG0813NDIATMA1 is well matched to industrial 24 V nominal input buck regulators powering sensors, motor-control logic, and PLC I/O subsystems. Its 25 V VDS limits the safe input to roughly 20 V continuous, but when paired with an upstream TVS or input filter the part handles 24 V industrial bus transients within margin. The PG-TISON-8 Power Block simplifies the bill of materials versus a discrete half-bridge, while the exposed pad layout supports sufficient copper area to keep junction temperature rise within industrial -40 to +125 C ratings under typical 3-5 A loads.
おすすめ
USB-PD and Laptop Adapter Buck Stage
In USB Power Delivery adapters and laptop Type-C charger designs, the BSG0813NDIATMA1 forms the primary-side or secondary-side synchronous buck half-bridge for stepping 19-20 V down to 5 V, 9 V, or 20 V Type-C PD rails. The Power Block's 33 A peak high-side current handles PD 100 W peak loads, while the 25 V VDS comfortably tolerates the rectified 19 V adapter bus. The compact 5.0 x 6.0 mm PG-TISON-8 footprint reduces the charger PCB size, and the integrated half-bridge reduces EMI compared to discrete layouts at the typical 200-400 kHz switching frequency used in PD adapters.
おすすめ
Graphics Card and GPU Core VR
The BSG0813NDIATMA1 fits discrete GPU and graphics-card core voltage regulators, where the synchronous buck half-bridge steps a 12 V rail down to a 0.8-1.2 V GPU core voltage at high transient currents. The Power Block's low switching-loop inductance is essential at the multi-MHz switching frequencies used in modern GPU VRs to minimize voltage overshoot and ringing. The 33 A high-side rating supports single-phase VRs up to about 25 A peak, with multi-phase designs paralleling two or more Power Blocks for higher current GPUs.
おすすめ
Automotive Infotainment and ADAS Power Rails
Although the BSG0813NDIATMA1 is not explicitly AEC-Q100 qualified in the provided data, the part fits as a buck half-bridge in non-safety automotive subsystems such as infotainment head units, ADAS sensor power, and body-electronic modules where the input bus is regulated 12 V. For ADAS safety-critical rails requiring AEC-Q100 grade, designers should select an AEC-Q100 qualified Infineon OptiMOS part instead. The PG-TISON-8 footprint simplifies migration to the automotive-qualified variant without PCB rework.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: BSG0813NDIATMA1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | BSG0811NDIATMA1 | BSG0815NDIATMA1 | BSZ0901NSIATMA1 | BSC050N04LSGATMA1 | BSC019N04LSTATMA1 |
|---|---|---|---|---|---|---|
| Brand | Infineon | Infineon | Infineon | Infineon | Infineon | Infineon |
| Package | PG-TISON-8 (5.0 x 6.0 mm) | PG-TISON-8 (5.0 x 6.0 mm) - same | PG-TISON-8 (5.0 x 6.0 mm) - same | PG-TISON-8 (5.0 x 6.0 mm) - same | PG-TISON-8 (5.0 x 6.0 mm) - same | PG-TISON-8 (5.0 x 6.0 mm) - same |
| Topology | Synchronous buck half-bridge (HS + LS MOSFET) | Synchronous buck half-bridge | Synchronous buck half-bridge | Synchronous buck half-bridge | Synchronous buck half-bridge | Synchronous buck half-bridge |
| Drain-Source Voltage (VDS) | 25 V | 25 V | 25 V | 30 V | 40 V | 40 V |
| Technology Generation | OptiMOS 5 | OptiMOS 5 | OptiMOS 5 | OptiMOS | OptiMOS | OptiMOS |
| RoHS Status | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
主な差別化要因
- OptiMOS 5 silicon for best-in-class figure of merit （vs BSC050N04LSGATMA1)
- 25 V VDS optimized for 12 V bus applications （vs BSC019N04LSTATMA1)
- Power Block integration reduces BOM count and switching loop （vs Discrete high-side + low-side SO-8 pair)
設計ノート
Estimated: at continuous 19 A low-side load with 2.5 W package dissipation, the PG-TISON-8 thermal pad requires at least 1 square inch of 2 oz copper on a 4-layer FR-4 PCB to stay within the OptiMOS 5 thermal derating curve. For multi-phase VRMs paralleling two or more Power Blocks, double the copper area per phase. Without adequate copper, junction temperature can exceed 125 C and trigger thermal shutdown. Refer to Infineon application note AN_2013_PL11_1_0 for PG-TISON-8 thermal layout.
Place the BSG0813NDIATMA1 high-frequency loop capacitors (input ceramic + boot cap) directly adjacent to the HSD and BOOT pins to minimize the high-current switching loop. Keep the SW node copper area compact to reduce radiated EMI. The exposed thermal pad must be soldered to a continuous ground plane with thermal vias (8-12 vias of 0.3 mm diameter) to achieve the rated 2.5 W dissipation.
Do not exceed 25 V VDS across the input bus including transient spikes. Add a TVS diode rated at 24 V standoff on the input if the upstream source can produce ringing above 25 V during load transients. Also confirm that the bootstrap capacitor value matches the application note recommendation (typically 0.1 uF to 1 uF X7R) - an undersized boot cap causes high-side gate drive droop and Rds(on) increase at high duty cycles.
Route the gate-drive signals (HSG, LSG) as 50-ohm microstrip traces from the external gate driver to the Power Block gate pins, keeping them short and away from the SW node to avoid noise coupling. The SW node copper area should be minimized and surrounded by a ground copper pour to act as a faraday shield, reducing radiated EMI in compliance with FCC Part 15 / EN 55022 Class B for computing and telecom end products.
コンプライアンス情報
RoHS compliant per Infineon product page. Not AEC-Q100 qualified in the provided data; for automotive safety-critical rails, select an AEC-Q100 qualified Infineon OptiMOS part instead. MSL-1 per JEDEC J-STD-020 means no dry-pack required prior to reflow soldering.
