EP1S20B672C6 - Stratix FPGA 18,460 LEs 672-BGA | Intel / Altera
MPN: EP1S20B672C6 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $742.27 | $742.27 |
| 10 | $668.04 | $6,680.40 |
| 100 | $594.5 | $59,450.00 |
| 500 | $535 | $267,500.00 |
| 1,000 | $489.5 | $489,500.00 |
Drop-in alternatives for EP1S20B672C6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1S20B672C7N
✅ Drop-In✓ In Stock
$320 / Unit
View Datasheet →EP1S20B672C5N
✅ Drop-In📋 Reference alternative (not in catalog)
EP1S20F672C6
✅ Drop-In✓ In Stock
$470 / Unit
View Datasheet →EP1S20B672I6
✅ Drop-In📋 Reference alternative (not in catalog)
EP1S20B672C7
✅ Drop-In📋 Reference alternative (not in catalog)
EP1S20B672C6 Maximum Ratings & Electrical Characteristics
| Family | Stratix |
| Manufacturer | Intel (formerly Altera) |
| Logic Elements | 18,460 |
| Embedded Memory Bits | 1,669,248 |
| User I/O Count | 426 |
| Package | 672-ball FineLine BGA (672-BBGA) |
| Package Dimensions | 35 mm x 35 mm |
| Ball Pitch | 1.27 mm |
| Process Technology | 130 nm CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Speed Grade | C6 |
| Operating Temperature | 0 C to 85 C (commercial) |
| Maximum Internal Frequency | 450.05 MHz |
| Logic Family | CMOS |
| Configuration Method | PS / PPS / PPA / JTAG |
EP1S20B672C6 35 mm x 35 mm Pin Configuration Guide
Complete pinout information for EP1S20B672C6 (35 mm x 35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1S20B672C6.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1S20B672C6 is suitable for 6 applications: High-Speed Data Acquisition Systems, Telecommunications Baseband Processing, Video Broadcast and Image Processing, ASIC Prototyping and Emulation, Military and Aerospace Signal Processing, Industrial Control and Factory Automation.
High-Speed Data Acquisition Systems
The EP1S20B672C6 fits multi-channel data acquisition front-ends because its 18,460 logic elements and embedded DSP blocks deliver parallel sample processing at high sample rates. The 426 user I/O pins support wide LVDS or LVTTL parallel buses that connect directly to multi-channel ADCs without external bus multiplexers, while TriMatrix embedded memory (1,669,248 bits) buffers incoming sample bursts before DSP downconversion. The 450.05 MHz internal clock rate enables real-time FIR filtering and decimation chains in a single device, replacing multi-ASIC solutions and shortening FPGA design cycles. Use the device between the ADC bank and a host processor or DMA engine to offload channelization, FFT, and threshold detection work, reducing host CPU load.
Recommended
Telecommunications Baseband Processing
In telecom baseband designs, the EP1S20B672C6 maps efficiently to channel cards that require parallel symbol-rate processing, scrambling, and FEC encoding. Its DSP blocks accelerate Viterbi, Turbo, and Reed-Solomon decoder kernels used in 3G/4G modem subsystems, while 426 user I/O pins connect to standard OBSAI/CPRI framer interfaces and backplane SERDES links. The 1.5 V core supply and C6 speed grade meet commercial telecom card thermal envelopes, and Quartus II synthesis supports existing telecom IP cores. Use it where deterministic per-symbol latency is critical and where DSP block count is the gating resource.
Recommended
Video Broadcast and Image Processing
The EP1S20B672C6 is well suited to SD/HD video processing pipelines, where its 18,460 logic elements implement de-interlacers, scalers, color-space converters, and overlay compositors in a single device. Embedded TriMatrix memory holds multiple video frame buffers or line stores without external SRAM, and the 426 I/O pins interface to BT.656, BT.1120, DVI, or HDMI bridges. Its DSP blocks accelerate 2D convolution kernels for image filtering and edge detection. Place it between the video decoder ASIC and the display controller to handle real-time processing at 148.5 MHz pixel clock for HD-SDI workflows.
Recommended
ASIC Prototyping and Emulation
For ASIC prototyping, the EP1S20B672C6 hosts partitioned RTL of mid-complexity ASICs, allowing software teams to develop firmware before tape-out. Its 18,460 logic elements represent roughly 1-2 million gates of synthesized logic, sufficient for many networking or storage controller ASICs, while 1,669,248 bits of embedded memory model large register files and FIFOs. The 672-ball BGA exposes 426 I/O pins to map almost any ASIC pinout via a prototyping PCB. Use multiple EP1S20B672C6 devices in a multi-FPGA partitioning flow to scale capacity up to full ASIC complexity.
Recommended
Military and Aerospace Signal Processing
Stratix devices in the same family and package, including industrial-temperature grades, are used in military and aerospace signal processing applications where mature silicon and long-term configuration bitstream stability matter. The EP1S20B672C6 forms the processing heart of radar front-ends, electronic warfare subsystems, and avionics data buses; its DSP blocks implement pulse compression, MTI filtering, and beamforming kernels, and its 426 I/O pins connect to high-speed ADC and DAC converters. Use the I-grade variant for deployed military platforms, but validate the EP1S20B672C6 commercial grade in lab and development environments.
Recommended
Industrial Control and Factory Automation
In factory automation systems, the EP1S20B672C6 implements high-speed motion controllers, multi-axis servo loops, and protocol bridges (EtherCAT, PROFINET, EtherNet/IP). Its DSP blocks execute PID loops and state-space controllers at microsecond cycle times, while 426 I/O pins handle encoder feedback, limit switches, and discrete I/O expansion. The TriMatrix embedded memory captures motion profile trajectories without external memory access. Industrial users benefit from the long-life silicon revisions of mature Stratix devices that have been qualified across thousands of deployed machine builders.
Recommended
Recommended Products Summary
Engineering reference data for EP1S20B672C6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1S20B672C7N | EP1S20B672C5N | EP1S20F672C6 | EP1S20B672I6 | EP1S20B672C7 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 672-ball FineLine BGA (35x35mm, 1.27mm pitch) | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same |
| Logic Elements | 18,460 | 18,460 | 18,460 | 18,460 | 18,460 | 18,460 |
| Embedded Memory Bits | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 |
| User I/O Count | 426 | 426 | 426 | 426 | 426 | 426 |
| Speed Grade | C6 | C7 (faster) | C5 (slower) | F6 (faster family) | I6 (industrial temp) | C7 (faster) |
| Operating Temperature | 0 C to 85 C (commercial) | 0 C to 85 C (commercial) | 0 C to 85 C (commercial) | 0 C to 85 C (commercial) | -40 C to 100 C (industrial) | 0 C to 85 C (commercial) |
| Core Voltage (VCCINT) | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
Key Differentiators
- High logic density in a 130 nm mature-process FPGA (vs EP1S10F672C7 (10k LE variant))
- C6 speed grade balances performance and yield (vs EP1S20B672C7N)
- Commercial temperature range with Stratix silicon maturity (vs EP1S20B672I6)
Design Notes
Estimated: Stratix EP1S20 family devices require multi-rail power sequencing - VCCINT (1.5 V core) must reach 1.0 V before VCCIO banks are energized, and VCCIO must not exceed VCCINT + 0.3 V at any time to avoid latch-up. Use a dedicated FPGA power sequencer IC and add a 1 ms to 10 ms delay between VCCINT and VCCIO ramps. Decoupling: place 100 nF X7R ceramics on every VCCINT/VCCIO pin pair within 5 mm trace length, plus bulk 330 uF tantalum or polymer capacitors at the regulator outputs. Without proper sequencing, inrush current on VCCIO can forward-bias internal ESD structures.
Estimated: at 100% logic utilization with sustained 200 MHz clock activity, an EP1S20 can dissipate 5 W to 8 W. The 672-ball FineLine BGA has theta_JA around 12 C/W with a standard 4-layer JEDEC test board, giving a junction-to-ambient rise of 60 C to 100 C above ambient. For enclosed chassis designs, attach a heatsink with thermal interface material and force 200 LFM to 400 LFM airflow across the BGA. Industrial-temperature variants have a 100 C junction limit; commercial C6 parts must keep Tj below 85 C for proper operation.
Use a minimum 8-layer PCB stack-up with continuous GND and VCCINT planes directly under the BGA. BGA breakout: 1.27 mm pitch requires 0.2 mm (8 mil) trace width with 0.2 mm spaces through the BGA fanout area; via-in-pad (0.25 mm microvias) is recommended for inner-row signal escapes. Match LVDS pair lengths within 0.5 mm (20 mil) and route each pair on a 100 ohm differential impedance. Keep high-speed SERDES-grade signals (GXB, if used) on the top two layers with adjacent GND reference.
Stratix configuration bitstreams are NOT compatible with Stratix II, III, or later families - do not attempt to load a Cyclone or newer bitstream onto the EP1S20. Always regenerate programming files in Quartus II 13.0 SP1 or earlier; newer Quartus Prime releases removed legacy Stratix support. JTAG chain order matters: place JTAG-configured devices with TDI-to-TDO in the correct sequence or use a boundary-scan chain re-order. Finally, do not assume all 426 user I/O pins are simultaneously usable - bank VCCIO selection constrains which I/O standards are simultaneously supported.
Compliance Information
Compliance data was not present in the verified web data; RoHS/REACH/lead-free status for the EP1S20B672C6 is marked unknown. AEC-Q100 is not applicable because this is an FPGA, not an automotive-grade discrete or analog IC.
