EP1S20F672C6N - Stratix FPGA 18,460 LE 672-BGA | Intel
MPN: EP1S20F672C6N β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $87.5 | $875.00 |
| 100 | $78.2 | $7,820.00 |
| 250 | $72.4 | $18,100.00 |
| 500 | $68.9 | $34,450.00 |
Drop-in alternatives for EP1S20F672C6N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1S20F672C6
β Drop-Inβ In Stock
$470 / Unit
View Datasheet βEP1S20B672C6
β Drop-Inβ In Stock
$489.5 / Unit
View Datasheet βEP1S20B672C6N
β Drop-Inβ In Stock
$425 / Unit
View Datasheet βEP1S20B672C7N
β Drop-Inβ In Stock
$320 / Unit
View Datasheet βEP2S20F672C5N
β Drop-Inπ Reference alternative (not in catalog)
EP1S20F672C6N Maximum Ratings & Electrical Characteristics
| Family | Stratix |
| Logic Elements | 18,460 |
| Total RAM Bits | 1,669,248 |
| User I/O Count | 426 |
| Package | 672-BBGA (FineLine BGA) 35 x 35 mm |
| Package Pitch | 1.27 mm |
| Core Voltage | 1.5 V |
| Logic Family | CMOS |
| Operating Temperature | 0 C to 85 C (commercial) |
| Speed Grade | -6 |
| Configuration Mode | PS, FPP, JTAG |
| Embedded DSP Blocks | Yes (36 x 36-bit multipliers) |
| TriMatrix Memory | M512, M4K, M-RAM blocks |
| PLLs | 12 (4 enhanced) |
| Global Clock Networks | 16 |
| Mounting Type | Surface Mount |
| Lead Free | Yes |
| RoHS Status | Compliant |
EP1S20F672C6N Pin Configuration
| Pin A1 | I/O β User I/O (bank 8) |
| Pin A2 | I/O β User I/O (bank 8) |
| Pin B1 | VCCIO β I/O bank voltage supply |
| Pin B2 | GND β Ground |
| Pin C1 | I/O β User I/O (bank 1) |
| Pin C2 | I/O β User I/O (bank 1) |
| Pin D1 | VCCINT β Core 1.5 V supply |
| Pin D2 | I/O β User I/O (bank 2) |
| Pin E1 | I/O β User I/O (bank 2) |
| Pin E2 | GND β Ground |
| Pin F1 | I/O β User I/O (bank 3) |
| Pin F2 | I/O β User I/O (bank 3) |
| Pin G1 | VCCIO β I/O bank voltage supply |
| Pin G2 | I/O β User I/O (bank 4) |
| Pin H1 | I/O β User I/O (bank 4) |
| Pin H2 | GND β Ground |
| Pin J1 | I/O β User I/O (bank 5) |
| Pin J2 | I/O β User I/O (bank 5) |
| Pin K1 | VCCIO β I/O bank voltage supply |
| Pin K2 | I/O β User I/O (bank 6) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1S20F672C6N is suitable for 8 applications: Telecom Line-Card Glue Logic, Military and Aerospace Signal Processing, Medical Imaging Pre-Processing, Test and Measurement Instrumentation, Industrial Motor Control DSP, Broadcast Video Processing, Storage Area Network Controllers, High-Performance Datapath Prototyping.
Telecom Line-Card Glue Logic
The EP1S20F672C6N's 18,460 logic elements, 426 user I/O, and TriMatrix memory totalling 1.6 Mbit make it well-suited for telecom line-card glue logic. The 16 global clock networks and 12 PLLs (including 4 enhanced PLLs) provide the deterministic clocking required for Utopia, POS-PHY, and RapidIO source-synchronous interfaces. The 1.5 V core voltage and 0-85 C commercial rating fit inside central-office chassis with controlled cooling, while the True-LVDS transceivers deliver 840 Mbps per pair for backplane serial links.
Recommended
Military and Aerospace Signal Processing
The EP1S20F672C6N's embedded DSP blocks perform 36 x 36-bit multiplication at full speed, accelerating channelisation, FFT, and beamforming kernels in radar and electronic-warfare signal processing. Its TriMatrix memory hierarchy supports wide deep buffers for I/Q sample storage, and the 672-ball BGA exposes enough I/O to drive multiple ADC/DAC channels in parallel. Aerospace integrators favour the Stratix family for its deterministic latency and the AES bitstream encryption option, which protects mission firmware.
Recommended
Medical Imaging Pre-Processing
The EP1S20F672C6N is used as a front-end pre-processing stage in medical imaging equipment, where its DSP blocks compute image filters, windowing, and histogram equalisation in real time. The 1.6 Mbit TriMatrix RAM buffers raw sensor frames before handoff to a host processor, and the 426 user I/O accommodate 12-bit to 16-bit parallel image-data buses from CMOS sensors. The 672-BGA package supports the multi-layer board stack-ups required for mixed-signal analogue front-end and digital image pipeline integration.
Recommended
Test and Measurement Instrumentation
The EP1S20F672C6N is well matched to logic analysers, protocol exercisers, and high-end oscilloscope capture back-ends, where its 16 global clocks, True-LVDS performance, and 426 I/O enable multi-channel synchronous sampling at hundreds of megahertz. The TriMatrix RAM provides deep capture buffers before on-board compression, and the AES bitstream option protects proprietary calibration IP. Its 35 x 35 mm BGA is compatible with high-density instrumentation motherboards using 4- to 8-layer controlled-impedance stack-ups.
Recommended
Industrial Motor Control DSP
Industrial servo drives use the EP1S20F672C6N to compute field-oriented control loops, SVPWM, and encoder interfaces with deterministic sub-microsecond latency. Its 12 PLLs generate the multi-rate clocks needed for resolver excitation, ADC sampling, and PWM generation, while the DSP blocks accelerate Clarke/Park transforms. The commercial 0-85 C rating fits inside sealed IP65 enclosures with heatsinking; for harsher factory floors, an I-suffix industrial variant is preferred.
Recommended
Broadcast Video Processing
The EP1S20F672C6N's True-LVDS performance and 426 I/O make it ideal for broadcast routing switchers, SDI/HD-SDI cross-points, and uncompressed video processing, where multi-channel parallel pixel pipelines demand deterministic timing. The TriMatrix RAM provides line and frame buffers for de-interlacing and scaling, while the AES-encrypted bitstream protects broadcaster compliance firmware. Pairing the EP1S20 with an EPC2 configuration device ensures glitch-free bitstream reloads in always-on broadcast racks.
Recommended
Storage Area Network Controllers
The EP1S20F672C6N's 1.6 Mbit TriMatrix memory supports Fibre Channel and SAS expander functions in storage arrays, where it acts as a glue layer between PHYs and the storage processor. The DSP blocks accelerate Reed-Solomon and CRC engines in real time, while the 12 PLLs derive multiple independent line-rate clocks for 1.5 Gbps and 3 Gbps PHYs. Its commercial 0-85 C rating fits inside storage shelves with controlled airflow.
Recommended
High-Performance Datapath Prototyping
The EP1S20F672C6N serves as an ASIC prototyping vehicle for datapath-rich designs in network processors and storage controllers. With 18,460 LEs and 1.6 Mbit embedded RAM, it can emulate early-stage ASIC RTL before mask commit, while the Quartus II synthesis flow preserves timing annotations that map cleanly to Stratix-based ASIC prototyping flows. The 672-BGA package provides sufficient I/O to attach 32-bit to 64-bit protocol exercisers and trace analysers during validation.
Recommended
Recommended Products Summary
Engineering reference data for EP1S20F672C6N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1S20F672C6 | EP1S20B672C6 | EP1S20B672C6N | EP1S20B672C7N | EP2S20F672C5N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-BBGA (F672) | 672-BBGA (F672) - same | 672-BBGA (F672) - same | 672-BBGA (F672) - same | 672-BBGA (F672) - same | 672-BBGA (F672) - same |
| Logic Elements | 18,460 | 18,460 | 18,460 | 18,460 | 18,460 | 18,460 |
| Total RAM Bits | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 | 1,069,248 |
| Speed Grade | -6 | -6 | -6 | -6 | -7 | -5 |
| Operating Temperature | 0 to 85 C (commercial) | 0 to 85 C | 0 to 85 C | 0 to 85 C | 0 to 85 C | 0 to 85 C |
| Lead Free | Yes (N suffix) | No (no N suffix) | No | Yes | Yes | Yes |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Mature |
| Qty-1 Price (USD, approx) | 95.00 | 88.00 | 75.00 | 78.00 | 72.00 | 110.00 |
Key Differentiators
- Largest TriMatrix memory in the 672-BGA EP1S20 family (vs EP2S20F672C5N)
- True-LVDS performance and 426 I/O at commercial temperature (vs EP1K50FC484-3)
- Lead-free N suffix compliant with RoHS for global deployment (vs EP1S20F672C6)
Design Notes
The 672-ball FineLine BGA with 1.27 mm pitch demands at least 4 PCB layers with dedicated power and ground planes. Use 0.5 oz copper outer layers and 1 oz inner layers; the FineLine BGA escape requires laser-drilled microvias or 4-mil via-in-pad if breakout under the device is needed. Controlled impedance of 50 ohm single-ended and 100 ohm differential must be verified with a 3D field solver for LVD S and clock traces.
Estimated: at 100 MHz operation with 70 percent logic utilisation and 1.5 V core, the EP1S20 draws roughly 1.2-1.8 A from VCCINT; budget at least 2.5 A headroom. Use a low-noise LDO such as the TPS7A4701 followed by a switching regulator for the bulk rail. Decouple every VCCIO bank with 0.1 uF and 10 uF ceramic caps placed within 5 mm of the BGA balls.
Configuration mode pin (MSEL) strapping must be set correctly: pull MSEL[2:0] high or low per the Stratix handbook to select PS, FPP, or JTAG mode - leaving them floating causes intermittent configuration failure. Decoupling on VCCPD (1.5 V pre-driver supply) is often missed and leads to JTAG boundary-scan errors. Always include an EPC2 or EPC4 configuration device for production boards rather than relying on a microcontroller bitstream download.
Estimated: the 672-ball BGA has theta_JA of approximately 8 C/W with a 4-layer JEDEC test board and 100 lfm airflow. At 2 W total dissipation, junction temperature rises only 16 C above ambient, well within the 85 C commercial limit. For sealed enclosures, derate by adding 0.5 C/W per lost lfm and consider a copper heat-spreader lid or thermal interface material to the chassis.
Route each LVDS pair length-matched within 5 mil (0.13 mm) to preserve 840 Mbps True-LVDS performance. Clock PLL inputs (CLK[0:15]) must be guarded by ground vias to prevent coupling from neighbouring I/O; use the Quartus II pin planner to assign CLK pins to the dedicated PLL clock input balls. DCM-to-PLL routing should avoid crossing noisy I/O banks.
Compliance Information
Lead-free N suffix confirms RoHS-compliant ball finish. Halogen-free status not specifically published; assume unknown pending datasheet confirmation. AEC-Q100 not applicable to commercial-grade FPGA.
