EP1S20B672C6N - Stratix FPGA, 18460 LEs, 672-BGA | Intel
MPN: EP1S20B672C6N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $636.13 | $636.13 |
| 10 | $595 | $5,950.00 |
| 50 | $540 | $27,000.00 |
| 100 | $488 | $48,800.00 |
| 500 | $425 | $212,500.00 |
Drop-in alternatives for EP1S20B672C6N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1S20B672C6
✅ Drop-In✓ In Stock
$489.5 / Unit
View Datasheet →EP1S20B672C6N
✅ Drop-In✓ In Stock
$425 / Unit
View Datasheet →EP1S20B672C6N Maximum Ratings & Electrical Characteristics
| Family | Stratix |
| Series | EP1S20 |
| Logic Elements (LE) | 18,460 |
| Logic Array Blocks (LAB) | 1,846 |
| Embedded Memory | 1,669,248 bits |
| Maximum User I/O | 426 |
| Process Technology | 130 nm CMOS |
| Core Voltage | 1.5 V |
| Package | 672-ball BGA (672-BBGA), 35 x 35 mm, 1.27 mm pitch |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 C to +85 C (Commercial) |
| Speed Grade | 6 |
| Configuration Method | Passive Serial / Fast Passive Parallel / JTAG |
| RoHS Status | Compliant |
| Lifecycle Status | Not Recommended for New Designs (NRND) |
EP1S20B672C6N 672-ball bga (672-bbga), 35 x 35 mm, 1.27 mm pitch Pin Configuration Guide
Complete pinout information for EP1S20B672C6N (672-ball bga (672-bbga), 35 x 35 mm, 1.27 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1S20B672C6N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1S20B672C6N is suitable for 6 applications: Telecommunications Line Cards, High-Speed Digital Signal Processing, ASIC Prototyping, Network Switches and Routers, Video and Image Processing, Test and Measurement Instrumentation.
Telecommunications Line Cards
The EP1S20B672C6N fits telecom line-card designs because its 18,460 logic elements and 1,669,248 bits of embedded TriMatrix memory provide headroom for channelized protocol processing, framing, and traffic shaping on a single chip. The 426 user I/Os in the 672-BGA package accommodate multiple SGMII / LVDS links to line-side SERDES and to the backplane. With dedicated DSP blocks, the EP1S20B672C6N can also implement echo cancellation and equalization stages directly in fabric, eliminating an external DSP chip. Quartus II design tools and pre-vetted IP cores shorten development time for SONET/SDH and Ethernet-based platforms.
Recommended
High-Speed Digital Signal Processing
The EP1S20B672C6N targets high-speed DSP applications through its embedded DSP blocks that perform multiply-accumulate at hundreds of MHz, paired with 1,669,248 bits of on-chip memory to hold coefficients and intermediate data. This combination enables FIR filters, FFT engines, and adaptive equalizers at multi-MSPS rates without external memory. The 672-BGA package provides 426 I/Os to interface to high-speed ADCs and DACs, while 1.5 V core and configurable I/O banks ease integration with mixed-voltage signal chains. Altera's DSP Builder and IP library for Stratix shorten algorithm-to-bitstream development.
Recommended
ASIC Prototyping
The EP1S20B672C6N is a strong ASIC prototyping vehicle because its 18,460 logic elements and 1,846 LABs are large enough to map moderate-complexity ASICs while preserving accurate timing. The TriMatrix memory blocks (512, 4K, and 512K sizes) match the wide range of on-chip RAM blocks typical in modern ASICs. With 426 user I/Os in the 672-BGA package, the device can drive the full I/O complement of an ASIC during in-circuit validation. Quartus II's TimeQuest timing analyzer and partition-based incremental compile let prototype teams iterate quickly on multi-million-gate designs.
Recommended
Network Switches and Routers
The EP1S20B672C6N suits network switch and router designs because it integrates 18,460 logic elements, large TriMatrix memory, and 426 I/Os in a single 672-BGA package. Designers can implement packet classification, lookup engines, and queuing logic in the logic fabric while using the on-chip M-RAM blocks for packet buffers and statistics counters. The device's PLL resources support multiple clock domains required by NPU and PHY interfaces, and Quartus II provides IP for TCAM, hash, and QoS engines. Compared with discrete ASSPs, the EP1S20B672C6N gives OEM switching platforms a flexible feature roadmap.
Recommended
Video and Image Processing
The EP1S20B672C6N is well suited to video and image processing pipelines because its DSP blocks accelerate motion estimation, color-space conversion, and scaling algorithms, while the TriMatrix memory holds full frames or scan-line buffers without external SRAM. The 426 user I/Os of the 672-BGA package support multiple parallel video buses (BT.1120, Camera Link, LVDS) and DDR memory interfaces for frame storage. With a 1.5 V core and configurable I/O banks, the EP1S20B672C6N integrates directly with HD video ADCs and HDMI / DVI transmitters. Quartus II's Video and Image Processing Suite provides ready-to-use IP for deinterlacing, scaling, and overlay.
Recommended
Test and Measurement Instrumentation
The EP1S20B672C6N serves high-end test and measurement equipment because its logic density and embedded DSP allow real-time waveform generation, protocol decoding, and statistical analysis on a single device. TriMatrix memory buffers deep acquisition records, and 426 I/Os in the 672-BGA package support high-speed ADC and DAC interfaces (LVDS, DDR2). The 1.5 V core plus configurable I/O bank voltages ease integration with mixed-signal front-ends. Designers use Quartus II's SignalTap II logic analyzer to debug internal nodes in real time, an advantage over fixed-architecture ASICs.
Recommended
Recommended Products Summary
Engineering reference data for EP1S20B672C6N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1S20B672C6 | EP1S20B672C6N |
|---|---|---|---|
| Package | 672-BBGA (35 x 35 mm, 1.27 mm pitch) | 672-BBGA - same | 672-BBGA - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Family / Series | Stratix / EP1S20 | Stratix / EP1S20 | Stratix / EP1S20 |
| Logic Elements (LE) | 18,460 | 18,460 | 18,460 |
| Embedded Memory | 1,669,248 bits | 1,669,248 bits | 1,669,248 bits |
| User I/O | 426 | 426 | 426 |
| Speed Grade | 6 | 6 | 6 |
| Operating Temperature | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) |
| Core Voltage | 1.5 V | 1.5 V | 1.5 V |
| Terminal Finish | Lead-free (NiPdAu) | Tin-Lead (SnPb) | Lead-free (NiPdAu) |
Key Differentiators
- Higher logic density than ACEX EP1K and lower-cost Stratix EP1S10 (vs EP1K100FC484-3)
- Lead-free terminal finish (vs EP1S20B672C6)
- True drop-in compatibility with same-density Stratix speed grades (vs EP1S10B672C6N)
Design Notes
Estimated: The 672-BGA package at full 18,460-LE utilization with high toggle rates can dissipate 5-8 W. With a typical 1 oz 4-layer PCB and 0.5 m/s airflow, theta_JA is around 12-15 C/W, giving a junction temperature rise of 60-120 C above ambient. For continuous operation in commercial-temperature environments, provide a minimum 25 x 25 mm copper land area on the top layer and an array of 0.3 mm thermal vias under the die to keep Tj below 125 C. Use a heatsink or heat-spreader lid for designs sustained above 70 C ambient.
The 672-BGA package uses 1.27 mm pitch and requires NSMD (non-solder-mask-defined) pads per IPC-7351 to ensure reliable BGA joint formation. Use ENIG (Electroless Nickel Immersion Gold) surface finish for lead-free assembly. For high-speed I/O such as LVDS or DDR interfaces, target 50-ohm single-ended and 100-ohm differential controlled-impedance traces, with length matching within 50 mil for differential pairs. Reference the Altera Stratix 672-BGA pinout file and AN-315 ('Guidelines for Designing High-Speed FPGA PCBs') for stackup recommendations.
Do not confuse the EP1S20B672C6N with the EP1S10B672C6N - both share the 672-BGA package but the EP1S10 has only 10,570 LEs and 920,448 bits of memory. The BGA ball map is not guaranteed identical between the two density grades; substituting one for the other requires verifying each ball against the Stratix pinout file. Also note that newer Quartus Prime (14.0 and later) drops support for the EP1S20 family; legacy Quartus II 13.0sp1 is the last version that synthesizes this device. Plan tool version and licensing carefully for new design starts.
Compliance Information
RoHS compliant per 'N' suffix designation (lead-free NiPdAu finish). NRND (Not Recommended for New Designs) by Intel. Not AEC-Q100 qualified - this is a commercial-grade FPGA. For new automotive designs, choose a Cyclone IV/V Auto or MAX 10 device.
