EP2S15F672C5 - Stratix II FPGA, 15.6K LEs, 672-BGA | Intel
部品番号: EP2S15F672C5 ⚠ ラストタイムバイ| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265 | $2,650.00 |
| 100 | $240 | $24,000.00 |
| 500 | $218 | $109,000.00 |
| 1,000 | $199 | $199,000.00 |
EP2S15F672C5 概要
What is an FPGA? A Field Programmable Gate Array is a programmable logic device that contains an array of configurable logic blocks (CLBs), programmable interconnect, and dedicated hard IP such as block RAM, DSP blocks, and transceivers. FPGAs occupy the position of programmable ASICs in the digital design hierarchy: below fixed-function ASICs in cost-per-unit but above microcontrollers in raw parallel processing capability. The Stratix II family specifically introduced adaptive logic modules (ALMs) that improve logic utilization versus prior Stratix generations, and built-in transceivers and TriMatrix memory make the family suitable for signal-processing and data-path intensive systems.
Key features of the EP2S15F672C5 include 15,600 logic elements organized into ALMs, 419,328 bits of embedded memory, embedded DSP blocks for fixed- and floating-point math, dedicated clock management PLL resources, and 366 user I/O pins supporting multiple I/O standards including LVDS, LVTTL, LVCMOS, SSTL, and HSTL. The FPGA also supports configuration via passive serial, fast passive parallel, and JTAG modes.
Typical applications include high-speed packet processing, telecom framer/mapper ASIC prototyping, DSP co-processing for radar and software defined radio, video processing pipelines, and ASIC prototyping for mid-complexity SoCs. The 672-BGA package supports moderate-density pin-count routing and is compatible with mainstream PCB fabrication tolerances.
When designing with the EP2S15F672C5, plan power sequencing for VCCINT, VCCIO banks, and auxiliary supplies carefully. Use IBIS models for signal-integrity simulation on LVDS links. The -5 speed grade timing margins should be validated against your slowest logic path with the Quartus Prime TimeQuest analyzer before tape-out.
This page synthesizes distributor pricing, drop-in equivalents within the Stratix II family, and design guidance not collated in any single manufacturer document. Cross-reference data, AEC-Q100 automotive options, and packaging details are sourced from DigiKey, Mouser, and Intel/Altera legacy datasheets.
ドロップイン代替品: EP2S15F672C5 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP2S15F672C5 （同一形状・フットプリント） — 相違点: Package, Speed Grade, Operating Temperature, Configuration Method, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
EP2S15F672C4N
✅ ドロップイン✓ 在庫あり
$195 / 個
データシートを見る →EP2S15F672C4
✅ ドロップイン✓ 在庫あり
$235 / 個
データシートを見る →EP2S15F672C3N
✅ ドロップイン✓ 在庫あり
$142.75 / 個
データシートを見る →EP2S15F672C3
✅ ドロップイン✓ 在庫あり
$142.3 / 個
データシートを見る →EP2S15F672C5 最大定格＆電気的特性
| Family | Stratix II |
| Series | EP2S15 |
| Logic Elements | 15,600 |
| CLBs | 6,240 |
| Memory Bits | 419,328 |
| Maximum User I/O | 366 |
| Operating Frequency (max) | 640 MHz |
| Speed Grade | -5 (mid-tier) |
| Package Type | 672-ball FineLine BGA (FBGA) |
| Package Dimensions | 27 mm x 27 mm |
| Ball Pitch | 1 mm |
| Process Technology | 90 nm CMOS |
| 動作温度 | Commercial (0C to +85C) |
| Configuration Method | Passive Serial / Fast Passive Parallel / JTAG |
| RoHS ステータス | Compliant (legacy lead-free version exists) |
| 実装タイプ | Surface Mount |
EP2S15F672C5 27 mm x 27 mm ピン配置ガイド
EP2S15F672C5 (27 mm x 27 mm パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP2S15F672C5.
詳細は データシート をご参照ください。
主な用途
EP2S15F672C5 の用途: 7 件s: Telecom Line Card Packet Processing, DSP Co-Processing for Software Defined Radio, ASIC Prototyping for Mid-Complexity SoCs, Video Processing Pipeline, Industrial Motor Control, Test and Measurement Instrumentation, Aerospace Avionics Databus Bridge.
Telecom Line Card Packet Processing
The EP2S15F672C5 fits telecom line-card designs that need 15.6K logic elements and 419 Kb of block RAM for header parsing, lookup-table caching, and queue management. With 366 user I/Os and HSTL/SSTL I/O support, the FPGA interfaces cleanly to network processors, SERDES, and external TCAM devices. The -5 speed grade supports typical 200-300 MHz fabric operation, sufficient for 10G Ethernet MAC classification at line rate. Designers typically instantiate soft 10G MAC IP, packet classifier, and traffic-shaping blocks within ALMs, reserving DSP blocks for hashing and CRC acceleration.
おすすめ
DSP Co-Processing for Software Defined Radio
The EP2S15F672C5 supports SDR baseband processing where 15.6K LEs and dedicated DSP blocks deliver FIR filters, FFT butterflies, and channel equalization at sample rates up to ~150 MSPS. Embedded block RAM stores twiddle-factor tables and intermediate sample buffers. The -5 grade timing margin allows one DSP block per ALM pairing at 250 MHz, enabling real-time LTE physical-layer downlink decode. The 672-FBGA package provides ample I/O for parallel ADC/DAC interfaces and Aurora or LVDS links to the host baseband processor.
おすすめ
ASIC Prototyping for Mid-Complexity SoCs
The EP2S15F672C5 is widely used as an ASIC prototyping vehicle because its ALM architecture maps cleanly to ASIC standard-cell libraries and its 366 I/Os support the full SoC pin-out for mid-complexity designs. Engineers partition the target ASIC into multiple Stratix II FPGAs using TDM or pin-multiplexing. The -5 speed grade models ASIC timing margins of approximately 200 MHz, sufficient for CPU subsystem validation. Quartus II TimeQuest correlates back to ASIC SDFs with high accuracy.
おすすめ
Video Processing Pipeline
The EP2S15F672C5 fits HD video processing where 15.6K LEs implement scaling, de-interlacing, and color-space conversion pipelines. Block RAM buffers full HD frames at 148.5 MHz pixel clock. Embedded DSP blocks accelerate 2D filters and motion-estimation kernels. The 672-FBGA exposes enough LVDS pairs to drive dual-channel DVI/HDMI TMDS links, plus DDR2 SDRAM interfaces for frame-store memory. Industrial video inspection, broadcast encoders, and medical imaging systems all use this density.
おすすめ
Industrial Motor Control
The EP2S15F672C5 supports industrial servo and motor-control applications where its ALMs implement field-oriented control (FOC), space-vector PWM, and current-loop compensators. With 366 I/Os, the FPGA drives multiple PWM channels, quadrature encoder inputs, and isolated gate-driver interfaces. The 672-FBGA package suits industrial temperature ranges when system-level airflow keeps the die within commercial spec. Latency-critical control loops run at 50-100 kHz with sub-microsecond determinism.
おすすめ
Test and Measurement Instrumentation
The EP2S15F672C5 enables high-end test instrumentation including logic analyzers, protocol exercisers, and BERT pattern generators. Its 15.6K LEs implement stimulus generation and response capture pipelines; embedded block RAM stores long PRBS patterns. The 366 I/Os support multi-channel LVDS acquisition at sample rates up to 1 GSPS when paired with external ADCs. The -5 speed grade timing margin supports deterministic protocol timing for USB 3.0, PCIe Gen1, and SATA I link training emulators.
おすすめ
Aerospace Avionics Databus Bridge
The EP2S15F672C5 is used in avionics line-replaceable units to bridge legacy ARINC 429/1553 databuses with modern Ethernet or Fibre Channel fabrics. Its ALMs implement protocol engines, error counters, and health-monitoring telemetry. 366 user I/Os support multiple redundant MIL-STD-1553 channels plus Ethernet MAC interfaces. The commercial temperature grade requires thermal management in pressurized avionics bays. Note: this part is not formally DO-254 certifiable; aerospace programs typically use the -I industrial-grade equivalent and apply DAL-C/D process documentation.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP2S15F672C5 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP2S15F672C4N | EP2S15F672C4 | EP2S15F672C3N | EP2S15F672C3 |
|---|---|---|---|---|---|
| Brand | Intel (Altera legacy) | Intel | Intel | Intel | Intel |
| Package | 672-ball FBGA (27x27mm, 1mm pitch) | 672-ball FBGA (27x27mm, 1mm pitch) - same | 672-ball FBGA (27x27mm, 1mm pitch) - same | 672-ball FBGA (27x27mm, 1mm pitch) - same | 672-ball FBGA (27x27mm, 1mm pitch) - same |
| Speed Grade | -5 (mid-tier) | -4 | -4 | -3 (faster) | -3 (faster) |
| Logic Elements | 15,600 | 15,600 | 15,600 | 15,600 | 15,600 |
| Memory Bits | 419,328 | 419,328 | 419,328 | 419,328 | 419,328 |
| User I/O | 366 | 366 | 366 | 366 | 366 |
| Solder Ball / Lead-Free | Leaded ball (legacy) | Lead-free (N suffix) | Leaded ball | Lead-free (N suffix) | Leaded ball |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
| Max Fmax (typical path) | ~450 MHz (mid-grade) | ~400 MHz | ~400 MHz | ~550 MHz | ~550 MHz |
主な差別化要因
- Mid-tier -5 speed grade balances Fmax and price （vs EP2S15F672C3 (speed grade -3))
- Leaded solder balls retain legacy assembly compatibility （vs EP2S15F672C4N (N suffix = lead-free))
- 672-FBGA exposes 366 user I/Os for high-pin-count interfaces （vs Smaller-package Stratix II variants (F484, F780))
設計ノート
Stratix II EP2S15 devices require multiple supply rails: VCCINT (core, typically 1.2V), VCCIO (per bank, 1.5V/1.8V/2.5V/3.3V), VCCPD (I/O pre-driver), VCCPGM (configuration), and VCCA_PLL/VCCD_PLL (analog PLL). Use a sequenced power architecture with monotonic ramp-up; failure to sequence may cause long-term reliability degradation or in-rush latch-up. Decouple each rail with 0.1 uF X7R per 4-6 balls plus bulk 100-330 uF polymer.
The EP2S15F672C5 in FBGA672 has typical theta_JA around 13-15 C/W with 4-layer JEDEC PCB and 1.5 m/s airflow. At full utilization (100% toggle rate across 15K LEs + active DSP + memory), die power can reach 5-8W; plan a thermal pad or heatsink. Use Quartus II PowerPlay early estimation to budget per-design power before PCB commitment.
Layout the FBGA672 with 1.0 mm pitch using 0.5 mm via-in-pad or dog-bone micro-via fanout on a 4- or 6-layer stack-up. Match-impedance traces (50 ohm SE / 100 ohm diff) for LVDS pairs and DDR memory interfaces. Reference the Altera AN 575: High-Speed Board Layout Guidelines for Stratix II; route all clocks on inner stripline layers with length-matched, guard-banded traces.
Do not reuse configuration files across Stratix II speed grades without recompiling - bitstream includes speed-bin-specific PROM data. Ensure JTAG chain order matches schematic; nCONFIG, nSTATUS, and CONF_DONE must have 4.7 kohm pull-ups to VCCPGM. Verify MSL3 floor-life handling per JEDEC J-STD-033 because FBGA packages absorb moisture rapidly.
Run Quartus TimeQuest timing analysis with the -5 speed-grade SDC file and verify all paths meet setup/hold across PVT corners. For LVDS outputs, place 100 ohm differential termination within 7 mm of the receiver. Use IBIS models for board-level SI simulation on multi-MHz parallel buses interfacing the FPGA.
コンプライアンス情報
EP2S15F672C5 is the leaded ball (non-N) variant - the leaded SnPb balls make it explicitly non-RoHS, but the -N suffix variants (C4N, C3N) are RoHS-compliant with lead-free SAC balls. The part is commercial grade, not AEC-Q100 qualified; choose industrial -I variants for harsh environment. Last-time-buy lifecycle per Intel PCN.