EPC144ICC20 - Altera 440kb Config EPROM, 20-Pin TSSOP | Intel FPGA
部品番号: EPC144ICC20 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.6 | $4,300.00 |
| 1,000 | $7.45 | $7,450.00 |
EPC144ICC20 概要
A configuration EPROM is a non-volatile memory device that stores the FPGA's SRAM-based configuration bitstream. Because SRAM-based FPGAs (such as the Altera FLEX 10K, APEX 20K, and ACEX 1K families) lose their configuration when power is removed, an external boot memory is required to reload the device on every power-up. The EPC144ICC20 belongs to the EPC1/EPC2/EPC1441 family of configuration PROMs that interface to the FPGA through Altera's proprietary serial or parallel configuration bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE). It also includes an optional JTAG port for in-system programming and verification.
Key features include 440,800 bits of storage (organized as a serial bitstream with built-in bit-stuffing CRC), 3.3V or 5.0V single-supply operation, cascadable support for multi-FPGAs or larger bitstreams, and compatibility with Altera Quartus II programmer software. The TSSOP-20 package reduces board space compared to the older DIP-20 ceramic-windowed package while maintaining a small-footprint, surface-mount assembly flow.
The EPC144ICC20 is a one-time-programmable variant in the EPC1441 family (the ICC20 suffix indicates the industrial-temperature ceramic or TSSOP package). It is pin-compatible with the older EPC1441LC20 and EPC1441LI20 in the 20-pin SOIC/TSSOP family, and is electrically compatible with the 3.3V logic levels used by the APEX 20K and ACEX 1K families.
Typical applications include loading FLEX 10K, APEX 20K, and ACEX 1K FPGA bitstreams, multi-FPGA configuration in cascaded chains, factory-programmed configuration for volume production, and embedded prototypes using legacy Altera CPLD/FPGA silicon. Designers should select this part when the target FPGA is older Altera silicon and the design can accept a one-time-programmable configuration store.
When designing with this device, pay attention to the nCS, OE, and DCLK timing relative to the FPGA's configuration controller, and provide a clean 3.3V rail with a 0.1 uF decoupling capacitor near the VCC pin. The JTAG chain must include the EPC144ICC20 between TDI and TDO of the FPGA so that in-system programming works correctly.
This page synthesizes distributor availability, drop-in pin-compatible alternatives, and practical design notes that are not consolidated in any single manufacturer datasheet.
ドロップイン代替品: EPC144ICC20 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPC144ICC20 （同一形状・フットプリント） — 相違点: Memory Type, Package, Operating Temperature, Programming Method, Supply Voltage.
クイック比較ツール — 並列比較する代替部品を選択:
EPC1441LI20
✅ ドロップイン✓ 在庫あり
$8.1 / 個
データシートを見る →EPC1441LI20N
✅ ドロップイン✓ 在庫あり
$4.29 / 個
データシートを見る →EPC1441LC20
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPC1441LC20N
✅ ドロップイン✓ 在庫あり
$7.95 / 個
データシートを見る →EPC1213LI20
✅ ドロップイン✓ 在庫あり
$9.75 / 個
データシートを見る →EPC144ICC20 最大定格＆電気的特性
| メモリタイプ | Configuration EPROM (UV-erasable, OTP variant) |
| メモリサイズ | 440,800 bits |
| Usable Configuration Bits | 433,008 bits |
| Configuration Interface | Altera serial / JTAG configuration bus |
| 電源電圧 | 3.3 V or 5.0 V |
| Programming Method | JTAG in-system programmer (Altera Quartus II) |
| Cascade Support | Yes (multi-FPGA chain) |
| パッケージ | TSSOP-20 |
| 動作温度 | -40 C to +85 C (industrial grade) |
| RoHS ステータス | unknown |
| Lead-Free | unknown |
| ピン数 | 20 |
| Compatible FPGAs | Altera FLEX 10K, APEX 20K, ACEX 1K families |
| Manufacturer | Altera (now Intel FPGA) |
| ライフサイクル状態 | Obsolete / Last Time Buy (per distributor stock) |
EPC144ICC20 ピン構成
| ピン 1 | VCC — 3.3 V or 5.0 V supply |
| ピン 2 | DATA — Serial configuration data output to FPGA |
| ピン 3 | DCLK — Configuration clock input from FPGA |
| ピン 4 | nCONFIG — Configuration control (active-low) |
| ピン 5 | nSTATUS — Status output (active-low) |
| ピン 6 | CONF_DONE — Configuration complete output |
| ピン 7 | nCS — Chip select (active-low) |
| ピン 8 | OE — Output enable (active-low) |
| ピン 9 | nCASC — Cascade output for chained PROMs (active-low) |
| ピン 10 | GND — Ground |
| ピン 11 | TDI — JTAG test data input |
| ピン 12 | TMS — JTAG test mode select |
| ピン 13 | TCK — JTAG test clock |
| ピン 14 | TDO — JTAG test data output |
| ピン 15 | A0 — Address line 0 (for parallel mode) |
| ピン 16 | A1 — Address line 1 (for parallel mode) |
| ピン 17 | A2 — Address line 2 (for parallel mode) |
| ピン 18 | A3 — Address line 3 (for parallel mode) |
| ピン 19 | A4 — Address line 4 (for parallel mode) |
| ピン 20 | A5 — Address line 5 (for parallel mode) |
主な用途
EPC144ICC20 の用途: 6 件s: FLEX 10K FPGA Configuration Loading, APEX 20K Series Boot PROM, ACEX 1K Family Configuration, Multi-FPGA Cascaded Configuration Chain, Legacy Industrial Control Systems, Avionics and Military Legacy Hardware.
FLEX 10K FPGA Configuration Loading
The EPC144ICC20 stores the configuration bitstream of legacy Altera FLEX 10K FPGAs (such as EPF10K20, EPF10K30, EPF10K50) at system power-up. Because FLEX 10K devices are SRAM-based, they lose their logic configuration when power is removed. The EPC144ICC20's 440,800-bit storage and serial configuration bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) provide a one-chip boot solution. For EPF10K100 or larger FPGAs exceeding 440k bits, two EPC144ICC20 devices can be cascaded in series to deliver the full bitstream.
おすすめ
APEX 20K Series Boot PROM
The EPC144ICC20 reliably boots Altera APEX 20K FPGAs (EP20K60, EP20K100, EP20K200) in mid-size designs where the bitstream fits within 440,800 bits. APEX 20K devices use the same serial configuration protocol as FLEX 10K, so the EPC144ICC20 is protocol-compatible. Designers should verify the .pof file size against the EPC144ICC20's 433,008 usable bits after Quartus II compression. Larger APEX 20K designs may require EPC2 or cascaded EPC144ICC20 chains.
おすすめ
ACEX 1K Family Configuration
The EPC144ICC20 is well-matched to the Altera ACEX 1K family (EP1K10, EP1K30, EP1K50, EP1K100) where the compressed bitstream typically falls below 440,800 bits. ACEX 1K FPGAs operate at 2.5V core but use 3.3V configuration I/O, which the EPC144ICC20 supports natively. The JTAG chain between EPC144ICC20 and ACEX 1K enables in-system reprogramming during development and field updates via Quartus II programmer.
おすすめ
Multi-FPGA Cascaded Configuration Chain
The EPC144ICC20 supports cascaded configuration in systems with multiple FPGAs that share a single boot chain. Multiple EPC144ICC20 devices can be wired in series with nCASC handshaking, allowing each device to forward the bitstream to the next FPGA after its own data has been delivered. This topology is used in dense compute boards where two or three FLEX 10K or APEX 20K devices must boot from a parallel set of PROMs. Each cascaded EPC144ICC20 adds 440,800 bits to the chain.
おすすめ
Legacy Industrial Control Systems
The EPC144ICC20's industrial -40 C to +85 C operating temperature range makes it suitable for legacy industrial control systems (CNC controllers, SCADA RTUs, factory automation) that were built around FLEX 10K or APEX 20K FPGAs in the late 1990s and early 2000s. As of 2026-09-11, many of these systems remain in service and require factory-programmed replacement PROMs for spare-part inventory. The one-time-programmable ICC20 variant is preferred for factory-sealed control systems that should not be field-reprogrammed.
おすすめ
Avionics and Military Legacy Hardware
The EPC144ICC20 and its pin-compatible EPC1441LI20 variant are used to refresh configuration PROMs in legacy military and avionics systems where the original FLEX 10K or APEX 20K FPGAs remain qualified but the original boot PROMs have failed or aged out. The industrial temperature grade and UV-erasable package enable depopulation and re-programming during depot-level maintenance. For new designs, modern FPGAs with internal flash configuration are recommended, but for legacy sustainment, the EPC144ICC20 remains the qualified boot PROM.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPC144ICC20 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPC1441LI20 | EPC1441LI20N | EPC1441LC20 | EPC1441LC20N | EPC1213LI20 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | TSSOP-20 | TSSOP-20 | TSSOP-20 | TSSOP-20 | TSSOP-20 | TSSOP-20 |
| Memory Size | 440,800 bits | 440,800 bits | 440,800 bits | 440,800 bits | 440,800 bits | 212,942 bits (-52%) |
| Usable Configuration Bits | 433,008 bits | 433,008 bits | 433,008 bits | 433,008 bits | 433,008 bits | 212,942 bits |
| Operating Temperature | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) |
| Supply Voltage | 3.3 V or 5.0 V | 3.3 V or 5.0 V | 3.3 V or 5.0 V | 3.3 V or 5.0 V | 3.3 V or 5.0 V | 3.3 V or 5.0 V |
| JTAG Programming | Yes | Yes | Yes | Yes | Yes | Yes |
| Cascade Support | Yes (multi-FPGA chain) | Yes | Yes | Yes | Yes | Yes |
| Compatible FPGA Families | FLEX 10K, APEX 20K, ACEX 1K | FLEX 10K, APEX 20K, ACEX 1K | FLEX 10K, APEX 20K, ACEX 1K | FLEX 10K, APEX 20K, ACEX 1K | FLEX 10K, APEX 20K, ACEX 1K | FLEX 10K, APEX 20K, ACEX 1K (small devices only) |
主な差別化要因
- Industrial-grade TSSOP-20 footprint with -40 to +85 C range （vs EPC1441LC20)
- Drop-in compatible with multiple TSSOP-20 EPC1441 family variants （vs EPC1441TC32)
- 440,800-bit storage sufficient for mid-size FLEX 10K and APEX 20K FPGAs （vs EPC1213LI20)
設計ノート
Provide a clean 3.3 V or 5.0 V supply to VCC (pin 1) with a 0.1 uF decoupling capacitor placed within 5 mm of the VCC pin. The EPC144ICC20 draws approximately 50 mA peak during configuration readback; bulk capacitance of 10 uF is recommended on the supply rail. Do not share VCC with switching DC-DC converters - noise above 50 mVpp can corrupt the configuration clock (DCLK) domain.
Route the DATA and DCLK traces as a matched-length pair, keeping them under 50 mm to avoid skew. Place a 33 ohm series resistor on the DCLK line near the EPC144ICC20 to dampen reflections if the FPGA is more than 25 mm away. The nSTATUS, nCONFIG, and CONF_DONE signals are open-drain on the FPGA side and require 10 kohm pull-ups to VCC. CONF_DONE must transition high within 100 us of the last bit for the FPGA to enter user mode.
Estimated: a common mistake is to leave the JTAG chain disconnected - without including the EPC144ICC20 in the JTAG TDI-TDO chain between the JTAG header and the FPGA, Quartus II programmer cannot detect the PROM. Always include the EPC144ICC20 in the JTAG chain in the BSDL file order, and verify with the JTAG chain debugger before attempting programming. Also verify that the .pof file size does not exceed the 433,008 usable bits - Quartus II will warn but the engineer must manually trim the design if oversize.
Place the EPC144ICC20 within 50 mm of the target FPGA to minimize DCLK/Data skew. Keep the configuration bus traces on the same PCB layer without vias; vias on DCLK add 1-2 ns of jitter per via. For multi-FPGA cascaded chains, route nCASC from PROM-1 to nCS of PROM-2 with a maximum stub length of 10 mm. The TSSOP-20 exposed pad (if present on the package variant) should be soldered to a copper pour for thermal relief.
コンプライアンス情報
RoHS and lead-free status marked unknown because the verified web data does not include explicit compliance certificates for EPC144ICC20. The LI20 variants are typically lead-free, but engineers should verify the specific lot certificate with the distributor before assembly.
