XCF04SVOG20C - 4Mb Platform Flash Configuration PROM | AMD/Xilinx
部品番号: XCF04SVOG20C ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $59.81 | $59.81 |
| 10 | $55.2 | $552.00 |
| 100 | $47.85 | $4,785.00 |
| 500 | $41.4 | $20,700.00 |
| 1,000 | $36.9 | $36,900.00 |
XCF04SVOG20C 概要
A Platform Flash PROM is a non-volatile configuration memory IC that boots up an FPGA by clocking out its stored bitstream at power-on. The category belongs to the broader taxonomy of FPGA configuration memories -> serial flash for FPGAs -> non-volatile boot memory -> programmable logic support ICs. Unlike generic SPI flash, Platform Flash PROMs are designed with FPGA-specific control signals (CCLK, DONE, INIT, PROGRAM) and timing compatible with Xilinx slave-serial and SelectMAP-mapped configuration protocols, which simplifies board design and removes the need to bind an MCU to load the bitstream.
Key features include a low-power advanced CMOS FLASH process, IEEE 1149.1 JTAG boundary-scan and in-system programming, configurable slave serial or daisy-chain configuration modes, an internal oscillator that drives the master CCLK output, design version storage for multi-bitstream systems, and a read-protect security fuse. The PROM is specified for 3.3V core and I/O operation and is rated for an operating temperature range appropriate to industrial environments.
Architecturally, the XCF04SVOG20C combines a 4-Mbit flash array with a configuration controller state machine that handles FPGA handshaking. Endurance is rated by the manufacturer at thousands of program/erase cycles, and data retention is specified in years for industrial-grade operation. The single-pin-per-bit data path makes the device pin-compatible within the Platform Flash PROM family across densities of 1 Mbit, 4 Mbit, 8 Mbit, 16 Mbit, and 32 Mbit.
Typical applications include Spartan-6 and Virtex-5 FPGA configuration, FPGA-based industrial controllers that boot from non-volatile memory, test-and-measurement loaders, and any Xilinx FPGA system that requires field-updatable configuration or daisy-chained multi-FPGA configuration. Designers also use Platform Flash PROMs in safety-critical systems because the PROM's configuration validity is verified by the FPGA's CRC logic at every boot.
Design consideration: when migrating an XCF04S design to a newer Xilinx configuration solution, verify the master/slave mode and DONE polarity on the PCB. Also note that the XCF04SVOG20C has been transitioned out of production by AMD/Xilinx (see lifecycle status); users with long-lived programs should plan around the suggested active alternatives listed below.
This page consolidates distributor pricing, lifecycle status, drop-in alternatives, and design notes for engineers migrating off the XCF04SVOG20C, with information that goes beyond the manufacturer datasheet.
ドロップイン代替品: XCF04SVOG20C — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: XCF04SVOG20C （同一形状・フットプリント） — 相違点: Memory Type, Supply Voltage, Bits per Word, Density, Logic Family.
クイック比較ツール — 並列比較する代替部品を選択:
XCF04SVOGG20C
✅ ドロップイン📋 参考代替品（カタログ未掲載）
XCF04SVOGG20C0936
✅ ドロップイン📋 参考代替品（カタログ未掲載）
XCF04SVOGG20CES
✅ ドロップイン📋 参考代替品（カタログ未掲載）
XCF04SVOG20CES
✅ ドロップイン📋 参考代替品（カタログ未掲載）
XCF02SVOG20C
✅ ドロップイン✓ 在庫あり
$19.4 / 個
データシートを見る →XCF04SVOG20C 最大定格＆電気的特性
| メモリタイプ | In-System Programmable Configuration PROM (Flash) |
| Density | 4194 kbit (4 Mbit) |
| メモリ構成 | 4000k words x 1 bit |
| Bits per Word | 1 |
| Interface / Protocol | Serial / Daisy-chain (Xilinx slave-serial) |
| Programming Interface | JTAG (IEEE 1149.1) |
| 電源電圧 | 3.0 V to 3.6 V (3.3 V typ.) |
| Logic Family | CMOS (advanced CMOS FLASH process) |
| 動作温度 | -40C to +85C (industrial) |
| パッケージ | TSSOP-20 |
| ピン数 | 20 |
| 実装タイプ | Surface Mount |
| Configuration Modes | Slave serial / Daisy chain |
| Design Version Storage | Supported (multi-bitstream) |
| Data Compression | Built-in (decompresses up to 8 Mbit compressed bitstream) |
| Read Protection | Yes (security fuse) |
| Internal Oscillator (CCLK) | Yes |
XCF04SVOG20C ピン構成
| ピン 1 | GND — Ground reference |
| ピン 2 | TMS — JTAG test mode select (IEEE 1149.1) |
| ピン 3 | TDI — JTAG test data input |
| ピン 4 | TCK — JTAG test clock |
| ピン 5 | CF — Configuration mode select |
| ピン 6 | NC — Not connected (per datasheet) |
| ピン 7 | PROGRAM — Active-low PROGRAM from FPGA |
| ピン 8 | INIT — FPGA INIT handshake, open-drain |
| ピン 9 | DONE — FPGA DONE handshake, open-drain |
| ピン 10 | CCLK — Configuration clock from FPGA |
| ピン 11 | DOUT — Daisy-chain data out to next PROM |
| ピン 12 | DIN — Configuration data input from PROM DOUT |
| ピン 13 | OE/RESET — Output enable / reset |
| ピン 14 | CE — Chip enable (active low in some modes) |
| ピン 15 | NC — Not connected (per datasheet) |
| ピン 16 | NC — Not connected (per datasheet) |
| ピン 17 | NC — Not connected (per datasheet) |
| ピン 18 | TDO — JTAG test data output |
| ピン 19 | NC — Not connected (per datasheet) |
| ピン 20 | VCC — +3.3 V supply voltage |
主な用途
XCF04SVOG20C の用途: 6 件s: Spartan-6 FPGA Slave-Serial Configuration, Daisy-Chained Multi-FPGA Configuration, Industrial Embedded Controller Boot Memory, Field-Updatable FPGA Logic via JTAG, Test & Measurement Instrumentation, Safety-Critical Configuration with CRC Verification.
Spartan-6 FPGA Slave-Serial Configuration
The XCF04SVOG20C is the recommended boot device for Spartan-6 LX and LXT FPGAs in low-to-mid density designs, where its 4 Mbit raw storage holds the uncompressed bitstream of devices such as the XC6SLX16-3CPG196C. Placed adjacent to the FPGA on the PCB, the PROM clocks configuration data out on each rising edge of CCLK under the Xilinx slave-serial protocol, and the FPGA's DONE/INIT handshake signals verify the bitstream before starting user logic. Compatibility with Spartan-6, Spartan-3E, and Virtex-5 families means a single 20-pin TSSOP footprint supports many existing FPGA boards.
おすすめ
Daisy-Chained Multi-FPGA Configuration
When a board carries multiple FPGAs or a chain of Spartan-6 / Virtex-5 devices, the XCF04SVOG20C drives a DOUT pin into the next device's DIN to extend the configuration chain without adding controller logic. Each PROM in the chain loads its slice of the multi-bitstream; designers typically allocate one 4 Mbit PROM per Spartan-6 LX16-class device. The Platform Flash PROM family supports this natively, so no glue logic is required between daisy-chained FPGAs.
おすすめ
Industrial Embedded Controller Boot Memory
Industrial controllers using Spartan-6 or Spartan-3E FPGAs typically store their bitstream in an XCF04SVOG20C so the system boots unattended on power-up without an MCU supervisor. The -40C to +85C operating range fits factory-floor and outdoor cabinet enclosures, and the optional data decompression roughly doubles usable storage when the bitstream is pre-compressed by iMPACT, allowing room for future feature additions on the same 20-pin TSSOP board footprint.
おすすめ
Field-Updatable FPGA Logic via JTAG
Designers program the XCF04SVOG20C in-system through its JTAG pins (TDI/TDO/TCK/TMS per IEEE 1149.1), so firmware revisions can be pushed to deployed boards via Xilinx iMPACT or Vivado without removing the chip. The design-version storage feature enables multiple slot-stored bitstreams on a single PROM, allowing A/B redundancy in safety-critical industrial systems. Because the data interface is JTAG, no external programmer is required during field service.
おすすめ
Test & Measurement Instrumentation
Test fixtures and modular instruments that use Spartan-3E / Spartan-6 FPGAs for digital signal processing can be re-characterized by re-flashing the XCF04SVOG20C in-circuit, allowing the same hardware platform to host several calibration variants without re-spinning the board. The PROM's slave-serial clock recovery from the FPGA's CCLK keeps configuration deterministic across product revisions, and the TSSOP-20 footprint simplifies probe access during bench characterization.
おすすめ
Safety-Critical Configuration with CRC Verification
In functional-safety applications (rail, avionics subsystems, medical lab instruments), the XCF04SVOG20C stores the golden bitstream that the Spartan-6 / Virtex-5 FPGA verifies by CRC at every boot. If the check fails, the FPGA drives INIT low and asserts the proper system fault, so configuration integrity is tied directly to the reliability of the non-volatile flash cell. Pairing this PROM with a watchdog supervisor such as the TPS3808G50QDBVRQ1 adds independent power-rail monitoring before the FPGA starts execution.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: XCF04SVOG20C — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | XCF04SVOGG20C | XCF04SVOGG20C0936 | XCF04SVOGG20CES | XCF04SVOG20CES | XCF02SVOG20C |
|---|---|---|---|---|---|---|
| Brand | AMD / Xilinx | AMD / Xilinx | AMD / Xilinx | AMD / Xilinx | AMD / Xilinx | AMD / Xilinx |
| Package | TSSOP-20 | TSSOP-20 - same | TSSOP-20 - same | TSSOP-20 - same | TSSOP-20 - same | TSSOP-20 - same |
| Memory Density | 4 Mbit | 4 Mbit | 4 Mbit | 4 Mbit | 4 Mbit | 2 Mbit (-50%) |
| Configuration Protocol | Slave-serial / daisy chain | Slave-serial / daisy chain | Slave-serial / daisy chain | Slave-serial / daisy chain | Slave-serial / daisy chain | Slave-serial / daisy chain |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lead-free / Green | Varies by date code | Yes (G = green) | Yes (G = green) | Yes (G = green) | Varies | Varies |
| Compatibility with Spartan-6 / Virtex-5 | Yes | Yes | Yes | Yes | Yes | Yes (density-limited) |
| Lifecycle Status | Obsolete | Active | Active | Active | EOL | Active |
主な差別化要因
- Active lead-free production status （vs XCF04SVOG20C)
- Same footprint, half the density （vs XCF02SVOG20C)
- Lower per-unit cost than EOL stock （vs XCF04SVOG20CES)
設計ノート
The XCF04SVOG20C is OBSOLETE per the AMD/Xilinx Product Discontinuance Notice dated September 28, 2020. New designs should target the active XCF04SVOGG20C drop-in in the same 20-pin TSSOP footprint, since the G suffix denotes lead-free green compliance and is in active production. Confirm with your supplier that any existing inventory is genuine before placing production orders.
Place the XCF04SVOG20C adjacent to the FPGA's configuration pins to keep the CCLK/DIN traces short (under 2 inches if possible). Add a 0.1 uF decoupling capacitor on VCC (pin 20) within 50 mils of the pad, and tie GND (pin 1) directly to the ground plane with a via-in-pad or short trace. For daisy-chained configurations, route DOUT to DIN of the next FPGA with matched trace length to avoid intra-clock skew.
The DONE and INIT signals are open-drain on the PROM side and require a 4.7 kohm pull-up to VCCO of the FPGA's configuration bank. Pull-up resistors should be located near the FPGA, not the PROM, so the rise time is preserved across long PCB traces. Keep TMS, TDI, TCK, TDO from the PROM JTAG port away from switching DC-DC converter nodes to prevent in-system programming failures.
Do NOT substitute the XCF04SVOG20C with the XCF08PVOG20C expecting pin compatibility: the XCF08P series uses a different package and may not fit the original 20-pin TSSOP footprint. Estimated mismatch: XCF08P comes in VO48 (48-pin TQFP) and a 20-pin VO20 variant has different pin assignments; verify against the XCFxxP data sheet before PCB rework, and treat the XCF08P as a functional upgrade only after a board respin.
コンプライアンス情報
G suffix variants (XCF04SVOGG20C, XCF04SVOGG20C0936, XCF04SVOGG20CES) are lead-free and RoHS-compliant by AMD/Xilinx part numbering convention. The legacy G-less parts may use leaded finishes; verify date code.
