EPC1213LI20 - 212Kb OTP Serial Config PROM for FPGAs | Intel
部品番号: EPC1213LI20 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EPC1213LI20 概要
A Configuration PROM is a non-volatile memory device that holds the FPGA configuration bitstream and serially transfers it to the SRAM-based FPGA at power-up, after system reset, or whenever reconfiguration is required. Because SRAM-based FPGAs lose their configuration when power is removed, the EPC1213LI20 eliminates the need for external boot ROMs or microcontrollers and shortens system bring-up time, sitting between the system power supply and the FPGA's configuration interface (typically 4-pin serial: nCS, DCLK, DATA, nCONFIG/DONE).
Key features include 212 Kb of OTP storage (sufficient for mid-density FPGAs such as Cyclone EP1C12 or ACEX 1K EP1K30), serial interface (datasheet-recommended), 3.3 V/5 V VCC operation with 3.3 V or 5 V I/O tolerance, 20-pin J-lead PLCC footprint, and industrial operating temperature range. Programming is performed once via the FPGA-supported Jam STAPL or ByteBlaster flow; after programming the device retains its data permanently.
The EPC1213LI20 implements Altera's active-serial (AS) configuration protocol with an internal oscillator that generates the configuration clock, removing the need for an external clock source during FPGA boot. Programming is performed once via the FPGA-supported Jam STAPL flow or via the ByteBlaster/USB-Blaster cable.
Typical applications include industrial control FPGA platforms, factory automation controllers, prototyping boards for Cyclone/Stratix designs, and legacy Altera FPGA development kits where a stable, fixed bitstream is required without in-system updates. Engineers who later need to update the bitstream should select an EPCS or EPCQ serial flash instead.
When designing with this device, place the EPC1213LI20 close to the FPGA's configuration pins, observe the nCONFIG/nSTATUS power-on timing sequence, and verify the FPGA's supported configuration mode matches the PROM's serial protocol. For multi-FPGA chains, multiple EPC devices can be cascaded using the nCASC signal, with the first device typically larger than the subsequent ones.
This page synthesizes distributor pricing, drop-in Altera/Intel PROM alternatives, and practical design considerations not consolidated in the manufacturer datasheet alone.
ドロップイン代替品: EPC1213LI20 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPC1213LI20 （同一形状・フットプリント） — 相違点: Memory Type, Operating Temperature, Interface, Package, Memory Size.
クイック比較ツール — 並列比較する代替部品を選択:
EPC1213LC20
✅ ドロップイン✓ 在庫あり
$7.4 / 個
データシートを見る →EPC1064VLC20
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$1.51 / 個
データシートを見る →EPC1064LC20
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.85 / 個
データシートを見る →EPC1213LI20 最大定格＆電気的特性
| メモリタイプ | OTP Configuration PROM (non-volatile) |
| メモリサイズ | 212 Kbit |
| インターフェースタイプ | Serial (Altera active-serial configuration) |
| Supply Voltage (VCC) | 3.3 V / 5 V |
| I/O Voltage Tolerance | 3.3 V or 5 V |
| Programmability | OTP (one-time programmable) |
| パッケージ | 20-PLCC (9x9 mm), J-lead |
| ピン数 | 20 |
| 動作温度 | -40C to +85C (industrial) |
| Compatible FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Mode | Active Serial (AS) |
| Internal Oscillator | Yes (generates DCLK to FPGA) |
| Cascade Support | Yes (nCASC pin for multi-device chains) |
EPC1213LI20 ピン構成
| ピン 1 | A0/MSEL — Address input for cascade / mode select |
| ピン 2 | nCS — Chip select (active low) from FPGA |
| ピン 3 | DCLK — Configuration clock input from FPGA |
| ピン 4 | DATA — Serial data output to FPGA |
| ピン 5 | nCONFIG — Configuration control (active low) |
| ピン 6 | nSTATUS — Status output (active low) |
| ピン 7 | OE — Output enable (active low) |
| ピン 8 | nCASC — Cascade output to next PROM (active low) |
| ピン 9 | GND — Ground |
| ピン 10 | GND — Ground |
| ピン 11 | GND — Ground |
| ピン 12 | VCC — Supply voltage (3.3 V or 5 V) |
| ピン 13 | VCC — Supply voltage (3.3 V or 5 V) |
| ピン 14 | VCC — Supply voltage (3.3 V or 5 V) |
| ピン 15 | A1 — Address input for cascade |
| ピン 16 | A2 — Address input for cascade |
| ピン 17 | nCE — Chip enable (active low) |
| ピン 18 | RESERVED — Reserved - leave floating or to VCC |
| ピン 19 | RESERVED — Reserved - leave floating |
| ピン 20 | VCC — Supply voltage (3.3 V or 5 V) |
主な用途
EPC1213LI20 の用途: 6 件s: Altera Cyclone FPGA Boot Memory, Legacy FLEX 10K Design Support, Stratix II GX Configuration Source, Industrial Control Systems, Prototyping & Development Boards, Military & Aerospace FPGA Platforms.
Altera Cyclone FPGA Boot Memory
The EPC1213LI20 stores the FPGA bitstream and serially loads it into Cyclone EP1C12 or similar mid-density FPGAs at power-up via the active-serial protocol. Its 212 Kbit capacity matches Cyclone bitstream sizes (1.0-1.4 Mbit compressed), and the on-chip oscillator drives DCLK without external clocking. Cascade support via nCASC enables multi-FPGA configuration chains for parallel processing boards. Designers should verify FPGA-supported configuration modes match the PROM's serial protocol before committing to the 20-PLCC footprint.
おすすめ
Legacy FLEX 10K Design Support
For legacy Altera FLEX 10K and FLEX 6000 designs, the EPC1213LI20 provides reliable one-time configuration storage in industrial temperature environments. The 3.3 V/5 V supply flexibility matches older 5 V-tolerant FLEX configuration interfaces, and the 20-PLCC J-lead package is socket-compatible with development board footprints designed in the late 1990s. This PROM remains the only practical choice for maintaining existing FLEX-based products where PCB redesign is cost-prohibitive.
おすすめ
Stratix II GX Configuration Source
In Stratix II GX designs where the bitstream is finalized and field updates are not required, the EPC1213LI20 supplies the initial configuration data via the active-serial interface. Designers using larger Stratix II devices (EP2SGX30 and above) should verify bitstream size - if exceeding 212 Kbit, cascade multiple EPC devices using nCASC. The PLCC-20 socket allows field replacement during board bring-up without reworking the FPGA footprint.
おすすめ
Industrial Control Systems
The EPC1213LI20's industrial -40C to +85C operating range makes it suitable for factory automation controllers, PLC platforms, and industrial motor drives using Altera FPGAs. Its OTP nature prevents accidental bitstream corruption in the field, which is critical for safety-certified industrial equipment. The 20-PLCC package offers mechanical robustness against vibration when socketed with retention clips, and the 3.3 V/5 V supply compatibility supports legacy industrial 5 V rails.
おすすめ
Prototyping & Development Boards
Educational and prototyping Altera FPGA boards historically used EPC1213LI20 to provide stable pre-programmed configuration for student projects and reference designs. The PLCC-20 socket allows the PROM to be swapped between exercises or removed when using JTAG-only configuration during development. This use case is fading as modern development kits adopt USB-Blaster direct JTAG programming, but legacy Cyclone II and Stratix II boards still benefit from the EPC1213 for plug-and-play demos.
おすすめ
Military & Aerospace FPGA Platforms
In military and aerospace applications where single-source, locked configuration is preferred over field-updatable flash, the EPC1213LI20's OTP behavior provides a security advantage - the bitstream cannot be remotely altered. Its industrial temperature grade (-40C to +85C) supports most ground-based and avionics environments, though extended-temp (-55C) screening requires derating analysis. Cascade chains support multi-FPGA signal processing payloads common in defense applications.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPC1213LI20 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPC1213LC20 | EPC1064VLC20 | EPC1064LC20 |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 20-PLCC (9x9 mm) | 20-PLCC (9x9 mm) - same | 20-PLCC - same | 20-PLCC - same |
| Memory Size | 212 Kbit | 212 Kbit (same) | 65 Kbit (smaller) | 65 Kbit (smaller) |
| Programmability | OTP (one-time) | OTP (one-time) | OTP (one-time) | OTP (one-time) |
| Supply Voltage | 3.3 V / 5 V | 3.3 V / 5 V | 5 V only | 5 V only |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial, VCC=5V) | 0C to +70C (commercial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
| Compatible FPGA Family | FLEX/ACEX/APEX/Cyclone/Stratix | Same families | FLEX 6000 / FLEX 10K (smaller FPGAs only) | FLEX 6000 / FLEX 10K (smaller FPGAs only) |
主な差別化要因
- Industrial temperature grade in same package （vs EPC1213LC20)
- 4x larger capacity in same footprint （vs EPC1064LC20)
- Multi-voltage support vs 5V only （vs EPC1064VLC20)
設計ノート
Estimated: at 3.3 V VCC and active serial configuration, peak supply current is approximately 30 mA typical / 50 mA peak during configuration load. Decouple VCC with a 100 nF ceramic capacitor placed within 5 mm of pins 12-14 and 20, plus a 10 uF tantalum bulk capacitor on the VCC plane. During standby (post-configuration), current drops below 5 mA. Multiple cascaded PROMs multiply active current - budget power accordingly.
Place the EPC1213LI20 within 50 mm of the FPGA's configuration pins (nCS, DCLK, DATA, nCONFIG, nSTATUS) to avoid signal integrity issues. Use a continuous ground plane under the PLCC-20 socket; route DCLK as a controlled-impedance trace (50 ohm typical) with no more than two vias. For cascade chains, place downstream EPC devices in physical sequence along the nCASC signal path to minimize stub lengths.
Critical: the EPC1213LI20 is OTP - verify the bitstream is final before programming. Once programmed, the device cannot be erased or rewritten. For prototypes, use an EPCS/EPCQ flash device instead. Also note that the EPC1213 does NOT support in-system programming from the FPGA's JTAG chain - an external programmer (ByteBlaster) is required.
Series-terminate the DCLK signal with a 33 ohm resistor near the FPGA driver to suppress reflections on long configuration traces. The DATA output from the EPC1213LI20 is a 3-state signal - confirm the FPGA's DATA input has a proper pull-up if the PROM is disconnected during JTAG configuration. Watch for ground bounce on simultaneous multi-pin switching during configuration; use stitching capacitors every 4th pin along the PLCC socket.
コンプライアンス情報
EPC1213LI20 is a legacy Altera (now Intel) part - detailed compliance certificates should be requested from Intel directly. As an industrial-grade part, AEC-Q100 automotive qualification does not apply. RoHS/REACH compliance is not explicitly stated in distributor data.
