EPM570T100A5N - 570 LEs, 440 Macrocells, MAX II CPLD | Altera
部品番号: EPM570T100A5N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $11.2 | $11.20 |
| 10 | $10.08 | $100.80 |
| 100 | $8.96 | $896.00 |
| 500 | $7.84 | $3,920.00 |
| 1,000 | $6.72 | $6,720.00 |
EPM570T100A5N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PLA-style logic blocks (Logic Array Blocks, or LABs) on a single chip with a global interconnect matrix. CPLDs are positioned below FPGAs in cost and complexity but above simple PALs/GALs in density, and they retain their configuration without an external configuration memory. In the broader programmable logic taxonomy, CPLDs sit alongside FPGAs as programmable logic devices, both derived from programmable read-only memory technology, and serve as power-management companion logic, bus interfaces, and deterministic boot-time controllers.
Key features include instant-on (no boot PROM required thanks to on-chip flash), 1.8 V internal core voltage, MultiVolt™ I/O supporting 1.5/1.8/2.5/3.3 V interfaces, JTAG-based IEEE 1149.1 in-system programmability, and a 4-wire JTAG chain for boundary-scan testing. The device also offers 8 Kbits of user flash memory (UFM) for storing parameters, serial numbers, or small configuration tables, plus a built-in oscillator that supports common asynchronous tasks without external clocks.
Architecturally, the EPM570T100A5N combines a non-volatile flash configuration cell array with a deterministic logic fabric that delivers predictable, jitter-free timing well suited to control applications. Compared with SRAM-based FPGAs, MAX II CPLDs are immune to configuration-memory bit-flip events and require no external boot device, reducing BOM cost and PCB footprint.
Typical applications include I/O expansion and voltage translation between 3.3 V MCUs and 5.0 V peripherals, power-sequencing logic for multi-rail systems, LED display refresh and multiplexing controllers, industrial bus bridges (SPI, I2C, UART), and FPGA/CPLD configuration-memory replacement. Designers favor MAX II for designs that need deterministic boot, low standby power, and minimal board area.
When designing, allow sufficient decoupling on each VCCINT and VCCIO bank, and observe the I/O bank grouping rules from the Altera MAX II Device Handbook. Route JTAG signals (TCK, TMS, TDI, TDO) with short, parallel traces and a 4.7 kΩ pull-up on TCK. Avoid using the I/O banks above 3.3 V when the connected peripherals only need 3.3 V, to minimize EMI and simplify signal integrity.
This page synthesizes distributor pricing, verified drop-in alternatives from the MAX II family, and practical design notes that go beyond the manufacturer datasheet to help engineers shorten selection time.
ドロップイン代替品: EPM570T100A5N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM570T100A5N （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Family, Programming Interface, Configuration Memory.
クイック比較ツール — 並列比較する代替部品を選択:
EPM570GT100C5N
✅ ドロップイン✓ 在庫あり
$11.05 / 個
データシートを見る →EPM570T100I5N
✅ ドロップイン✓ 在庫あり
$12.49 / 個
データシートを見る →EPM570GT100I5N
✅ ドロップイン✓ 在庫あり
$16.5 / 個
データシートを見る →EPM570GT100I5
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$4.95 / 個
データシートを見る →EPM570GM100C5N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$10.4 / 個
データシートを見る →XC9572XL-100TQG
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM570T100A5N 最大定格＆電気的特性
| Device Family | MAX II |
| Logic Elements | 570 |
| Macrocells | 440 |
| User I/O Pins | 76 |
| Number of Logic Array Blocks (LABs) | 57 |
| パッケージ | 100-pin TQFP |
| Pin-to-Pin Logic Delay (tPD) | 5.4 ns |
| Maximum Internal Frequency | 304 MHz |
| Core Supply Voltage (VCCINT) | 1.8 V (typical) |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| User Flash Memory (UFM) | 8 Kbits |
| Configuration Memory | On-chip non-volatile flash |
| Programming Interface | JTAG (IEEE 1149.1) - ISP |
| 動作温度 | -40 °C to +125 °C (industrial) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
EPM570T100A5N ピン構成
| ピン 1 | I/O — User I/O bank 1 |
| ピン 2 | I/O — User I/O bank 1 |
| ピン 3 | I/O — User I/O bank 1 |
| ピン 4 | I/O — User I/O bank 1 |
| ピン 5 | I/O — User I/O bank 1 |
| ピン 6 | I/O — User I/O bank 1 |
| ピン 7 | I/O — User I/O bank 1 |
| ピン 8 | I/O — User I/O bank 1 |
| ピン 9 | I/O — User I/O bank 1 |
| ピン 10 | I/O — User I/O bank 1 |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O bank 1 |
| ピン 13 | I/O — User I/O bank 1 |
| ピン 14 | I/O — User I/O bank 1 |
| ピン 15 | I/O — User I/O bank 1 |
| ピン 16 | I/O — User I/O bank 1 |
| ピン 17 | I/O — User I/O bank 1 |
| ピン 18 | I/O — User I/O bank 1 |
| ピン 19 | I/O — User I/O bank 1 |
| ピン 20 | I/O — User I/O bank 1 |
| ピン 21 | VCCIO1 — I/O bank 1 supply (1.5/1.8/2.5/3.3 V) |
| ピン 22 | I/O — User I/O bank 1 |
| ピン 23 | I/O — User I/O bank 1 |
| ピン 24 | I/O — User I/O bank 1 |
| ピン 25 | I/O — User I/O bank 1 |
| ピン 26 | I/O — User I/O bank 2 |
| ピン 27 | I/O — User I/O bank 2 |
| ピン 28 | I/O — User I/O bank 2 |
| ピン 29 | I/O — User I/O bank 2 |
| ピン 30 | GND — Ground |
| ピン 31 | I/O — User I/O bank 2 |
| ピン 32 | I/O — User I/O bank 2 |
| ピン 33 | I/O — User I/O bank 2 |
| ピン 34 | I/O — User I/O bank 2 |
| ピン 35 | I/O — User I/O bank 2 |
| ピン 36 | I/O — User I/O bank 2 |
| ピン 37 | VCCIO2 — I/O bank 2 supply (1.5/1.8/2.5/3.3 V) |
| ピン 38 | I/O — User I/O bank 2 |
| ピン 39 | I/O — User I/O bank 2 |
| ピン 40 | I/O — User I/O bank 2 |
| ピン 41 | I/O — User I/O bank 2 |
| ピン 42 | I/O — User I/O bank 2 |
| ピン 43 | I/O — User I/O bank 2 |
| ピン 44 | I/O — User I/O bank 2 |
| ピン 45 | I/O — User I/O bank 2 |
| ピン 46 | I/O — User I/O bank 2 |
| ピン 47 | I/O — User I/O bank 2 |
| ピン 48 | I/O — User I/O bank 2 |
| ピン 49 | I/O — User I/O bank 2 |
| ピン 50 | VCCINT — Core supply 1.8 V |
| ピン 51 | GND — Ground |
| ピン 52 | I/O — User I/O bank 3 |
| ピン 53 | I/O — User I/O bank 3 |
| ピン 54 | I/O — User I/O bank 3 |
| ピン 55 | I/O — User I/O bank 3 |
| ピン 56 | I/O — User I/O bank 3 |
| ピン 57 | I/O — User I/O bank 3 |
| ピン 58 | I/O — User I/O bank 3 |
| ピン 59 | I/O — User I/O bank 3 |
| ピン 60 | I/O — User I/O bank 3 |
| ピン 61 | VCCIO3 — I/O bank 3 supply (1.5/1.8/2.5/3.3 V) |
| ピン 62 | I/O — User I/O bank 3 |
| ピン 63 | I/O — User I/O bank 3 |
| ピン 64 | I/O — User I/O bank 3 |
| ピン 65 | I/O — User I/O bank 3 |
| ピン 66 | I/O — User I/O bank 3 |
| ピン 67 | I/O — User I/O bank 3 |
| ピン 68 | I/O — User I/O bank 3 |
| ピン 69 | I/O — User I/O bank 3 |
| ピン 70 | I/O — User I/O bank 3 |
| ピン 71 | GND — Ground |
| ピン 72 | I/O — User I/O bank 4 |
| ピン 73 | I/O — User I/O bank 4 |
| ピン 74 | I/O — User I/O bank 4 |
| ピン 75 | I/O — User I/O bank 4 |
| ピン 76 | I/O — User I/O bank 4 |
| ピン 77 | VCCIO4 — I/O bank 4 supply (1.5/1.8/2.5/3.3 V) |
| ピン 78 | I/O — User I/O bank 4 |
| ピン 79 | I/O — User I/O bank 4 |
| ピン 80 | I/O — User I/O bank 4 |
| ピン 81 | I/O — User I/O bank 4 |
| ピン 82 | I/O — User I/O bank 4 |
| ピン 83 | I/O — User I/O bank 4 |
| ピン 84 | I/O — User I/O bank 4 |
| ピン 85 | I/O — User I/O bank 4 |
| ピン 86 | I/O — User I/O bank 4 |
| ピン 87 | GND — Ground |
| ピン 88 | TDI — JTAG Test Data In |
| ピン 89 | TMS — JTAG Test Mode Select |
| ピン 90 | TCK — JTAG Test Clock |
| ピン 91 | TDO — JTAG Test Data Out |
| ピン 92 | GND — Ground |
| ピン 93 | I/O — User I/O bank 4 |
| ピン 94 | I/O — User I/O bank 4 |
| ピン 95 | I/O — User I/O bank 4 |
| ピン 96 | I/O — User I/O bank 4 |
| ピン 97 | I/O — User I/O bank 4 |
| ピン 98 | I/O — User I/O bank 4 |
| ピン 99 | I/O — User I/O bank 4 |
| ピン 100 | I/O — User I/O bank 4 |
主な用途
EPM570T100A5N の用途: 6 件s: I/O Expansion and Voltage Translation, Power Sequencing Logic, Industrial Bus Bridging (SPI, I2C, UART), LED Display Refresh and Multiplexing, FPGA Configuration Memory Replacement, Glue Logic and Custom State Machines.
I/O Expansion and Voltage Translation
The EPM570T100A5N excels at I/O expansion for microcontrollers that lack sufficient pins or need to interface with peripherals at mismatched voltage rails. Its MultiVolt I/O banks natively support 1.5 V, 1.8 V, 2.5 V, and 3.3 V, enabling direct bridging between a 3.3 V MCU and 1.8 V sensors without external level shifters. With 76 user I/O and 5.4 ns pin-to-pin delay, the CPLD can debounce, multiplex, and serialize signals in real time for industrial control panels and human-machine interfaces.
おすすめ
Power Sequencing Logic
The EPM570T100A5N is well-suited to multi-rail power sequencing because of its instant-on flash configuration and deterministic 5.4 ns timing. The CPLD can monitor PG (power-good) signals from each DC-DC converter and assert the next enable only after the previous rail stabilizes, with sub-microsecond precision. Its non-volatile storage eliminates boot races that plague SRAM-based FPGAs. Use it to sequence 0.8 V core, 1.8 V DDR, 3.3 V analog, and 5.0 V driver rails in ATX, server, and embedded designs.
おすすめ
Industrial Bus Bridging (SPI, I2C, UART)
With 570 logic elements, the EPM570T100A5N can host multiple protocol bridges simultaneously - for instance, converting SPI to parallel GPIO, I2C to UART, or UART to LVDS. The 76 user I/O and 5.4 ns delay support clock rates well above 100 MHz for SPI peripherals. Programmable logic outperforms microcontrollers in deterministic latency, which matters for real-time industrial buses like Modbus, PROFIBUS, and EtherCAT slave interfaces.
おすすめ
LED Display Refresh and Multiplexing
The EPM570T100A5N's deterministic timing and 76 I/O pins make it an effective controller for multiplexed LED matrices, seven-segment displays, and signage panels. Each LAB can drive a row/column pair, and the 5.4 ns delay supports refresh rates above 1 kHz without flicker. The on-chip 8-Kbit UFM can store fonts, animation tables, or brightness curves, eliminating an external EEPROM.
おすすめ
FPGA Configuration Memory Replacement
Designers use the EPM570T100A5N to replace dedicated configuration memory on small SRAM-based FPGAs, holding the FPGA bitstream in the on-chip flash and loading it over JTAG at boot. The CPLD's instant-on behavior means the FPGA is configured within milliseconds of power-up. This reduces BOM cost (no separate PROM) and PCB area, while the 8-Kbit UFM also stores board serial numbers and calibration data.
おすすめ
Glue Logic and Custom State Machines
The EPM570T100A5N is the canonical 'glue logic' device: it replaces dozens of 74-series TTL chips with a single reprogrammable IC, which simplifies board layout, reduces cost, and accelerates prototyping. Its 440 macrocells can implement deep finite state machines for motor control, packet processing, or sensor-fusion pre-conditioning. The non-volatile configuration lets the design ship without external boot support.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM570T100A5N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM570GT100C5N | EPM570T100I5N | EPM570GT100I5N | EPM570GT100I5 | XC9572XL-100TQG |
|---|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Altera | Altera - same brand | Altera - same brand | Altera - same brand | Altera - same brand | Xilinx - cross-brand |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 72 (equivalent logic) |
| Macrocells | 440 | 440 | 440 | 440 | 440 | 72 |
| User I/O | 76 | 76 | 76 | 76 | 76 | 72 |
| Speed Grade | A5 (5.4 ns, industrial -40 to +125C) | C5 (commercial 0 to +85C) | I5 (industrial -40 to +85C) | I5 industrial + G-series low Iq | I5 industrial + G-series low Iq | -10 speed grade |
| VCCINT (Core) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 3.3 V |
| I/O Voltage (VCCIO) | 1.5/1.8/2.5/3.3 V (MultiVolt) | 1.5/1.8/2.5/3.3 V MultiVolt | 1.5/1.8/2.5/3.3 V MultiVolt | 1.5/1.8/2.5/3.3 V MultiVolt | 1.5/1.8/2.5/3.3 V MultiVolt | 3.3 V (5V tolerant) |
主な差別化要因
- Higher density than XC9572XL in same TQFP-100 footprint （vs XC9572XL-100TQG)
- Industrial temperature grade with fastest speed bin （vs EPM570T100C5N)
- TQFP package is easier to rework than FBGA （vs EPM570F100A5N)
設計ノート
The EPM570T100A5N requires separate decoupling on VCCINT (1.8 V) and each VCCIO bank (1.5/1.8/2.5/3.3 V). Place one 0.1 µF ceramic plus one 10 µF tantalum within 5 mm of each VCC pin. Per Altera MAX II guidelines, ramp VCCINT and VCCIO simultaneously or VCCINT first; reverse sequencing can trigger latch-up. Add a 4.7 kΩ pull-up on TCK to keep the JTAG chain in a known state during power-up.
Route JTAG signals TCK, TMS, TDI, TDO in parallel with 50 Ω characteristic impedance, length-matched within 25 mm. Keep TCK away from switching signals by at least 3× the trace spacing to avoid coupling. For multi-device JTAG chains, place devices in order of TDI→TDO with the chain length under 150 mm total to stay within IEEE 1149.1 timing.
Do not assign signals to a pin that shares its VCCIO bank with a higher-voltage peripheral if your design operates the bank at lower voltage - the I/O will drive at the lower rail and fail to reach the peripheral's VIH. Always verify the VCCIO assignment for each bank in the Quartus Pin Planner before compiling. Also, ensure the JTAG chain is correctly terminated with the BSDL file for the device, otherwise Quartus Programmer will report 'unexpected TDO' errors.
Estimated: at industrial temperature extremes (-40 °C to +125 °C), the EPM570T100A5N in TQFP-100 (θJA ≈ 50 °C/W on a 4-layer JEDEC board) will dissipate up to ~1.5 W when all 76 I/O toggle at 100 MHz. Junction temperature rise above ambient is roughly 50 °C/W × 1.5 W = 75 °C, well within the 125 °C limit. Reduce toggle frequency or limit I/O count for tight-thermal designs.
コンプライアンス情報
RoHS and REACH compliant per Altera/Intel product page. The MAX II family uses Pb-free (lead-free) packaging and halogen-free mold compound. AEC-Q100 qualification is not applicable since the part is a programmable logic device, not an automotive-grade IC; check with the vendor for automotive-temperature variants.