EPM570T100C4 - 570 LEs, 5.4ns CPLD | Intel (Altera) MAX II | TQFP-100
部品番号: EPM570T100C4 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $15.32 | $15.32 |
| 10 | $14.2 | $142.00 |
| 100 | $12.5 | $1,250.00 |
| 500 | $10.8 | $5,400.00 |
| 1,000 | $9.4 | $9,400.00 |
EPM570T100C4 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile, reprogrammable digital logic IC that combines the deterministic timing of PAL/GAL architecture with modern flash-backed configuration. CPLDs sit in the broader taxonomy of programmable logic: glue-logic IC -> programmable logic device -> CPLD/FPGA -> silicon in the wider semiconductor hierarchy. Unlike FPGAs, which are RAM-based and require a configuration bitstream at every power-up, MAX II CPLDs store their configuration in on-chip flash, providing instant-on behavior at sub-100 microsecond times with zero external boot memory.
Key features include a 3.3V core / 1.8V internal supply, MultiVolt I/O supporting 1.5V, 1.8V, 2.5V, and 3.3V interfacing on every I/O bank, 80 user I/O pins (TQFP-100), in-system programmability via JTAG (IEEE 1149.1), and a built-in oscillator for free-running or timer applications. The 5.4 ns tPD makes the EPM570T100C4 one of the fastest members of the MAX II family.
The MAX II architecture uses a Logic Array Block (LAB) topology with 16 macrocells per LAB, a Programmable Interconnect Matrix (PIA), and per-macrocell registers with product-term logic. The on-chip user flash supports ISP (in-system programming) without external boot PROMs, simplifying board layout. Designers can use Quartus II / Intel Quartus Prime Web Edition for synthesis and fitting.
Typical applications include bus-bridging glue logic, I/O expansion and voltage-level translation between 1.8V/2.5V/3.3V domains, address decoding and wait-state generation for microprocessors, configuration control for power sequencers, and LED / 7-segment display multiplexing. The wide MultiVolt I/O support is particularly valuable in mixed-voltage designs where 3.3V ASICs must interface to legacy 5V peripherals.
When designing with the EPM570T100C4, ensure all four JTAG pins (TCK, TMS, TDI, TDO) are routed cleanly to a JTAG header for in-system programming. Place 0.1 uF decoupling capacitors near every VCCIO/VCCINT pin pair and provide a ground plane beneath the TQFP-100 thermal pad (exposed pad is not present on TQFP-100, but the central die flag should still tie to ground). The EPM570T100C4 is pin-compatible with the EPM570T100C3, C5, and A5 speed/temperature grades within the same T100 footprint, enabling easy migration.
ドロップイン代替品: EPM570T100C4 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM570T100C4 （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Family, Process Technology, Programming Interface.
クイック比較ツール — 並列比較する代替部品を選択:
EPM570T100C5
✅ ドロップイン✓ 在庫あり
$7.1 / 個
データシートを見る →EPM570T100C3N
✅ ドロップイン✓ 在庫あり
$8.1 / 個
データシートを見る →EPM570T100C3
✅ ドロップイン✓ 在庫あり
$8.5 / 個
データシートを見る →EPM570GT100C4N
✅ ドロップイン✓ 在庫あり
$9.85 / 個
データシートを見る →EPM570T100I5N
✅ ドロップイン✓ 在庫あり
$12.49 / 個
データシートを見る →EPM570T100A5N
✅ ドロップイン✓ 在庫あり
$6.72 / 個
データシートを見る →EPM570T100C4 最大定格＆電気的特性
| Family | MAX II |
| Logic Elements (LEs) | 570 |
| Macrocells | 440 |
| Maximum User I/O Pins (this package) | 80 |
| Pin-to-Pin Propagation Delay (tPD) | 5.4 ns |
| User Flash Memory | 8 Kbits |
| General-Purpose SRAM | 4.4 Mbits |
| Core Voltage (VCCINT) | 1.8 V |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| パッケージ | TQFP-100 (T100), 14 x 14 mm |
| 動作温度 | 0C to +85C (commercial) |
| Programming Interface | JTAG (IEEE 1149.1) - ISP |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| On-chip Oscillator | Yes (3.3 MHz / 5.5 MHz selectable) |
| Internal Logic Analyzers / ISP | JTAG-based in-system programmable, no external boot PROM required |
EPM570T100C4 ピン構成
| ピン 1 | I/O — General purpose user I/O (bank 1) |
| ピン 10 | I/O — General purpose user I/O (bank 1) |
| ピン 11 | I/O — General purpose user I/O (bank 1) |
| ピン 12 | VCCIO1 — Bank 1 I/O supply (1.5/1.8/2.5/3.3V) |
| ピン 13 | I/O — General purpose user I/O (bank 1) |
| ピン 14 | I/O — General purpose user I/O (bank 1) |
| ピン 15 | GND — Ground |
| ピン 16 | I/O — General purpose user I/O (bank 2) |
| ピン 17 | I/O — General purpose user I/O (bank 2) |
| ピン 18 | I/O — General purpose user I/O (bank 2) |
| ピン 19 | I/O — General purpose user I/O (bank 2) |
| ピン 2 | I/O — General purpose user I/O (bank 1) |
| ピン 20 | VCCIO2 — Bank 2 I/O supply |
| ピン 21 | I/O — General purpose user I/O (bank 2) |
| ピン 22 | I/O — General purpose user I/O (bank 2) |
| ピン 23 | GND — Ground |
| ピン 24 | I/O — General purpose user I/O (bank 2) |
| ピン 25 | I/O — General purpose user I/O (bank 2) |
| ピン 26 | I/O — General purpose user I/O (bank 2) |
| ピン 27 | I/O — General purpose user I/O (bank 2) |
| ピン 28 | VCCIO2 — Bank 2 I/O supply |
| ピン 29 | I/O — General purpose user I/O (bank 2) |
| ピン 3 | I/O — General purpose user I/O (bank 1) |
| ピン 30 | I/O — General purpose user I/O (bank 2) |
| ピン 31 | GND — Ground |
| ピン 32 | I/O — General purpose user I/O (bank 2) |
| ピン 33 | I/O — General purpose user I/O (bank 2) |
| ピン 34 | I/O — General purpose user I/O (bank 2) |
| ピン 35 | I/O — General purpose user I/O (bank 2) |
| ピン 36 | VCCIO2 — Bank 2 I/O supply |
| ピン 37 | I/O — General purpose user I/O (bank 2) |
| ピン 38 | I/O — General purpose user I/O (bank 2) |
| ピン 39 | GND — Ground |
| ピン 4 | I/O — General purpose user I/O (bank 1) |
| ピン 40 | I/O — General purpose user I/O (bank 2) |
| ピン 41 | TDI — JTAG Test Data In |
| ピン 42 | TMS — JTAG Test Mode Select |
| ピン 43 | TCK — JTAG Test Clock |
| ピン 44 | TDO — JTAG Test Data Out |
| ピン 45 | GND — Ground |
| ピン 46 | I/O — General purpose user I/O (bank 3) |
| ピン 47 | I/O — General purpose user I/O (bank 3) |
| ピン 48 | VCCIO3 — Bank 3 I/O supply |
| ピン 49 | I/O — General purpose user I/O (bank 3) |
| ピン 5 | VCCINT — Core supply (1.8V) |
| ピン 50 | I/O — General purpose user I/O (bank 3) |
| ピン 51 | GND — Ground |
| ピン 52 | I/O — General purpose user I/O (bank 3) |
| ピン 53 | I/O — General purpose user I/O (bank 3) |
| ピン 54 | I/O — General purpose user I/O (bank 3) |
| ピン 55 | I/O — General purpose user I/O (bank 3) |
| ピン 56 | VCCIO3 — Bank 3 I/O supply |
| ピン 57 | I/O — General purpose user I/O (bank 3) |
| ピン 58 | I/O — General purpose user I/O (bank 3) |
| ピン 59 | GND — Ground |
| ピン 6 | I/O — General purpose user I/O (bank 1) |
| ピン 60 | I/O — General purpose user I/O (bank 3) |
| ピン 61 | I/O — General purpose user I/O (bank 3) |
| ピン 62 | I/O — General purpose user I/O (bank 3) |
| ピン 63 | I/O — General purpose user I/O (bank 3) |
| ピン 64 | VCCIO3 — Bank 3 I/O supply |
| ピン 65 | I/O — General purpose user I/O (bank 3) |
| ピン 66 | I/O — General purpose user I/O (bank 3) |
| ピン 67 | GND — Ground |
| ピン 68 | I/O — General purpose user I/O (bank 3) |
| ピン 69 | I/O — General purpose user I/O (bank 4) |
| ピン 7 | I/O — General purpose user I/O (bank 1) |
| ピン 70 | VCCIO4 — Bank 4 I/O supply |
| ピン 71 | I/O — General purpose user I/O (bank 4) |
| ピン 72 | I/O — General purpose user I/O (bank 4) |
| ピン 73 | GND — Ground |
| ピン 74 | I/O — General purpose user I/O (bank 4) |
| ピン 75 | I/O — General purpose user I/O (bank 4) |
| ピン 76 | I/O — General purpose user I/O (bank 4) |
| ピン 77 | I/O — General purpose user I/O (bank 4) |
| ピン 78 | VCCIO4 — Bank 4 I/O supply |
| ピン 79 | I/O — General purpose user I/O (bank 4) |
| ピン 8 | I/O — General purpose user I/O (bank 1) |
| ピン 80 | I/O — General purpose user I/O (bank 4) |
| ピン 81 | GND — Ground |
| ピン 82 | I/O — General purpose user I/O (bank 4) |
| ピン 83 | I/O — General purpose user I/O (bank 4) |
| ピン 84 | I/O — General purpose user I/O (bank 4) |
| ピン 85 | I/O — General purpose user I/O (bank 4) |
| ピン 86 | VCCIO4 — Bank 4 I/O supply |
| ピン 87 | I/O — General purpose user I/O (bank 4) |
| ピン 88 | I/O — General purpose user I/O (bank 4) |
| ピン 89 | GND — Ground |
| ピン 9 | I/O — General purpose user I/O (bank 1) |
| ピン 90 | I/O — General purpose user I/O (bank 4) |
| ピン 91 | I/O — General purpose user I/O (bank 4) |
| ピン 92 | I/O — General purpose user I/O (bank 4) |
| ピン 93 | I/O — General purpose user I/O (bank 4) |
| ピン 94 | VCCINT — Core supply (1.8V) |
| ピン 95 | I/O — General purpose user I/O (bank 1) |
| ピン 96 | I/O — General purpose user I/O (bank 1) |
| ピン 97 | I/O — General purpose user I/O (bank 1) |
| ピン 98 | I/O — General purpose user I/O (bank 1) |
| ピン 99 | VCCIO1 — Bank 1 I/O supply |
| ピン 100 | I/O — General purpose user I/O (bank 1) |
主な用途
EPM570T100C4 の用途: 6 件s: Bus Bridging & Voltage-Level Translation, Address Decoding & Wait-State Generation, I/O Expansion for Microcontrollers, Power-Sequencer & Reset Controller, Display Multiplexing (LED / 7-Segment), Industrial Glue Logic & Legacy Replacement.
Bus Bridging & Voltage-Level Translation
The EPM570T100C4 is ideal for bus-bridging between mismatched voltage domains such as 3.3V MCUs interfacing to 1.8V sensors, because every I/O supports MultiVolt levels of 1.5/1.8/2.5/3.3V via VCCIO bank selection. With 80 user I/Os in TQFP-100, the part can translate wide parallel buses (16- or 32-bit) without external level-shifters. The 5.4 ns tPD adds at most one clock cycle of latency at 100 MHz bus rates, making it transparent to most peripheral interconnects. Quartus Prime synthesis makes the protocol translator HDL-friendly, allowing rapid adaptation between I2C, SPI, UART, and parallel bus widths on the same device.
おすすめ
Address Decoding & Wait-State Generation
The EPM570T100C4's 570 logic elements and 5.4 ns pin-to-pin delay make it a classic choice for address decoding and wait-state generation in microprocessor and microcontroller systems. The 440 macrocells can decode large memory maps or peripheral selects (chip-enable, read/write strobes) within a single access cycle, even at 100 MHz external bus rates. Combined logic and registered output macros let the same device generate handshaking, DTACK, READY, and BUSREQ signals without external glue logic. The non-volatile, instant-on MAX II configuration ensures the chip-select map is correct at every cold-boot without external boot PROM.
おすすめ
I/O Expansion for Microcontrollers
Many low-cost microcontrollers lack sufficient I/O pins for complex user interfaces. The EPM570T100C4 expands up to 80 GPIOs in TQFP-100, with each I/O supporting 1.5-3.3V MultiVolt levels for direct connection to modern MCU peripherals. The CPLD can debounce keypad inputs, multiplex 7-segment displays, drive stepper motors via PWM, and interface to legacy 5V peripherals through resistive pull-ups. With on-chip flash memory, the I/O map and pin-function assignments are preserved across power cycles, eliminating external configuration storage.
おすすめ
Power-Sequencer & Reset Controller
The EPM570T100C4 generates deterministic, multi-rail power-up and power-down sequences for FPGAs, ASICs, and complex SoCs that require strict rail timing. The 5.4 ns propagation delay and on-chip oscillator enable precise PG (power-good) chain timing, while 80 I/Os support monitoring of up to 16-20 voltage rails with parallel fault-output flags. Non-volatile storage means the sequence is correct from the very first power cycle without external boot memory, and JTAG ISP enables in-field sequencing updates via standard programmers.
おすすめ
Display Multiplexing (LED / 7-Segment)
The EPM570T100C4 can multiplex 8-digit 7-segment displays with brightness control through PWM modulation generated entirely in user logic. With 80 user I/Os, it supports up to 32 multiplexed segments or 64 individual LEDs without external drivers. The on-chip 3.3 MHz or 5.5 MHz oscillator provides a free-running PWM carrier for flicker-free dimming, and the 5.4 ns tPD allows display refresh rates above 1 kHz for stable visual output. Non-volatile storage preserves brightness calibration across power cycles.
おすすめ
Industrial Glue Logic & Legacy Replacement
The EPM570T100C4 is widely used as a 5V-tolerant glue-logic replacement for legacy 74-series TTL/CMOS parts in industrial control and factory automation designs. Its MultiVolt 3.3V I/O can directly drive legacy 5V inputs through proper bus-hold or pull-up configuration, while the 570 logic elements can replace 10-20 discrete logic packages per board. The instant-on flash configuration reduces mean-time-to-repair in field-replaceable modules, and JTAG ISP allows rapid firmware updates in the field through standardized test access ports. Industrial-grade variants (EPM570T100I5N) extend operation to -40C to +100C for factory environments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM570T100C4 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM570T100C5 | EPM570T100C3N | EPM570T100I5N |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | TQFP-100 (T100) | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same |
| Pin-to-Pin Delay (tPD) | 5.4 ns | 7.0 ns | 7.5 ns | 7.0 ns |
| Logic Elements | 570 | 570 | 570 | 570 |
| User I/O Pins | 80 | 80 | 80 | 80 |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) |
| Lead-Free Finish | Standard (SnPb) per suffix | Standard | Pb-free | Pb-free |
| Approx 1k Reel Price (USD) | $9.40 | $7.80 - $8.50 (lower-cost speed grade) | $7.20 - $8.00 | $14.00 - $16.00 (industrial premium) |
主な差別化要因
- Fastest MAX II speed grade in TQFP-100 （vs EPM570T100C5)
- Larger logic capacity than MAX II EPM240 （vs EPM240T100C5N)
- Non-volatile instant-on vs SRAM-based FPGA boot （vs Cyclone IV EP4CE6E22 (small FPGA))
設計ノート
Estimated: at typical 3.3V VCCIO and 1.8V VCCINT, the EPM570T100C4 core draws approximately 30-50 mA active and 1-2 mA standby. Decouple every VCCIO/VCCINT pin pair with a 0.1 uF X7R ceramic capacitor placed within 5 mm of the pin, plus a single 10 uF bulk capacitor near the device. VCCIO bank supplies may be powered at different voltages (1.5/1.8/2.5/3.3V), but VCCINT must remain at 1.8V +/- 5%. Sequencing order: bring up VCCINT first, then VCCIO banks, to avoid I/O latch-up.
Route the four JTAG signals (TCK, TMS, TDI, TDO) as a matched-length bus with TCK pulled to a clean ground reference; keep JTAG traces away from high-frequency switching nodes. Place a 4.7 kohm pull-up on TDI and TMS to VCCIO3 to keep the JTAG TAP controller in known state during board reset. Provide a 10-pin JTAG header (or 0.1 inch header) on every board to support in-system programming. Quartus Prime generates the SOF/JIC programming file used with the USB-Blaster, ByteBlaster, or Ethernet-Blaster download cables.
Common pitfalls with MAX II CPLDs include: (1) forgetting that VCCINT and VCCIO are separate rails - VCCINT must always be 1.8V; (2) mixing I/O standards across banks without observing bank voltage constraints; (3) driving 5V signals into 3.3V VCCIO without a series resistor or level shifter; (4) omitting the on-chip user flash lock-bit setting when security is needed; (5) confusing the C4/C5/C3 speed grades - all share pinout but have different tPD timings. Always recompile Quartus designs when changing speed grade to verify timing closure.
コンプライアンス情報
EPM570T100C4 base part number is the standard (SnPb) finish; Pb-free variants carry 'N' suffix (e.g. EPM570T100C4N). RoHS compliance verified via Intel/Altera product page. AEC-Q100 not qualified - choose EPM570T100A5N for automotive temperature grade.
