LPC55S28JBD64K - 150MHz Cortex-M33 MCU 512KB | NXP
部品番号: LPC55S28JBD64K ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $5.2 | $5.20 |
| 10 | $4.75 | $47.50 |
| 100 | $4.3 | $430.00 |
| 500 | $3.95 | $1,975.00 |
| 1,000 | $3.6 | $3,600.00 |
LPC55S28JBD64K 概要
A microcontroller (MCU) is a complete computing system on a single chip, integrating a processor core, non-volatile program memory, SRAM, and peripherals such as UART, SPI, I2C, ADC, and timers. The LPC552x/S2x family belongs to NXP's LPC5500 series within the broader EdgeVerse edge computing platform, targeting general embedded and industrial IoT applications.
Key features of the LPC55S28 include the Armv8-M mainline architecture with TrustZone hardware security, a PRINCIPE-based secure boot flow in the 'S' variant, and a cost-effective 40-nm NVM process. The Cortex-M33 core with DSP instructions delivers high performance efficiency for signal-processing workloads, while the dual-bank flash architecture supports in-field firmware updates. Peripherals include Flexcomm serial interfaces, dual 12-bit ADCs, USB full-speed device, and multiple timer/PWM blocks.
Technically, the LPC55S2x leverages pin-, software- and peripheral-compatibility across the LPC552x/S2x family, letting designers scale flash density or security features without PCB redesign. According to NXP, the family provides a balance of security, performance efficiency, and system integration for general embedded markets.
Typical applications include industrial IoT nodes, secure connected devices, motor control and digital power, consumer appliances, and medical monitoring equipment, where 150 MHz real-time performance and TrustZone-based security are required.
When designing with this part, plan the power architecture around a 1.8-3.6 V supply range and use the exposed thermal pad for ground connection and improved signal integrity. Ensure SWD and ISP programming pads are accessible for production flash and debug.
This page synthesizes distributor pricing, drop-in same-family alternatives, a 64-pin pinout reference, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: LPC55S28JBD64K — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LPC55S28JBD64K （同一形状・フットプリント） — 相違点: Package, Flash Memory, Core Processor, Interrupt Controller, Mounting Type.
クイック比較ツール — 並列比較する代替部品を選択:
LPC55S26JBD64K
✅ ドロップイン✓ 在庫あり
$3.89 / 個
データシートを見る →LPC5528JBD64K
✅ ドロップイン✓ 在庫あり
$5.3 / 個
データシートを見る →LPC5526JBD64K
✅ ドロップイン✓ 在庫あり
$3.52 / 個
データシートを見る →LPC55S16JBD64K
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
LPC55S06JBD64K
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
LPC55S28JBD64K 最大定格＆電気的特性
| Core Processor | ARM Cortex-M33 (Armv8-M mainline) |
| Core Size | 32-bit |
| 最大クロック周波数 | 150 MHz |
| Flash Memory | 512 KB |
| SRAM | 104 KB |
| 電源電圧 | 3.3 V (1.8 V to 3.6 V range) |
| Security Features | TrustZone, secure boot (S variant) |
| Peripherals | Flexcomm serial interfaces, USB full-speed device, dual 12-bit ADC, timers/PWM, DMA |
| Connectivity | UART, SPI, I2C, I2S via Flexcomm |
| パッケージ | 64-HTQFP (10x10 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| Process Technology | 40-nm NVM |
| Product Family | LPC55S2x (LPC5500 Series, EdgeVerse platform) |
| Program Memory Type | FLASH |
| Data Converters | Dual 12-bit ADC |
LPC55S28JBD64K ピン構成
| ピン 1 | PIO0_0 — GPIO0 pin 0 / analog function (flexible pin mux) |
| ピン 2 | PIO0_1 — GPIO0 pin 1 / flexible pin mux |
| ピン 3 | PIO0_2 — GPIO0 pin 2 / flexible pin mux |
| ピン 4 | PIO0_3 — GPIO0 pin 3 / flexible pin mux |
| ピン 5 | PIO0_4 — GPIO0 pin 4 / flexible pin mux |
| ピン 6 | PIO0_5 — GPIO0 pin 5 / flexible pin mux |
| ピン 7 | PIO0_6 — GPIO0 pin 6 / flexible pin mux |
| ピン 8 | PIO0_7 — GPIO0 pin 7 / flexible pin mux |
| ピン 9 | PIO0_8 — GPIO0 pin 8 / flexible pin mux |
| ピン 10 | PIO0_9 — GPIO0 pin 9 / flexible pin mux |
| ピン 11 | PIO0_10 — GPIO0 pin 10 / flexible pin mux |
| ピン 12 | PIO0_11 — GPIO0 pin 11 / flexible pin mux |
| ピン 13 | PIO0_12 — GPIO0 pin 12 / flexible pin mux |
| ピン 14 | PIO0_13 — GPIO0 pin 13 / SWDIO (serial wire debug data) |
| ピン 15 | PIO0_14 — GPIO0 pin 14 / SWCLK (serial wire debug clock) |
| ピン 16 | PIO0_15 — GPIO0 pin 15 / flexible pin mux |
| ピン 17 | PIO0_16 — GPIO0 pin 16 / flexible pin mux |
| ピン 18 | PIO0_17 — GPIO0 pin 17 / flexible pin mux |
| ピン 19 | PIO0_18 — GPIO0 pin 18 / USB0_LANGO / flexible pin mux |
| ピン 20 | PIO0_19 — GPIO0 pin 19 / flexible pin mux |
| ピン 21 | PIO0_20 — GPIO0 pin 20 / USB0_LANDP path / flexible pin mux |
| ピン 22 | PIO0_21 — GPIO0 pin 21 / flexible pin mux |
| ピン 23 | PIO0_22 — GPIO0 pin 22 / flexible pin mux |
| ピン 24 | PIO0_23 — GPIO0 pin 23 / USB0_DP (USB data plus) |
| ピン 25 | PIO0_24 — GPIO0 pin 24 / USB0_DM (USB data minus) |
| ピン 26 | PIO0_25 — GPIO0 pin 25 / flexible pin mux |
| ピン 27 | PIO0_26 — GPIO0 pin 26 / flexible pin mux |
| ピン 28 | PIO0_27 — GPIO0 pin 27 / flexible pin mux |
| ピン 29 | PIO0_28 — GPIO0 pin 28 / flexible pin mux |
| ピン 30 | PIO0_29 — GPIO0 pin 29 / flexible pin mux |
| ピン 31 | PIO0_30 — GPIO0 pin 30 / flexible pin mux |
| ピン 32 | PIO0_31 — GPIO0 pin 31 / flexible pin mux |
| ピン 33 | PIO1_0 — GPIO1 pin 0 / flexible pin mux |
| ピン 34 | PIO1_1 — GPIO1 pin 1 / flexible pin mux |
| ピン 35 | PIO1_2 — GPIO1 pin 2 / flexible pin mux |
| ピン 36 | PIO1_3 — GPIO1 pin 3 / flexible pin mux |
| ピン 37 | PIO1_4 — GPIO1 pin 4 / flexible pin mux |
| ピン 38 | PIO1_5 — GPIO1 pin 5 / flexible pin mux |
| ピン 39 | PIO1_6 — GPIO1 pin 6 / flexible pin mux |
| ピン 40 | PIO1_7 — GPIO1 pin 7 / flexible pin mux |
| ピン 41 | PIO1_8 — GPIO1 pin 8 / flexible pin mux |
| ピン 42 | PIO1_9 — GPIO1 pin 9 / flexible pin mux |
| ピン 43 | PIO1_10 — GPIO1 pin 10 / flexible pin mux |
| ピン 44 | PIO1_11 — GPIO1 pin 11 / flexible pin mux |
| ピン 45 | PIO1_12 — GPIO1 pin 12 / flexible pin mux |
| ピン 46 | PIO1_13 — GPIO1 pin 13 / flexible pin mux |
| ピン 47 | PIO1_14 — GPIO1 pin 14 / flexible pin mux |
| ピン 48 | PIO1_15 — GPIO1 pin 15 / flexible pin mux |
| ピン 49 | PIO1_16 — GPIO1 pin 16 / flexible pin mux |
| ピン 50 | PIO1_17 — GPIO1 pin 17 / flexible pin mux |
| ピン 51 | PIO1_18 — GPIO1 pin 18 / flexible pin mux |
| ピン 52 | PIO1_19 — GPIO1 pin 19 / flexible pin mux |
| ピン 53 | ADC0_CH0A / PIO — ADC0 channel 0A input / GPIO (flexible mux) |
| ピン 54 | ADC0_CH1A / PIO — ADC0 channel 1A input / GPIO (flexible mux) |
| ピン 55 | VREFP — ADC positive voltage reference |
| ピン 56 | VREFN — ADC negative voltage reference (ground) |
| ピン 57 | VDDA — Analog supply (3.3 V) |
| ピン 58 | VSSA — Analog ground |
| ピン 59 | XTALIN — Crystal oscillator input |
| ピン 60 | XTALOUT — Crystal oscillator output |
| ピン 61 | RESET — External reset input (open-drain) |
| ピン 62 | VBAT — Battery backup supply for RTC |
| ピン 63 | VDD — Digital core/IO supply (3.3 V) |
| ピン 64 | VSS — Digital ground |
主な用途
LPC55S28JBD64K の用途: 6 件s: Industrial IoT Edge Nodes, Motor Control and Digital Power, Secure Connected Devices, Consumer Appliances, Medical Monitoring Equipment, Building Automation and Access Control.
Industrial IoT Edge Nodes
The LPC55S28JBD64K fits industrial IoT nodes that need secure connectivity and real-time local processing. Its 150 MHz Cortex-M33 core with DSP instructions handles protocol stacks, sensor fusion, and local analytics, while TrustZone and secure boot protect device identity keys and firmware integrity against physical tampering. The 512 KB flash accommodates an RTOS, a TCP/MQTT stack, and OTA update banks, and the 104 KB SRAM buffers telemetry without external memory. Flexcomm serial interfaces connect to Ethernet MACs, RS-485 transceivers, or Wi-Fi/BLE modules, and the dual 12-bit ADCs digitize analog sensors directly. Deployed between sensor front-ends and cloud gateways, it adds no switching noise and keeps deterministic response under load.
おすすめ
Motor Control and Digital Power
For BLDC/PMSM drives and digital power supplies, the LPC55S28JBD64K provides the combination of a 150 MHz core, hardware PWM timers, and dual 12-bit ADCs needed for field-oriented control loops at tens of kilohertz. DSP instructions accelerate Clarke/Park transforms and PI current loops, while deterministic Cortex-M33 interrupt latency keeps current sampling phase-aligned. The 512 KB flash holds sensorless observers and parameter self-tuning routines with room for OTA updates. Complementary gate drivers and supervisors from the XAIPART catalog complete the power stage; the MCU reads bus voltage and phase currents through its ADCs and modulates the inverter with high resolution, all from a single 3.3 V rail.
おすすめ
Secure Connected Devices
Products that must protect credentials - payment terminals, smart locks, authenticated accessories - benefit from the LPC55S28's TrustZone isolation and NXP secure boot. The Cortex-M33 mainline architecture partitions a secure world holding keys and cryptographic routines from a non-secure application world, so even a compromised application cannot extract root secrets. Secure boot verifies signed firmware on every reset, and the dual-bank 512 KB flash enables fail-safe encrypted OTA updates with rollback. USB full-speed device support covers physical provisioning and user connectivity. Compared with bolting on a separate secure element, this single-chip approach reduces BOM cost while keeping the root of trust on-die.
おすすめ
Consumer Appliances
In appliances such as cooktops, air conditioners, and power tools, the LPC55S28JBD64K serves as the main control MCU driving user interfaces, sensor monitoring, and motor control. The 150 MHz core leaves headroom for capacitive-touch processing and display updates while running the main state machine, and Flexcomm UART/SPI/I2C interfaces connect displays, EEPROMs, and communication modules. The dual 12-bit ADCs monitor temperatures, currents, and user inputs, and timer/PWM blocks drive fans and compressors. With 512 KB flash, one firmware image can serve multiple appliance SKUs with feature flags, reducing firmware variant count. Its industrial temperature behavior and 3.3 V operation simplify power design in mains-powered products.
おすすめ
Medical Monitoring Equipment
Portable and bedside medical monitors use the LPC55S28JBD64K to acquire physiological signals, filter them, and relay data to displays or gateways. The dual 12-bit ADCs sample patient sensors, while DSP instructions implement real-time digital filtering of ECG/spO2 waveforms at 150 MHz. TrustZone supports HIPAA-aligned device security for stored data and wireless transmission, and secure boot ensures only validated clinical firmware runs. The 512 KB flash retains calibration tables and logging buffers, and low-power modes extend battery life in ambulatory designs. Its 3.3 V single-supply operation and small 10x10 mm 64-pin HTQFP footprint fit compact handheld enclosures without forced-air cooling.
おすすめ
Building Automation and Access Control
Access-control panels, door controllers, and HVAC zone controllers leverage the LPC55S28's security features and peripheral mix. Secure boot and TrustZone protect credential databases and prevent unauthorized firmware substitution on networked controllers, an increasing regulatory requirement. Flexcomm UARTs interface to RS-485 reader buses, SPI to memory and displays, and timers to door-relay and siren outputs; dual ADCs monitor tamper loops and power quality. The 150 MHz core runs card-decrypt and match algorithms with low latency for fast user throughput, while 512 KB flash holds extensive user tables. As a drop-in family, designers can scale to LPC55S26 in cost-optimized SKUs on the same PCB.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LPC55S28JBD64K — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LPC55S26JBD64K | LPC5528JBD64K | LPC5526JBD64K | LPC55S16JBD64K |
|---|---|---|---|---|---|
| Package | 64-HTQFP (10x10 mm) EP | 64-HTQFP (10x10 mm) EP - same | 64-HTQFP (10x10 mm) EP - same | 64-HTQFP (10x10 mm) EP - same | 64-HTQFP (10x10 mm) EP - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Core / Clock | Cortex-M33 @ 150 MHz | Cortex-M33 @ 150 MHz | Cortex-M33 @ 150 MHz | Cortex-M33 @ 150 MHz | Cortex-M33 @ 150 MHz |
| Flash | 512 KB | 256 KB | 512 KB | 256 KB | 256 KB |
| SRAM | 104 KB | 96 KB | 104 KB | 96 KB | 96 KB |
| TrustZone / Secure Boot | Yes (S variant) | Yes | No | No | Yes |
| Supply Voltage | 3.3 V (1.8-3.6 V) | 3.3 V (1.8-3.6 V) | 3.3 V (1.8-3.6 V) | 3.3 V (1.8-3.6 V) | 3.3 V (1.8-3.6 V) |
| Lifecycle Status | Active | Active | Active | Active | Active |
主な差別化要因
- Full 512 KB flash with secure boot （vs LPC55S26JBD64K)
- TrustZone security included （vs LPC5528JBD64K)
- Largest flash in the pin-compatible family （vs LPC55S16JBD64K)
設計ノート
The exposed pad on the 64-HTQFP must be soldered to a ground plane array of thermal vias - it is both the primary ground return and the thermal relief path for the 40-nm die. Use 4x4 or larger via farms under the pad with at least 0.3 mm drill holes filled or tented per your assembly process. Keep the SWDIO/SWCLK (PIO0_13/PIO0_14) traces under 10 cm and place a 100-ohm series resistor on SWDIO for hot-probe robustness during production programming.
Decouple each VDD pin with 100 nF X7R capacitors placed within 2 mm of the pin, plus a single 4.7-10 uF bulk capacitor near the supply entry. The analog domain (VDDA/VREFP) should be fed from a filtered or separate LDO rail - sharing digital supply ripple directly degrades the dual 12-bit ADC effective number of bits. Estimated: a 10 kHz-100 MHz ferrite bead with 1 uF + 100 nF on VDDA typically improves ADC noise by 1-2 ENOB relative to a shared rail.
The RESET pin is open-drain with internal pull-up; do not drive it push-pull from a supervisor IC - use an open-drain reset supervisor. For secure products, provision the S-variant key storage before final assembly because the secure boot fuses are one-time programmable and cannot be reworked. When migrating firmware from smaller-flash family members (LPC55S26/LPC55S16), verify linker regions and the flash bank layout, as image placement differs across densities.
USB0_DP/USB0_DM must be routed as a 90-ohm differential pair with length matching within 0.5 mm and no stubs; place the common-mode choke and ESD array within 5 mm of the connector. XTALIN/XTALOUT traces should be kept short (under 5 mm), guarded by ground, and away from switching signals to preserve oscillator startup margin and jitter performance for USB and CAN timing.
コンプライアンス情報
NXP product page lists Environmental Quality information but specific RoHS/REACH declarations were not present in the retrieved web data; consult the NXP LPC55S28JBD64 product page for official certificates.
