MT47H64M16HR-3:G - 1Gb DDR2 SDRAM 333MHz | Micron | 84-FBGA
部品番号: MT47H64M16HR-3:G ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $13.56 | $13.56 |
| 10 | $12.2 | $122.00 |
| 100 | $10.85 | $1,085.00 |
| 500 | $9.75 | $4,875.00 |
| 1,000 | $8.9 | $8,900.00 |
MT47H64M16HR-3:G 概要
DDR2 SDRAM (Double Data Rate 2 Synchronous Dynamic Random-Access Memory) is a volatile memory technology that transfers data on both the rising and falling edges of the clock, doubling throughput versus single-data-rate SDRAM. DDR2 builds on DDR1 with a 4n-bit prefetch architecture, on-die termination (ODT), and a lower 1.8 V core and I/O voltage, which reduces power versus 2.5 V DDR1. In the memory hierarchy, DDR2 SDRAM sits between the memory controller and the DRAM array, providing the working memory for embedded processors, networking equipment, and legacy computing platforms.
Key features of the MT47H64M16HR-3:G include a 1 Gbit density in a 64M x 16 configuration, 333 MHz clock (667 MT/s data rate), 450 ps access time, 1.7 V to 1.9 V supply voltage, and an 84-FBGA (8 x 12.5 mm) package. The device supports programmable CAS latency (CL=3 for the -3 speed grade), burst lengths of 4 or 8, and sequential or interleaved burst types. The differential data strobe (DQS/DQS#) improves signal integrity at high data rates, while the 4n-bit prefetch architecture enables high bandwidth with a modest internal clock.
The MT47H64M16HR-3:G uses Micron's DDR2 process technology with an on-chip DLL for clock synchronization and ODT for impedance matching. The 8-bank architecture allows concurrent operations across banks, improving effective bandwidth. The 1.8 V SSTL_18 I/O interface is compatible with JEDEC-standard DDR2 memory controllers, and the 84-FBGA package provides a compact footprint for space-constrained embedded designs.
Typical applications include embedded computing platforms, industrial control systems, networking and telecom equipment, legacy computing and server memory upgrades, and test and measurement instrumentation. The 1 Gbit density and 333 MHz speed make it suitable for designs requiring moderate memory capacity with DDR2-era memory controllers.
When designing with this device, ensure proper termination and impedance matching on the DDR2 bus, and verify that the memory controller supports the -3 speed grade (CL=3, 333 MHz). The 1.8 V supply must be well-regulated and decoupled to maintain signal integrity.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for the MT47H64M16HR-3:G DDR2 SDRAM.
ドロップイン代替品: MT47H64M16HR-3:G — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
MT47H64M16HR-3 IT:G
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MT47H64M16HR-3:H
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MT47H64M16HR-25E:H
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MT47H64M16HR-3 L:G
✅ ドロップイン📋 参考代替品（カタログ未掲載）
K4T1G164QF-BCF7
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MT47H64M16HR-3:G 最大定格＆電気的特性
| メモリタイプ | DDR2 SDRAM |
| メモリサイズ | 1 Gbit |
| メモリ構成 | 64M x 16 (8 Meg x 16 x 8 banks) |
| Clock Frequency | 333 MHz |
| データレート | 667 MT/s (DDR2-667) |
| Access Time | 450 ps |
| 電源電圧 | 1.7 V to 1.9 V |
| I/O Voltage | 1.8 V (SSTL_18-compatible) |
| インターフェース | Parallel |
| パッケージ | 84-FBGA (8 x 12.5 mm) |
| 実装タイプ | Surface Mount |
| 動作温度 | 0C to +85C (commercial) |
| CASレイテンシ | CL=3 (-3 speed grade) |
| Burst Length | 4 or 8 |
| Data Strobe | Differential (DQS, DQS#) |
| Prefetch Architecture | 4n-bit |
| RoHS ステータス | Compliant |
MT47H64M16HR-3:G ピン構成
| ピン A1 | VDD — Power supply 1.8 V |
| ピン A2 | VSSQ — I/O ground |
| ピン A3 | DQ0 — Data input/output |
| ピン A4 | VDDQ — I/O power supply 1.8 V |
| ピン A5 | DQ2 — Data input/output |
| ピン A6 | VSSQ — I/O ground |
| ピン A7 | DQ4 — Data input/output |
| ピン A8 | VDDQ — I/O power supply 1.8 V |
| ピン A9 | DQ6 — Data input/output |
| ピン B1 | VSS — Ground |
| ピン B2 | DQ1 — Data input/output |
| ピン B3 | VSSQ — I/O ground |
| ピン B4 | DQ3 — Data input/output |
| ピン B5 | VSSQ — I/O ground |
| ピン B6 | DQ5 — Data input/output |
| ピン B7 | VSSQ — I/O ground |
| ピン B8 | DQ7 — Data input/output |
| ピン B9 | VSSQ — I/O ground |
| ピン C1 | VDDQ — I/O power supply 1.8 V |
| ピン C2 | DQS — Data strobe |
| ピン C3 | VSSQ — I/O ground |
| ピン C4 | DQ8 — Data input/output |
| ピン C5 | VDDQ — I/O power supply 1.8 V |
| ピン C6 | DQ10 — Data input/output |
| ピン C7 | VSSQ — I/O ground |
| ピン C8 | DQ12 — Data input/output |
| ピン C9 | VDDQ — I/O power supply 1.8 V |
| ピン D1 | DQS# — Differential data strobe |
| ピン D2 | VSSQ — I/O ground |
| ピン D3 | DQ9 — Data input/output |
| ピン D4 | VSSQ — I/O ground |
| ピン D5 | DQ11 — Data input/output |
| ピン D6 | VSSQ — I/O ground |
| ピン D7 | DQ13 — Data input/output |
| ピン D8 | VSSQ — I/O ground |
| ピン D9 | DQ15 — Data input/output |
| ピン E1 | VDD — Power supply 1.8 V |
| ピン E2 | DQ14 — Data input/output |
| ピン E3 | VDDQ — I/O power supply 1.8 V |
| ピン E4 | LDQS — Lower data strobe |
| ピン E5 | VDDQ — I/O power supply 1.8 V |
| ピン E6 | UDQS — Upper data strobe |
| ピン E7 | VDDQ — I/O power supply 1.8 V |
| ピン E8 | LDQS# — Lower differential data strobe |
| ピン E9 | VDDQ — I/O power supply 1.8 V |
| ピン F1 | VSS — Ground |
| ピン F2 | UDQS# — Upper differential data strobe |
| ピン F3 | VSSQ — I/O ground |
| ピン F4 | VREF — Reference voltage |
| ピン F5 | VSSQ — I/O ground |
| ピン F6 | CK — Clock input |
| ピン F7 | VSSQ — I/O ground |
| ピン F8 | CK# — Differential clock input |
| ピン F9 | VSSQ — I/O ground |
| ピン G1 | VDDQ — I/O power supply 1.8 V |
| ピン G2 | CKE — Clock enable |
| ピン G3 | VDDQ — I/O power supply 1.8 V |
| ピン G4 | A0 — Address input |
| ピン G5 | VDDQ — I/O power supply 1.8 V |
| ピン G6 | A2 — Address input |
| ピン G7 | VDDQ — I/O power supply 1.8 V |
| ピン G8 | A4 — Address input |
| ピン G9 | VDDQ — I/O power supply 1.8 V |
| ピン H1 | VSS — Ground |
| ピン H2 | A1 — Address input |
| ピン H3 | VSSQ — I/O ground |
| ピン H4 | A3 — Address input |
| ピン H5 | VSSQ — I/O ground |
| ピン H6 | A5 — Address input |
| ピン H7 | VSSQ — I/O ground |
| ピン H8 | A6 — Address input |
| ピン H9 | VSSQ — I/O ground |
| ピン J1 | VDD — Power supply 1.8 V |
| ピン J2 | A7 — Address input |
| ピン J3 | VDDQ — I/O power supply 1.8 V |
| ピン J4 | A8 — Address input |
| ピン J5 | VDDQ — I/O power supply 1.8 V |
| ピン J6 | A9 — Address input |
| ピン J7 | VDDQ — I/O power supply 1.8 V |
| ピン J8 | A10 — Address input |
| ピン J9 | VDDQ — I/O power supply 1.8 V |
| ピン K1 | VSS — Ground |
| ピン K2 | BA0 — Bank address input |
| ピン K3 | VSSQ — I/O ground |
| ピン K4 | BA1 — Bank address input |
| ピン K5 | VSSQ — I/O ground |
| ピン K6 | BA2 — Bank address input |
| ピン K7 | VSSQ — I/O ground |
| ピン K8 | A11 — Address input |
| ピン K9 | VSSQ — I/O ground |
| ピン L1 | VDDQ — I/O power supply 1.8 V |
| ピン L2 | A12 — Address input |
| ピン L3 | VDDQ — I/O power supply 1.8 V |
| ピン L4 | CS# — Chip select |
| ピン L5 | VDDQ — I/O power supply 1.8 V |
| ピン L6 | RAS# — Row address strobe |
| ピン L7 | VDDQ — I/O power supply 1.8 V |
| ピン L8 | CAS# — Column address strobe |
| ピン L9 | VDDQ — I/O power supply 1.8 V |
| ピン M1 | VSS — Ground |
| ピン M2 | WE# — Write enable |
| ピン M3 | VSSQ — I/O ground |
| ピン M4 | ODT — On-die termination |
| ピン M5 | VSSQ — I/O ground |
| ピン M6 | NC — Not connected (per datasheet) |
| ピン M7 | VSSQ — I/O ground |
| ピン M8 | NC — Not connected (per datasheet) |
| ピン M9 | VSSQ — I/O ground |
| ピン N1 | VDD — Power supply 1.8 V |
| ピン N2 | VSS — Ground |
| ピン N3 | VDD — Power supply 1.8 V |
| ピン N4 | VSS — Ground |
| ピン N5 | VDD — Power supply 1.8 V |
| ピン N6 | VSS — Ground |
| ピン N7 | VDD — Power supply 1.8 V |
| ピン N8 | VSS — Ground |
| ピン N9 | VDD — Power supply 1.8 V |
主な用途
MT47H64M16HR-3:G の用途: 6 件s: Embedded Computing Platforms, Industrial Control Systems, Networking and Telecom Equipment, Legacy Computing and Server Memory Upgrades, Test and Measurement Instrumentation, Consumer Electronics and Set-Top Boxes.
Embedded Computing Platforms
The MT47H64M16HR-3:G provides 1 Gbit of DDR2 working memory for embedded processors and SoCs that use DDR2 memory controllers. Its 333 MHz clock and 667 MT/s data rate deliver sufficient bandwidth for embedded operating systems, while the 64M x 16 organization matches the 16-bit data bus common on embedded memory controllers. The 1.8 V SSTL_18 interface is directly compatible with JEDEC-standard DDR2 PHYs, and the 84-FBGA package saves board space. Designers should verify that the SoC memory controller supports the -3 speed grade (CL=3) and provide proper ODT and termination on the DDR2 bus to maintain signal integrity at 667 MT/s.
おすすめ
Industrial Control Systems
The MT47H64M16HR-3:G is used in industrial control and automation equipment that requires reliable DDR2 memory for program and data storage. Its 1 Gbit density supports control algorithms, data logging, and HMI buffers, while the 333 MHz speed provides adequate bandwidth for real-time control loops. The commercial temperature grade (0C to +85C) suits controlled factory environments; for extended-temperature installations, the MT47H64M16HR-3 IT:G variant is recommended. The 84-FBGA package and 1.8 V supply simplify integration into existing DDR2-based industrial boards, and the JEDEC-standard interface ensures compatibility with common industrial memory controllers.
おすすめ
Networking and Telecom Equipment
The MT47H64M16HR-3:G provides packet buffer and routing-table memory for networking and telecom equipment such as routers, switches, and gateways. The 667 MT/s data rate supports line-rate packet processing at moderate throughputs, while the 1 Gbit density accommodates forwarding tables and queue buffers. The differential DQS/DQS# strobes improve signal integrity on the DDR2 bus, which is critical in dense networking PCBs with multiple memory devices. The 1.8 V supply and 84-FBGA package align with standard networking board designs. Designers should ensure adequate decoupling and controlled-impedance routing to meet DDR2 timing margins at 333 MHz.
おすすめ
Legacy Computing and Server Memory Upgrades
The MT47H64M16HR-3:G serves as a replacement or upgrade memory device for legacy computing platforms and servers that use DDR2 SDRAM. Its 1 Gbit density and 333 MHz speed match the requirements of DDR2-era memory controllers, enabling repair and maintenance of existing systems. The 64M x 16 organization is compatible with standard DDR2 DIMM and SO-DIMM architectures, and the 84-FBGA package is the industry-standard footprint for DDR2 components. As DDR2 is a legacy technology, availability may be limited; designers should verify stock and consider the MT47H64M16HR-3 IT:G for extended-temperature server environments.
おすすめ
Test and Measurement Instrumentation
The MT47H64M16HR-3:G is used in test and measurement instruments for waveform capture, data buffering, and analysis. The 1 Gbit density provides sufficient storage for high-sample-rate acquisition buffers, while the 667 MT/s data rate supports fast data transfer to the instrument processor. The 1.8 V SSTL_18 interface and differential DQS/DQS# strobes maintain signal integrity in mixed-signal instrument designs. The 84-FBGA package allows compact layouts. Designers should pay attention to power supply decoupling and ground plane integrity to minimize noise coupling into sensitive analog measurement circuits.
おすすめ
Consumer Electronics and Set-Top Boxes
The MT47H64M16HR-3:G provides system memory for consumer electronics such as set-top boxes, digital TVs, and media players that use DDR2 memory. The 1 Gbit density supports operating systems, video buffers, and application data, while the 333 MHz speed handles standard-definition and moderate high-definition video processing. The 1.8 V supply reduces power versus DDR1, and the 84-FBGA package fits compact consumer PCBs. The commercial temperature grade suits indoor consumer environments. Designers should verify the SoC memory controller compatibility and provide adequate thermal relief for the FBGA package in enclosed consumer devices.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MT47H64M16HR-3:G — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MT47H64M16HR-3 IT:G | MT47H64M16HR-3:H | MT47H64M16HR-25E:H | K4T1G164QF-BCF7 |
|---|---|---|---|---|---|
| Package | 84-FBGA (8 x 12.5 mm) | 84-FBGA (8 x 12.5 mm) - same | 84-FBGA (8 x 12.5 mm) - same | 84-FBGA (8 x 12.5 mm) - same | FBGA-84 - same |
| Brand | Micron Technology | Micron Technology | Micron Technology | Micron Technology | Samsung Electronics |
| Memory Size | 1 Gbit | 1 Gbit | 1 Gbit | 1 Gbit | 1 Gbit |
| Organization | 64M x 16 | 64M x 16 | 64M x 16 | 64M x 16 | 64M x 16 |
| Clock Frequency | 333 MHz | 333 MHz | 333 MHz | 400 MHz | 333 MHz |
| Supply Voltage | 1.7 V to 1.9 V | 1.7 V to 1.9 V | 1.7 V to 1.9 V | 1.7 V to 1.9 V | 1.7 V to 1.9 V |
| Operating Temperature | 0C to +85C (commercial) | -40C to +85C (industrial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) |
| CAS Latency | CL=3 | CL=3 | CL=3 | CL=4 | CL=3 |
| Access Time | 450 ps | 450 ps | 450 ps | 400 ps | 450 ps |
| Data Rate | 667 MT/s | 667 MT/s | 667 MT/s | 800 MT/s | 667 MT/s |
主な差別化要因
- Commercial temperature grade at lower cost （vs MT47H64M16HR-3 IT:G)
- Standard 333 MHz DDR2-667 speed grade （vs MT47H64M16HR-25E:H)
- Micron DDR2 reliability and JEDEC compliance （vs K4T1G164QF-BCF7)
設計ノート
Route DDR2 data and strobe traces with controlled 50 ohm single-ended impedance and match trace lengths within each byte lane to within +/- 5 mm. The differential DQS/DQS# pairs should be routed as 100 ohm differential pairs with matched intra-pair skew. Keep the DDR2 bus away from sensitive analog or RF traces to avoid coupling. Use a solid ground plane under the DDR2 bus for return current control.
Decouple the 1.8 V VDD and VDDQ supplies with 0.1 uF ceramic capacitors placed as close as possible to each power ball, plus bulk 10 uF capacitors per device. The VREF pin requires a stable reference, typically generated by a resistor divider from VDDQ with a 0.1 uF bypass capacitor. Estimated: at 667 MT/s, the device draws approximately 200-300 mA depending on access patterns; size the regulator accordingly.
Do not exceed the 1.9 V maximum supply voltage, as this can damage the DDR2 SDRAM. Verify that the memory controller supports the -3 speed grade (CL=3, 333 MHz) before designing in this part. The ODT (on-die termination) pin must be properly controlled by the memory controller; incorrect ODT settings cause signal integrity failures at 667 MT/s. For extended-temperature applications, use the MT47H64M16HR-3 IT:G variant.
コンプライアンス情報
RoHS compliant per distributor data. Not AEC-Q100 qualified; commercial and industrial temperature grades available. Halogen-free status not confirmed in provided data.
