XCF02SVOG20C - 2Mb Platform Flash PROM for FPGA Config | AMD/Xilinx
部品番号: XCF02SVOG20C ⚠ ラストタイムバイ| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $34.85 | $34.85 |
| 10 | $31.2 | $312.00 |
| 100 | $26.5 | $2,650.00 |
| 500 | $22.1 | $11,050.00 |
| 1,000 | $19.4 | $19,400.00 |
XCF02SVOG20C 概要
A Platform Flash PROM is a non-volatile configuration memory IC purpose-built to hold FPGA bitstreams outside the FPGA fabric. In the broader component taxonomy it belongs to NOR Flash -> non-volatile memory -> memory IC -> integrated circuit. Unlike discrete SPI Flash or parallel boot memories, Platform Flash devices integrate the JTAG programming chain, FPGA hand-shake pins (CCLK, DONE, INIT, PROGRAM) and a cascade-ready architecture, so a single IC can boot a Xilinx Spartan or Virtex FPGA without external glue logic.
Key features include 2Mb density in a compact 20-TSSOP footprint, low-power advanced CMOS NOR Flash process, cascadable bitstream expansion for larger FPGAs, and JTAG boundary-scan with 3-stage registers per bidirectional pin. The industrial temperature grade (VOG suffix = -40C to +85C) and lead-free TSSOP-20 packaging make XCF02SVOG20C a mainstream choice for cost-sensitive Spartan-3 / Spartan-3A designs. The OG20C suffix denotes a TSSOP-20 package supplied in tube.
From a system-level perspective, XCF02SVOG20C connects directly to the FPGA's configuration mode pins (M[2:0] = 010 selects Master Serial mode). On power-up the PROM serial-clocks the bitstream via the FPGA CCLK pin, the FPGA drives DONE high, and the PROM tri-states its data line. The bidirectional pins are observable and controllable through the JTAG boundary-scan register, which speeds prototype debug and board-level interconnect testing. The NOR Flash cell array provides fast read access with low standby current.
Typical applications include Spartan-3, Spartan-3A, Spartan-3E, and Virtex-II configuration storage, industrial control boards, factory automation equipment, medical imaging FPGA platforms, and any design that requires a small-footprint non-volatile boot source for Xilinx FPGAs. Two or more XCF02S PROMs can be cascaded to support larger bitstreams for higher-density FPGAs.
When designing with XCF02SVOG20C, confirm the FPGA bitstream does not exceed 2Mb before committing the BOM. AMD PCN XCN20013 (2026) confirms there is NO direct drop-in replacement for XCF02SVOG20C; design teams are advised to forecast demand and place final orders before key dates in Appendix A of that PCN, or migrate the FPGA to a newer family that boots from internal SPI Flash.
This page synthesizes distributor pricing, lifecycle risk context (XCN20013), drop-in alternative scarcity, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: XCF02SVOG20C — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: XCF02SVOG20C （同一形状・フットプリント） — 相違点: Memory Type, Supply Voltage, Bits per Word, Density, Logic Family.
クイック比較ツール — 並列比較する代替部品を選択:
XCF04SVOG20C
✅ ドロップイン✓ 在庫あり
$36.9 / 個
データシートを見る →XCF01SVOG20C
✅ ドロップイン📋 参考代替品（カタログ未掲載）
XCF02SVOG20C 最大定格＆電気的特性
| メモリタイプ | NOR Flash PROM (in-system programmable) |
| Density | 2 Mbit (2,097,152 bits) |
| メモリ構成 | 2,000K x 1 bit |
| Bits per Word | 1 bit |
| 電源電圧 | 3.0 V to 3.6 V |
| Logic Family | CMOS (low-power advanced NOR Flash process) |
| Programmable Type | In System Programmable (ISP) |
| Programming Interface | IEEE 1149.1 / IEEE 1532 JTAG |
| Endurance | 20,000 program/erase cycles (guaranteed) |
| Data Retention | 20 years minimum |
| パッケージ / ケース | 20-TSSOP (0.173 inch / 4.40 mm body width) |
| Pins | 20 |
| 動作温度 | -40C to +85C (VOG = industrial) |
| Packaging | Tube (OG20C) |
| Lead Status | Lead Free |
| Cascade Support | Yes (multi-PROM bitstream expansion) |
| RoHS ステータス | Compliant |
XCF02SVOG20C ピン構成
| ピン 1 | VCC — 3.3V supply voltage |
| ピン 2 | GND — Ground |
| ピン 3 | TDI — JTAG Test Data In (IEEE 1149.1) |
| ピン 4 | TMS — JTAG Test Mode Select |
| ピン 5 | TCK — JTAG Test Clock |
| ピン 6 | TDO — JTAG Test Data Out |
| ピン 7 | NC — Not connected (per datasheet) |
| ピン 8 | INIT — FPGA INIT signal / open-drain bidirectional |
| ピン 9 | DONE — FPGA DONE indicator (open-drain) |
| ピン 10 | PROGRAM — FPGA PROGRAM active-low input |
| ピン 11 | CCLK — Configuration clock output to FPGA |
| ピン 12 | CCFK — Configuration clock feedback from FPGA |
| ピン 13 | OE/RESET — Output Enable / Reset dual-mode |
| ピン 14 | CF — Configuration Flash data output (Master Serial) |
| ピン 15 | CFI — Cascade configuration input from upstream PROM |
| ピン 16 | CFO — Cascade configuration output to downstream PROM/FPGA |
| ピン 17 | NC — Not connected (per datasheet) |
| ピン 18 | NC — Not connected (per datasheet) |
| ピン 19 | NC — Not connected (per datasheet) |
| ピン 20 | VCC — 3.3V supply voltage (second VCC pin) |
主な用途
XCF02SVOG20C の用途: 6 件s: Spartan-3 / Spartan-3A FPGA Configuration, Industrial Control & Factory Automation, Medical Imaging FPGA Platforms, Aerospace & Defense Avionics Subsystems, Legacy Networking Equipment, Test & Measurement Instrumentation.
Spartan-3 / Spartan-3A FPGA Configuration
The XCF02SVOG20C provides Master-Serial configuration storage for Xilinx Spartan-3, Spartan-3A and Spartan-3E FPGAs whose compressed bitstreams fit within 2 Mb. With 2,097,152 bits of NOR Flash and a guaranteed 20,000 program/erase cycle endurance, it is sized for the typical Spartan-3 configuration payload. The 3.0V-3.6V supply matches the FPGA's VCCO_2 bank and the JTAG chain allows in-system reprogramming during prototype bring-up without removing the PROM. According to AMD datasheet DS123, this device is the canonical boot source for cost-sensitive Spartan-3 designs. Note: per XCN20013 the part is on last-time-buy.
おすすめ
Industrial Control & Factory Automation
XCF02SVOG20C's industrial temperature grade (-40C to +85C), 20-year data retention, and lead-free TSSOP-20 package suit it for factory-floor controllers, PLC I/O modules, and motor-drive subsystems built on Spartan-3A. The JTAG boundary-scan with three register stages per bidirectional pin accelerates board interconnect testing on populated PCBs. According to AMD PCN XCN20013, customers building new industrial platforms should forecast demand and place final orders before the Appendix A key dates. For new designs, AMD recommends Spartan-7 with internal SPI Flash.
おすすめ
Medical Imaging FPGA Platforms
Medical imaging systems (ultrasound front-ends, portable X-ray controllers, patient monitors) often rely on Xilinx Spartan-3A FPGAs booted from XCF02SVOG20C. The 2 Mb storage is sufficient for image-pipeline bitstreams, while the 20-year retention and TSSOP-20 footprint reduce BOM height in compact handheld enclosures. The JTAG chain supports IEC 60601-1 compliant in-system firmware updates during field servicing. Reference designs from AMD pair this PROM with Spartan-3A DSP daughtercards used in mid-tier ultrasound beamformers.
おすすめ
Aerospace & Defense Avionics Subsystems
Avionics subsystems and UAV flight controllers historically use XCF02SVOG20C to boot Spartan-3 / Virtex-II FPGAs due to the industrial temperature range, 20-year retention, and radiation-tolerant CMOS process. The 20-TSSOP package is drop-in compatible with prior-generation designs. Cascade mode supports larger Virtex-II bitstreams. According to AMD PCN XCN20013, defense customers with long-lived platforms must place final orders before the Appendix A key dates; migration to radiation-hardened FPGAs with internal Flash is recommended for next-generation designs.
おすすめ
Legacy Networking Equipment
Legacy networking line cards and router switch fabrics built on Xilinx Virtex-II or Spartan-3 FPGAs use XCF02SVOG20C as the boot PROM. The 2 Mb capacity is well-matched to compact packet-processing pipelines, and JTAG ISP allows field firmware updates without board removal. According to AMD datasheet DS123, the JTAG chain (TDI/TDO/TCK/TMS) supports boundary-scan interconnect test for high-layer-count backplanes. Per XCN20013, network OEMs maintaining legacy platforms must secure inventory now.
おすすめ
Test & Measurement Instrumentation
Bench-top oscilloscopes, logic analyzers, and protocol analyzers built on Spartan-3A use XCF02SVOG20C as a low-cost boot PROM with JTAG-driven field firmware updates. The industrial -40C to +85C range supports both lab and field environments, and the 20-year data retention ensures long-term calibration integrity. Reference designs pair the PROM with Spartan-3A + high-speed ADC front-ends. According to AMD, JTAG boundary-scan accelerates manufacturing test of complex mixed-signal PCBs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: XCF02SVOG20C — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | XCF04SVOG20C | XCF01SVOG20C | XCF08PVOG48C |
|---|---|---|---|---|
| Brand | Xilinx | Xilinx | Xilinx | Xilinx |
| Package | TSSOP-20 | TSSOP-20 (same) | TSSOP-20 (same) | TSSOP-48 (NOT pin-compatible) |
| Density | 2 Mbit | 4 Mbit (+100%) | 1 Mbit (-50%) | 8 Mbit (+300%) |
| Supply Voltage | 3.0V to 3.6V | 3.0V to 3.6V | 3.0V to 3.6V | 1.6V to 2.0V |
| Configuration Mode | Master Serial | Master Serial | Master Serial | Master Serial |
| JTAG ISP | Yes (IEEE 1149.1/1532) | Yes (IEEE 1149.1/1532) | Yes (IEEE 1149.1/1532) | Yes (IEEE 1149.1/1532) |
| Endurance | 20,000 cycles | 20,000 cycles | 20,000 cycles | 20,000 cycles |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Lifecycle Status | Last-Time-Buy (XCN20013) | Last-Time-Buy | Last-Time-Buy | Active |
主な差別化要因
- Canonical 2Mb Master-Serial configuration PROM with 20,000 cycle endurance （vs XCF04SVOG20C)
- Pin-compatible with XCF01S and XCF04S family members （vs M25P40-VMN6TP)
- Industrial -40C to +85C temperature range （vs XCF08PVOG48C)
設計ノート
Per AMD PCN XCN20013, XCF02SVOG20C has NO direct drop-in replacement. Design teams using this PROM in Spartan-3 / Spartan-3A platforms must forecast demand (see Appendix A of XCN20013) and place final orders before the key dates. For new designs, AMD recommends migrating to Spartan-6 / Spartan-7 FPGAs that boot from internal SPI Flash - this eliminates the external PROM entirely. Do not assume this part will be available for production beyond the last-time-buy window.
Place 0.1uF and 10uF decoupling capacitors as close as possible to both VCC pins (1 and 20) of XCF02SVOG20C. Keep the CCLK trace short and impedance-controlled to the FPGA CCLK input; long clock traces cause configuration errors. Route JTAG signals TDI/TMS/TCK/TDO in a single daisy-chain bus with the FPGA - the PROM is the first device in the chain when both are JTAG-scannable. Avoid stubs on CF (configuration data) line.
Estimated bitstream fit check: before committing to XCF02SVOG20C, confirm the target FPGA bitstream is <= 2,097,152 bits after compression. Spartan-3 XC3S400 bitstreams are typically 1.6-1.9 Mbit compressed; Spartan-3A XC3S700A may exceed 2 Mbit. If the bitstream is borderline, choose XCF04SVOG20C (4 Mbit, same footprint) instead. Verify by generating the .bit file in ISE Impact and checking the bit count.
The CF (configuration flash data) line is a slow serial signal but is sensitive to noise on long PCB traces. Keep the CF trace short (< 50 mm), avoid running parallel to switching power or high-speed signals, and add a 10k pull-up to VCC if the FPGA mode is Master Serial. CCLK should be the only clock source during configuration - the FPGA returns CCFK to the PROM, so route these as a differential pair on the schematic.
コンプライアンス情報
RoHS compliant and lead-free per AMD/Xilinx product page and DigiKey listing. Not AEC-Q100 qualified - this is an FPGA configuration PROM for industrial/commercial FPGA platforms, not an automotive-grade IC. Last-time-buy per AMD PCN XCN20013.
