ADC/DAC
제품 (2518)
LTC2142IUP-12 - 12-Bit 65Msps Dual ADC | Analog Devices
The Analog Devices LTC2142IUP-12 is a 12-bit, 65 Msps, dual-channel, simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm, UPF) exposed-pad package. Designed for digitizing high-frequency, wide-dynamic-range signals, the device combines two matched 12-bit ADC cores with on-chip sample-and-hold and a common reference clock to maintain tight inter-channel phase alignment, making it suitable for diversity receivers and I/Q digitizers where channel-to-channel skew would corrupt image rejection. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time analog voltages into discrete digital codes at a defined sample rate. High-speed pipelined ADCs use a cascade of low-resolution stages to achieve the best trade-off between speed, resolution, and power; the LTC2142-12 family operates between 25 Msps and 65 Msps to cover a range of communications and instrumentation bandwidths. The LTC2142IUP-12 sits in the hierarchy: pipelined ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor. Key performance specifications include 70.8 dB SNR, 89 dB spurious-free dynamic range (SFDR), ±0.3 LSB INL (typical), ±0.1 LSB DNL (typical), and no missing codes over the industrial temperature range. Transition noise is specified at 0.3 LSB RMS. The output data interface is programmable between full-rate CMOS, double-data-rate CMOS, and double-data-rate LVDS via a parallel or simple SPI-mode serial configuration register. Typical applications include cellular base-station diversity receivers, multi-antenna software-defined radio (SDR) front-ends, medical ultrasound beamformers, and high-speed instrumentation digitizers. The separate output supply (OVDD) lets the CMOS swing range between 1.2 V and 1.8 V, which allows direct connection to low-voltage FPGAs without level shifters. The operating modes of the LTC2142IUP-12 - including output mode, input range, and power-down - are programmed through either a parallel mode-select pin set or the serial interface for finer control. Designers should follow Analog Devices reference layouts for the 9 mm x 9 mm QFN exposed pad to keep the thermal resistance at the published value. When designing with the LTC2142IUP-12, decouple AVDD and OVDD planes separately and route analog inputs as 50 Ω-1 controlled-impedance differential lines terminated at the ADC inputs to preserve the published SNR and SFDR at full input frequency. This page synthesizes distributor pricing across five channels (DigiKey, Mouser, Octopart, Vyrian, and DigChip) together with same-package pin-compatible variants and practical PCB-layout guidance that is not aggregated on any individual distributor listing.
LTC2142IUP-14 - 14-Bit 65Msps Low-Power Dual ADC | ADI
The Analog Devices LTC2142IUP-14 is a 14-bit, 65 Msps low-power dual-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 64-lead 9x9 mm QFN package (UP suffix). The part integrates two matched 14-bit ADC cores that sample on the same clock edge, eliminating inter-channel skew in time-interleaved or I/Q signal chains. What is a dual simultaneous-sampling ADC? A dual ADC is a single integrated circuit containing two matched A/D converter channels that sample their analog inputs at the exact same instant, sharing a common clock. Within the broader signal chain hierarchy, the LTC2142IUP-14 sits inside the data-converter (ADC) class, which is itself a sub-category of data-acquisition ICs, mixed-signal semiconductors, and ultimately integrated circuits. Each converter is preceded by an input track-and-hold and feeds a common reference, allowing direct-IF sampling and quadrature demodulation in communications receivers. Key headline parameters include 14-bit resolution, 65 Msps conversion rate per channel, 73.1 dB SNR, 90 dB SFDR, and a low 100 mW per-channel power dissipation. The device accepts single-ended or differential analog inputs with an input range of 1 Vp-p to 2 Vp-p (set by the MODE pin) and operates from a single 1.8 V analog supply. Digital outputs are LVDS-compatible, easing routing to an FPGA or ASIC across a noisy PCB. A flexible parallel or serial programming interface configures output format, gain, and test patterns. Architecturally, the converter uses a multi-stage pipelined core with proprietary linearization techniques that preserve linearity at high input frequencies, with a typical -3 dB analog input bandwidth of 125 MHz that comfortably exceeds the 65 Msps Nyquist requirement. This makes the part well suited to undersampling intermediate-frequency (IF) signals in wireless infrastructure. Typical applications include 3G/4G cellular base-station receivers, communications imaging, portable instrumentation, ultrasound scanners, and multi-channel data-acquisition cards where channel-to-channel phase coherence is mandatory. Designers frequently pair the LTC2142IUP-14 with low-noise LDOs such as the LT1761 and clock-distribution ICs from the AD951x family. When laying out the PCB, place the analog inputs as close to the ADC pins as possible, use a solid ground plane under the package, and route LVDS outputs with controlled 100 ohm differential impedance. The exposed paddle (EP) must be soldered to a low-impedance ground pad to provide both the electrical ground return and the primary thermal path for the 100 mW internal dissipation. This page synthesizes distributor pricing, package-faithful drop-in alternatives, and applied design notes that go beyond the manufacturer datasheet. It is intended as an engineering-grade reference for BOM managers and hardware designers evaluating the LTC2142IUP-14 for new designs or service replacements.
LTC2143CUP-12 - 12-Bit 80Msps Dual ADC | Analog Devices
The Analog Devices LTC2143CUP-12 is a 12-bit, 80 Msps, dual-channel, simultaneous-sampling pipelined analog-to-digital converter (ADC) in a 64-pin QFN (9x9 mm) package. It operates from a single 1.8 V supply and integrates two matched ADC cores, on-chip reference, and configurable CMOS/LVDS output modes for direct connection to FPGAs and DSPs. An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous analog waveforms into discrete digital codes for processing by microcontrollers, DSPs, or FPGAs. The pipelined ADC architecture — the hypernym hierarchy of which is: ADC -> data converter -> mixed-signal IC -> semiconductor — is the industry-preferred topology for sample rates from ~10 Msps to >500 Msps because it balances high speed, low power, and small die area. Dual-channel simultaneous-sampling ADCs such as the LTC2143-12 are critical for communications, radar, and I/Q demodulation where two related analog signals must be captured at the exact same instant. Key specifications of the LTC2143CUP-12 include: 12-bit resolution, 80 Msps sample rate, 70.1 dB SNR, 88 dB SFDR, ±0.4 LSB INL (typical), 1.8 V analog/digital supply, and selectable full-scale input range of 1 Vp-p or 2 Vp-p. The serial LVDS output interface (DDR LVDS) supports up to 80 Msps with reduced pin count and excellent common-mode noise rejection. Power consumption is approximately 125 mW per channel at full speed, which is class-leading for the 80 Msps / 12-bit category. Architecturally, the LTC2143-12 uses two interleaved 12-bit pipelined cores with a shared bandgap reference, an on-chip sample-and-hold amplifier, and a digital error-correction block. A self-calibration routine on power-up corrects capacitor mismatch and comparator offset, enabling the 88 dB SFDR performance without external calibration. The inputs are designed for differential drive to maximize even-order harmonic rejection; on-chip common-mode voltage generation simplifies AC-coupling with most modern op-amp drivers. Typical applications for the LTC2143CUP-12 include multi-carrier GSM/EDGE and LTE base-station receivers, diversity radio IF digitization, radar and lidar front-ends, high-speed data acquisition systems, medical imaging (ultrasound beamformers), and communications test equipment. The wide input bandwidth (~750 MHz) also suits the digitizing of IF signals up to ~200 MHz without additional downconversion. When designing with the LTC2143CUP-12, the most important layout consideration is the input network: use a transformer or differential op-amp driver such as the AD8138 with a 25 Ω series resistor at each analog input pin, and place the anti-aliasing RC network as close to the ADC as possible. Decouple the 1.8 V supply with 0.1 µF and 10 µF ceramic capacitors on every supply pin, and keep the LVDS output traces length-matched to within 5 mm to preserve DDR timing margins. This page synthesizes distributor pricing, drop-in same-package alternatives, and design notes that go beyond the manufacturer datasheet — including a parameter-by-parameter comparison table and an explicit selection guide for choosing the LTC2143CUP-12 versus faster or higher-resolution members of the LTC2145-12 / LTC2144-12 / LTC2143-12 family.
LTC2143CUP-14 - 14-Bit 80Msps Dual ADC | Analog Devices
The Analog Devices LTC2143CUP-14 is a 14-bit, 80 Msps, low-power dual pipelined analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9) exposed-pad package. The two simultaneously-sampling differential input channels make it well suited for digitizing I/Q baseband, communications IF strips, and multi-channel instrumentation front ends where channel-to-channel phase coherence matters. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog voltage and produces a discrete digital code representing its amplitude. Pipelined ADCs achieve a favorable trade-off between sample rate (tens to hundreds of MSPS) and resolution (10-16 bits) by cascading multiple low-resolution stages with inter-stage residue amplification; they are the dominant architecture in communications, imaging, and test-and-measurement front ends. Dual-channel pipelined ADCs such as the LTC2143CUP-14 simultaneously quantize two analog inputs so downstream DSP can recover quadrature relationships, multi-antenna phase, or multi-sensor time correlation. Key specifications include ±1 LSB typical INL, ±0.3 LSB typical DNL with no missing codes over the full temperature range, 1.2 LSB RMS transition noise, and flexible digital outputs supporting full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS. A separate output supply pin lets the CMOS swing range from 1.8 V to 3.3 V independent of the analog 1.8 V core rail, simplifying interface to FPGAs and ASICs on different I/O voltage domains. Typical applications include cellular base-station receivers, software-defined radio (SDR) front ends, multi-channel data acquisition cards, medical ultrasound beamformers, and portable battery-powered instrumentation. The 64-QFN (9x9) exposed pad keeps the package compact while providing a low thermal-resistance path that is essential for the multilayer board ground-plane layout recommended by the manufacturer datasheet. A clean unbroken ground plane in the layer immediately beneath the ADC is required to achieve the published SNR/SFDR performance. A primary design consideration is bypassing the analog and digital rails with low-ESR ceramic capacitors placed within 2 mm of each supply pin and tying the exposed pad to a solid ground pour with at least 16 thermal vias. The internal reference can be disabled in favor of an external reference when tighter gain error or channel matching is required across multiple ADCs.
LTC2143IUP-12 - 12-Bit 80Msps Dual ADC, 64-QFN | Analog Devices
The Analog Devices LTC2143IUP-12 is a 12-bit, 80 Msps, dual-channel, low-power pipelined analog-to-digital converter (ADC) housed in a 64-pin QFN (UP, 9x9 mm) package with exposed pad. The part is specified for the industrial temperature range (-40C to +85C) and operates from a single 1.8 V supply, drawing approximately 100 mW per channel at full sample rate. Per the LTC2145-12/LTC2144-12/LTC2143-12 family datasheet, the device features 70.6 dB SNR and 89 dB spurious-free dynamic range, with simultaneous sampling of two differential analog input channels. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts real-world analog waveforms into discrete digital codes for processing, storage, or transmission. The pipelined ADC architecture — of which the LTC2143IUP-12 is an instance — uses multiple low-resolution stages (typically 1.5 bits/stage) with inter-stage residue amplifiers to achieve high sampling rates at moderate resolution. Pipelined ADCs sit within the broader hierarchy: ADC → data converter → mixed-signal IC → semiconductor. They are the workhorse choice for communications, imaging, and test-and-measurement systems that require multi-MHz input bandwidth and 10-14 bits of resolution. The LTC2143IUP-12 supports input bandwidths up to approximately 750 MHz, allowing it to under-sample IF signals in communications receivers. Internal voltage reference, programmable digital output timing, and flexible LVDS/CMOS output modes simplify board-level integration. The dual, matched channels eliminate skew between ADC paths in MIMO or diversity receivers, while per-channel gain and offset adjustment registers help correct channel-to-channel mismatches at the system level. The 1.8 V single-supply architecture plus low power (about 100 mW per channel at 80 Msps) makes the LTC2143IUP-12 well suited for portable and thermally-constrained instrumentation. Optional LVDS outputs minimize digital switching noise on the board, which is critical when the analog inputs are at the millivolt level. Programmable full-scale input range (1 Vpp or 2 Vpp differential) gives designers headroom when interfacing with a variety of front-end amplifiers and anti-alias filters. Typical applications include cellular base-station receivers, software-defined radio (SDR) platforms, medical imaging front ends, portable test and measurement equipment, and multi-channel data acquisition systems. The wide input bandwidth also suits digital oscilloscopes and spectrum analyzer front ends. When designing with the LTC2143IUP-12, place the analog input traces as 100-ohm differential pairs with a grounded coplanar-waveguide structure, and keep the exposed pad soldered to a continuous ground plane for thermal dissipation and low-impedance return. Use the internal reference by default and decouple AVDD/DVDD/OVRDV with 0.1 uF and 10 uF ceramic capacitors as close to the pins as possible. This page synthesizes DigiKey and Mouser stock/pricing, drop-in pin-compatible alternatives in the same 64-QFN footprint, and practical design notes drawn from the Analog Devices datasheet — information that you will not find on any single distributor page.
LTC2144CUP-14 - 14-Bit 105Msps Dual ADC | Analog Devices
The Analog Devices LTC2144CUP-14 is a 14-bit, 105 Msps dual-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9 mm) package with exposed pad, designed for digitizing high-frequency, wide-dynamic-range signals in communications and imaging systems. Key specifications per the Analog Devices datasheet include a 14-bit resolution, 105 Msps sample rate per channel, two synchronized sample-and-hold inputs for simultaneous acquisition, and a low-power CMOS architecture intended for portable and high-density multi-channel designs. What is a simultaneous-sampling ADC? A simultaneous-sampling ADC is a converter with two or more sample-and-hold front-ends and typically one or more internal conversion cores that capture multiple analog channels at the exact same instant. Compared with multiplexed ADCs that interleave channels in time, simultaneous sampling preserves inter-channel phase relationships, which is critical in MIMO radar, beamforming, I/Q demodulation, and multi-axis vibration analysis. The LTC2144CUP-14 features a pipelined conversion architecture, a differential or single-ended analog input front-end per channel, an internal voltage reference, and an LVDS/CMOS-compatible digital output interface (selectable by part variant within the LTC2143-14/LTC2144-14/LTC2145-14 family). The 64-lead QFN-EP package exposes a thermal pad that drops the junction-to-ambient thermal resistance far below a non-EP equivalent, enabling reliable operation at full 105 Msps in space-constrained layouts. Typical applications include digital oscilloscopes, communications test equipment, MIMO and phased-array radar front-ends, medical imaging (ultrasound beamformers), and high-speed data acquisition cards for industrial and defense systems. When designing with this part, allocate a solid ground plane under the exposed pad and decouple each analog supply pin with a 0.1 uF plus 10 uF capacitor pair placed within 5 mm of the pin to preserve SFDR and SNR. This page synthesizes distributor pricing, drop-in alternatives from the LTC2143/LTC2144/LTC2145 family, and practical design notes not found in the manufacturer datasheet alone.
LTC2144IUP-12 - 12-Bit 105Msps Dual ADC | Analog Devices
The Analog Devices LTC2144IUP-12 is a 12-bit, 105 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9 mm) package with an exposed pad. It is part of the LTC2145-12/LTC2144-12/LTC2143-12 family that delivers 70.6 dB SNR and 89 dB spurious-free dynamic range (SFDR) for digitizing high-frequency, wide dynamic range signals. Ultralow 0.08 ps RMS jitter allows IF undersampling with excellent noise performance. An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes. Pipelined ADCs use a multi-stage architecture to achieve high sample rates (tens to hundreds of Msps) while keeping per-stage hardware compact; dual simultaneous-sampling ADCs capture two channels at exactly the same instant, eliminating channel-to-channel skew in I/Q or diversity receivers. Within the power management and data-converter taxonomy, the LTC2144IUP-12 belongs to high-speed pipelined ADCs -> data converters -> mixed-signal ICs -> integrated circuits. Key features of this part include 105 Msps per channel sample rate, 12-bit resolution, 70.6 dB SNR, 89 dB SFDR, 0.08 ps RMS aperture jitter, and a parallel CMOS/LVDS output interface selectable per channel. The 64-QFN (UP) exposed-pad package provides low thermal resistance (~28 C/W theta_JC via the pad), enabling operation across the industrial -40C to +85C temperature range. The pipelined architecture uses 12 internal stages with per-stage flash sub-ADC and MDAC residue amplification; sample-and-hold is on-chip and front-end differential, supporting 1 Vp-p to 2 Vp-p full-scale inputs. A separate output supply (OVDD) lets the digital outputs drive 1.8V to 3.3V logic while the analog core runs from 1.8V. Typical applications include communications receivers, cellular base-station digitizers, radar/sonar signal chains, medical imaging front-ends, and portable test instrumentation. Designers commonly pair it with the AD8138 differential driver at the input and an FPGA for the parallel data capture. Design trade-off: at 105 Msps with 1.8V analog supply, expect roughly 100 mW per channel dissipation. Use the exposed pad with a continuous ground plane and bypass AVDD with 10 uF + 0.1 uF ceramic as close as possible to each pin pair. This page synthesizes distributor pricing, drop-in same-package alternatives, and application-specific design notes not found in the manufacturer datasheet alone.
LTC2144IUP-14 - 14-Bit, 105Msps Dual ADC | Analog Devices
The Analog Devices LTC2144IUP-14 is a 14-bit, 105 Msps low-power dual simultaneous-sampling analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) exposed-pad package. Each of the two integrated channels samples at up to 105 MSPS with pipelined architecture, and the device draws only 312 mW total (approximately 156 mW per channel) from a single 1.8 V supply, with an optional 2.5 V drive for the LVDS/CMOS outputs. What is a dual pipelined ADC? A dual pipelined ADC is an analog-to-digital converter that integrates two independent sample-and-hold front-ends followed by multi-stage switched-capacitor pipeline stages. The architecture enables two channels to be digitized simultaneously, which is critical for applications such as MIMO wireless transceivers, diversity radar, and quadrature (I/Q) signal processing where phase coherence between channels determines system performance. Key features include 73.4 dB SNR and 90 dB SFDR at 70 MHz input, an internal transparent dither circuit that improves SFDR at low input frequencies, and a serial SPI port for mode configuration. The LTC2144-14 family supports CMOS, DDR CMOS, or DDR LVDS output modes, allowing flexible interface to FPGAs and ASICs. A built-in clock duty-cycle stabilizer relaxes PCB clock-routing constraints. The LTC2144IUP-14 is engineered for high-channel-count multi-board systems: a multi-lane serial output mode produces a single-lane serial data stream per channel, reducing FPGA pin count. Internal bandgap reference and proprietary pipeline design eliminate the need for external reference decoupling in most applications, reducing BOM cost. Pin compatibility with the 12-bit LTC2144-12 and 14-bit LTC2143-14 (80 MSPS) variants provides an easy resolution/sample-rate upgrade path within the same QFN-64 footprint. Typical applications include communications basestations (MIMO LTE/WCDMA diversity receivers), handheld portable instrumentation, medical imaging (ultrasound beamforming front-ends), and defense electronics such as phased-array radar digitizers. The industrial temperature range (-40C to +85C) supports outdoor and uncontrolled-environment deployments. When designing with this device, provide a clean low-noise ground plane directly under the exposed pad, route the 105 MHz encode clock as a 50 ohm controlled-impedance trace, and bypass each analog supply pin with a 0.1 uF X7R ceramic capacitor within 3 mm of the pin. The IUP suffix denotes the industrial-grade (-40C to +85C) package. This page synthesizes distributor pricing, drop-in alternatives, and practical layout guidance not found in the bare datasheet, with cross-references to companion Linear Technology ADC families.
LTC2145CUP-12 - 12-Bit 125Msps Dual ADC, 1.8V, 64-QFN | Analog Devices
The Analog Devices LTC2145CUP-12 is a 12-bit, 125 Msps, dual-channel, low-power analog-to-digital converter housed in a 64-lead (9 mm x 9 mm) QFN-EP package with exposed thermal pad. The device operates from a single 1.8 V analog supply, integrates two simultaneous-sampling pipelined ADC channels, and supports a separate digital I/O supply that can range from 1.2 V to 1.8 V for flexible logic interfacing. The C-grade commercial temperature range spans 0 °C to +70 °C. A pipelined ADC is a high-speed analog-to-digital converter architecture that uses multiple cascaded low-resolution stages, each producing a partial conversion with its own sample-and-hold, sub-ADC, and DAC. The pipeline architecture enables high conversion rates (tens to hundreds of Msps) at moderate power dissipation, making pipelined ADCs the workhorse of communications, radar, instrumentation, and imaging front-ends. The LTC2145CUP-12 belongs to the converter -> ADC -> high-speed ADC -> pipelined ADC hierarchy within Analog Devices' data-converter portfolio. Key specifications include ±0.3 LSB typical INL, ±0.1 LSB typical DNL with no missing codes over temperature, 0.3 LSB RMS transition noise, 70.6 dB SNR, 89 dB spurious-free dynamic range (SFDR), and 0.08 ps RMS ultra-low aperture jitter. Differential analog inputs are required to achieve the rated AC performance. The outputs are software-configurable as full-rate CMOS, double-data-rate (DDR) CMOS, or DDR LVDS. The pipelined core delivers two simultaneous conversions per sample clock with on-chip track-and-hold. The 0.08 ps RMS jitter specification is what enables undersampling of IF frequencies in communications receivers without SNR penalty - the part can capture narrowband IF signals well above Nyquist while preserving the analog input's dynamic range. The flexible output modes (CMOS / DDR CMOS / DDR LVDS) let designers trade off pin count, board complexity, and EMI against the lowest possible latency. Typical applications include cellular base-station receivers and digital predistortion feedback paths, multi-carrier software-defined-radio (SDR) platforms, medical ultrasound beamformers, and portable or battery-powered test and measurement instruments. The wide input bandwidth and low jitter allow direct IF sampling, eliminating a down-conversion stage in many radio architectures. When designing with this part, pay close attention to the analog input network: a differential transformer or fully differential driver (such as the AD8138 or ADA4927) must precede the ADC inputs, and the analog and digital grounds must be carefully partitioned on the PCB. Output mode selection is made via the MODE pin and is latched on reset; verify the mode configuration against your FPGA or ASIC capture logic before layout. This page synthesizes distributor pricing, drop-in-compatible variants, and practical layout notes drawn from Analog Devices application notes and reference designs - context not collected on a single distributor listing.
LTC2150CUJ-12 - 12-Bit 170Msps Single-Channel ADC | Analog Devices
The Analog Devices LTC2150CUJ-12 is a 12-bit, 170 Msps single-channel pipelined analog-to-digital converter (ADC) housed in a 40-lead 6 mm × 6 mm QFN package (UJ suffix, CUJ ordering code). The converter operates from a single 1.8 V analog supply and a separate 1.8 V to 3.3 V digital I/O supply, making it well suited to low-power, high-density digital systems that already have an LVDS or CMOS interface rail nearby. An ADC is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a sampling rate set by an external clock. Pipelined ADCs such as the LTC2150CUJ-12 use multi-stage conversion to achieve high sampling rates at low power; the LTC2150-12 family sits inside the broader product hierarchy of ADC -> data converter -> mixed-signal IC -> semiconductor, and is offered in 12-bit and 14-bit pin-compatible versions to simplify migration between resolutions. Key features include a 1.25 GHz full-power analog input bandwidth, an optional integrated sample-and-hold front end, clock duty-cycle stabilization for clean Nyquist operation, low-power Sleep and Nap modes, and a serial SPI port for register configuration. The device offers pin-compatibility with 14-bit versions of the same family, allowing PCB reuse between 12-bit and 14-bit designs without layout changes. Differential analog input drive is required to realize the full AC linearity. Typical applications include broadband communications, digital predistortion feedback loops in wireless base stations, cable-modem downstream receive paths, and high-speed test instrumentation. Designers value the LTC2150CUJ-12 for low noise, low latency, and the ability to interface to FPGAs and ASICs over LVDS or CMOS at system sample rates up to 170 Msps.
LTC2150CUJ-14 - 14-Bit 170Msps 1.8V ADC DDR LVDS | Analog Devices
The Analog Devices LTC2150CUJ-14 is a single-channel, 14-bit, 170 Msps pipelined analog-to-digital converter (ADC) housed in a 40-lead QFN (6 mm × 6 mm) package with an exposed pad. It operates from a single 1.8 V analog and digital supply and produces double-data-rate (DDR) LVDS digital outputs, making it well suited for direct connection to FPGA and ASIC capture buffers. A pipelined ADC is a successive-stage converter that resolves the input sample through a cascade of low-resolution flash stages interleaved with sample-and-hold amplifiers; this architecture delivers high sample rates (hundreds of Msps) with low latency (five clock cycles here) and excellent dynamic linearity. Within the broader signal-chain taxonomy, the LTC2150CUJ-14 sits as ADC -> data converter -> signal-chain IC -> semiconductor, occupying the digitisation stage between an analog front end (AFE, amplifier or downconverter) and a digital processor (FPGA/DSP/ASIC). Key headline parameters per the manufacturer datasheet 21521014fa: ±0.85 LSB typical INL, ±0.25 LSB typical DFL, no missing codes over temperature, 1.82 LSBRMS transition noise, 1.25 GHz full-power sample-and-hold bandwidth, and optional clock duty-cycle stabilizer for high performance across non-50% clock duty cycles. The differential ENC+/ENC- encode clock accepts sine, PECL, LVDS, TTL, or CMOS drivers, simplifying clocking from FPGA PLLs or crystal oscillators. The part integrates a serial SPI port for per-channel configuration (output mode, test patterns, power modes), low-power Sleep and Nap modes for power-managed applications, and a pin-compatible 12-bit upgrade path (LTC2150-12 / LTC2151-14 / LTC2152-14 family) for code re-use across 12/14-bit and 170/210/250 Msps variants. Differential analog and clock inputs maximise second-order linearity and common-mode rejection. Typical applications include cellular basestation receiver IF digitisation, medical imaging front ends (ultrasound beamformers, MRI receivers), radar and electronic-warfare IF sampling, cable-modem head-end CMTS downstream capture, broadband communications test equipment, and high-speed oscilloscope/data-acquisition front ends. Designers typically pair it with an AD8138 differential driver on the analog input, an AD9520 clock generator for ENC+, and an FPGA (e.g. Xilinx Kintex, Intel Cyclone) for LVDS capture. When designing with the LTC2150CUJ-14, follow the layout guidelines in the evaluation board DC1565A-C: solid ground planes under the exposed pad, length-matched 50 Ω LVDS output traces, and 0.1 µF + 10 µF decoupling close to each supply pin. Power dissipation is roughly proportional to sample rate and output mode, so enable Nap or Sleep mode when the converter is idle to meet system power budgets. This page synthesises distributor pricing, drop-in same-family alternatives, and practical design guidance that is not consolidated in the manufacturer datasheet.
LTC2151CUJ-14 - 14-Bit 210Msps ADC, DDR LVDS, 40-QFN | ADI
The Analog Devices LTC2151CUJ-14 is a 14-bit, 210 Msps pipelined analog-to-digital converter (ADC) housed in a 40-lead QFN (6x6 mm) package. The -14 speed grade operates at 210 Msps, while the family also includes the LTC2152-14 at 250 Msps and LTC2150-14 at 170 Msps, sharing the same pinout. The device targets demanding communications applications with AC performance that includes 70 dB SNR and 90 dB spurious-free dynamic range (SFDR), plus a 1.25 GHz input bandwidth enabling accurate undersampling of high-IF signals. An ADC (analog-to-digital converter) is a semiconductor that samples continuous analog voltages and converts them into discrete digital codes for downstream DSP, FPGA, or processor-based signal chains. Pipeline ADCs like the LTC2151-14 achieve a balance between high sampling rate, moderate resolution, and low latency - here, only five clock cycles - making them ideal for multi-carrier base stations, broadband digital pre-distortion, and software-defined radio. Within the broader taxonomy, this part is a high-speed ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Key specifications include +/-0.85 LSB INL (typical), +/-0.25 LSB DNL (typical), no missing codes over temperature, and 1.82 LSB RMS transition noise. The digital outputs are double-data-rate (DDR) LVDS, simplifying FPGA capture at full speed. The ENC+ and ENC- encode inputs accept differential sine wave, PECL, LVDS, TTL, or CMOS drive, and an optional clock duty-cycle stabilizer (DCS) maintains SNR across non-50% duty-cycle clock sources. Architecturally, the LTC2151-14 uses a multi-stage pipelined switched-capacitor core stabilized by an internal bandgap reference. The differential analog input pair is designed to be driven through a transformer or differential amplifier for best second-order distortion performance; a 1.25 GHz analog front-end allows IF sampling well above Nyquist. The DDR LVDS interface reduces the output pin count and eases FPGA I/O timing closure at hundreds of MHz. Typical applications include cellular base-station receivers, cable and broadband digital pre-distortion (DPD) feedback paths, test and measurement instrumentation, radar and LIDAR signal acquisition, and software-defined radios. The combination of wide input bandwidth and high SFDR suits multi-carrier GSM/WCDMA/LTE systems where adjacent carriers must remain distinguishable. Designers should pay particular attention to analog input network design - a 1:1 transformer or differential driver is recommended to realize the full 90 dB SFDR - and to FPGA LVDS capture timing because DDR mode halves the available timing budget. Place the part on a low-noise analog supply layer with decoupling close to each supply pin. This page synthesizes distributor stock, pricing, and pin-compatible drop-in alternatives (LTC2150CUJ-14 in the same family, plus competitor equivalents) alongside practical design considerations not duplicated in the manufacturer datasheet.
LTC2151IUJ-12 - 12-Bit 210Msps ADC, 40-QFN | Analog Devices
The Analog Devices LTC2151IUJ-12 is a single-channel 12-bit pipelined analog-to-digital converter (ADC) sampling at 210 Msps, packaged in a 40-lead 6mm x 6mm QFN (UJ suffix) with an exposed thermal pad. It is part of the LTC2152-12/LTC2151-12/LTC2150-12 pin-compatible ADC family, designed for digitizing high-frequency, wide-dynamic-range signals in communications, instrumentation, and defense imaging systems. A pipelined ADC is a high-speed converter architecture that processes the analog input through multiple low-resolution stages in parallel, each stage producing a sub-ADC residue that is digitized by the next stage. This approach enables sample rates well above what successive-approximation architectures can achieve, while maintaining low latency and good spurious-free dynamic range (SFDR). The LTC2151-12 sits at the top of the signal-chain hierarchy: analog sensor -> anti-alias filter -> pipelined ADC -> FPGA/ASIC digital processing. Key features include 1.25 GHz full-power bandwidth sample-and-hold, an optional clock duty-cycle stabilizer for jitter-insensitive operation, and low-power Sleep and Nap modes that reduce dissipation when the converter is idle. The serial SPI port allows in-system configuration of output format, gain, offset, and channel modes. Pin-compatible 14-bit versions (LTC2251-14 family) allow system scalability by swapping the ADC without PCB rework. The device accepts differential or single-ended analog inputs and produces LVDS, parallel CMOS, or serialized LVDS outputs selectable via SPI, simplifying interface to FPGAs. Excellent AC performance with high SFDR makes the LTC2151-12 suitable for directly digitizing IF signals in software-defined radio and radar receivers where spurious content can mask weak targets. Typical applications include cellular base-station receivers, radar and electronic-warfare signal processing, medical imaging front-ends, and high-speed data acquisition cards. The wide input bandwidth permits undersampling of IF carriers, reducing system cost by eliminating a downconversion stage. When designing with this ADC, ensure the analog input network presents 50 ohm (or 200 ohm differential) termination and that the encode clock source has low jitter (<200 fs RMS) to preserve SNR at high input frequencies. The exposed pad must be soldered to a continuous ground plane for thermal and electrical performance. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, including parametric cross-reference guidance for engineers migrating between the 12-bit and 14-bit LTC215x family members.
LTC2152IUJ-12 - 12-Bit 250Msps ADC, Single 1.8V Supply, 40-QFN | Analog Devices
The Analog Devices LTC2152IUJ-12 is a single-channel 12-bit analog-to-digital converter (ADC) sampling at up to 250 Msps, housed in a 40-lead 6x6 mm QFN package (UJ suffix). It is one of three speed grades in the LTC215x-12 family, alongside the 210 Msps LTC2151-12 and the 170 Msps LTC2150-12, and operates from a single 1.8 V analog supply with a separate 1.8 V digital supply for low-noise mixed-signal integration. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous-time analog voltages at discrete instants and quantises them into binary codes; pipeline ADCs such as the LTC2152-12 use a multi-stage switched-capacitor architecture that delivers high sample rates while preserving resolution. The LTC2152-12 belongs to the category hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor, serving communications, instrumentation, and defence systems that demand wide-bandwidth, high-dynamic-range signal acquisition. Key differentiating specifications include 12-bit resolution at 250 Msps real sampling rate, 1.8 V single supply operation, an internal high-bandwidth track-and-hold, differential analog inputs (per datasheet, the inputs must be driven differentially for specified performance), CMOS or DDR LVDS digital-output modes selectable per application, and a low-jitter clock PLL that relaxes the front-end analog filter requirements. The 40-QFN (6x6) package integrates an exposed pad that anchors the thermal and grounding strategy. Architecture-wise, the converter uses a pipelined core with digital error correction across multiple 1.5-bit-per-stage sub-ADCs, weighted against a precision reference and reconstructed by a latency-corrected output stage; this approach delivers spurious-free dynamic range (SFDR) suitable for multi-carrier wireless basestations and pulsed radar receivers where spurious content must remain well below the wanted signal. Typical applications include wideband digitisation of IF/RF signals in wireless infrastructure, digital oscilloscopes and spectrum analysers, radar and electronic-warfare receivers, cable-headend DOCSIS upstream capture, and medical ultrasound beamforming front-ends. The -IUJ suffix indicates the industrial temperature range (-40C to +85C) per ADI's part-numbering convention. When designing with this part, follow ADI's recommended differential input drive network (balun or transformer-coupled op-amp), place the analog and digital 1.8 V rails on separate PCB planes with a ferrite bead between them, and expose the bottom-side thermal pad with adequate vias to a ground pour - the package lead frame cannot dissipate the converter's full-load power without this copper area. This page synthesises ADI datasheet extracts, distributor pricing as of 2026-10-13, and a drop-in alternatives list not found on a single distributor page, giving engineers a faster cross-package/parametric path than re-querying DigiKey or Mouser manually.
LTC2152IUJ-14 - 14-Bit 250Msps ADC, 40-QFN | Analog Devices
The Analog Devices LTC2152IUJ-14 is a 14-bit, 250 Msps single-channel pipelined analog-to-digital converter (ADC) housed in a 40-lead QFN (6 mm x 6 mm) package with an exposed pad for thermal dissipation. Per the LTC2152-14 family datasheet (21521014fa), it features ±0.85 LSB INL (typical), ±0.25 LSB DNL (typical), no missing codes over temperature, and 1.82 LSBRMS transition noise, providing accurate conversion for high-speed signal acquisition. The wideband input supports a 1.4 GHz analog front-end, enabling excellent spurious-free dynamic range at high intermediate frequencies for communications and instrumentation front ends. DDR LVDS digital outputs simplify FPGA/ASIC interface alignment, while the differential ENC+/ENC- sample clock accepts sine, PECL, LVDS, TTL, or CMOS drive levels and an optional clock duty-cycle stabilizer preserves SNR across non-50% duty clocks. Industrial temperature grade (-40°C to +85°C) and a precision internal reference make the LTC2152IUJ-14 well-suited to demanding IF sampling, LTE/WiMAX base stations, and multi-carrier software-defined radio platforms. Common applications also include medical imaging, radar/LIDAR digitizers, and high-end test/measurement digitizer boards where the wide input bandwidth and low latency (six clock cycles) maximize usable signal headroom. At 250 Msps, typical power consumption allows fanless operation with adequate PCB copper on the exposed pad. According to the manufacturer datasheet, the LTC2152IUJ-14 is pin-compatible with the LTC2150-14 (170 Msps) and LTC2151-14 (210 Msps) in the same 40-QFN, giving designers a clear migration path when system sample-rate requirements change late in development. The industrial temperature grade ("I" suffix) and lead-free ("PBF") designation also qualify the part for harsh-environment embedded and ruggedized platforms. This page synthesizes distributor pricing, drop-in same-package alternatives (LTC2150/LTC2151 family), and practical PCB/layout guidance not found in the manufacturer datasheet alone.
LTC2155CUP-12 - Dual 12-Bit 170Msps ADC | Analog Devices
The Analog Devices LTC2155CUP-12 is a dual 12-bit 170 Msps analog-to-digital converter (ADC) designed for digitizing high-frequency, wide dynamic range signals. Housed in a 64-lead QFN (9 mm × 9 mm) package, the LTC2155CUP-12 delivers 68.5 dB SNR and 90 dB SFDR, while consuming only 545 mW total from a single 1.8 V supply. The device supports a single 1.8 V supply with DDR LVDS outputs and an easy-to-drive 1.5 V peak-to-peak input range. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that breaks the conversion into multiple low-resolution stages, each handling one sample per clock cycle. This pipeline approach enables high sampling rates (hundreds of Msps) while maintaining moderate resolution (10-16 bits), making pipelined ADCs the standard for communications, radar, and instrumentation applications. The LTC2155 belongs to the dual-pipelined ADC category, integrating two matched ADC channels on a single die for I/Q baseband or diversity reception. Key features of the LTC2155CUP-12 include a 1.25 GHz full-power bandwidth sample-and-hold, an optional clock duty cycle stabilizer, low-power sleep and nap modes, and a serial SPI port for configuration. The pin-compatible 14-bit versions (LTC2157-14/LTC2156-14/LTC2155-14) allow easy migration when higher dynamic range is needed. The differential inputs are easy to drive, simplifying front-end design for direct-IF sampling receivers. The architecture uses a high-speed pipelined core with on-chip reference and sample-and-hold, achieving excellent linearity and low jitter. DDR LVDS outputs simplify data capture by providing one data pair per channel per clock edge, reducing the number of data lines routed on the PCB. The internal duty cycle stabilizer compensates for clock source imperfections, preserving SNR at high input frequencies. Typical applications include communications receivers, cellular base stations, radar and LiDAR signal chains, portable instrumentation, medical imaging front-ends, and software-defined radio (SDR) platforms. The combination of dual channels, low power, and small QFN-64 footprint makes the LTC2155CUP-12 particularly suited to multi-channel compact systems. When designing with this ADC, pay close attention to the analog input network: a differential transformer or driver amplifier must present 1.5 V peak-to-peak to maximize SNR. Use low-jitter clock sources and matched-length differential output pairs to preserve LVDS timing margins at 170 Msps. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
LTC2155CUP-14 - Dual 14-Bit 170Msps ADC | Analog Devices
The Analog Devices LTC2155CUP-14 is a dual-channel, 14-bit, 170 Msps pipelined analog-to-digital converter housed in a 64-pin QFN (9x9 mm) package. It integrates two simultaneously-sampling ADC channels with parallel CMOS outputs, supports differential inputs, and operates from a 1.7 V to 1.9 V analog supply, drawing approximately 1.0 W per pair of channels at full sample rate. An ADC (Analog-to-Digital Converter) is a data converter IC that transforms continuous analog signals into discrete digital codes for processing by FPGAs, ASICs, DSPs or microcontrollers. Within the converter hierarchy, the LTC2155CUP-14 sits in the high-speed pipelined sub-family, which is the architecture of choice for communications, radar, instrumentation, and defense applications where tens-to-hundreds of Msps are required with 12-16 bit resolution. Pipelined ADCs use a multi-stage switched-capacitor architecture with per-stage residue amplifiers and digital error correction, achieving high sample rates at moderate power while maintaining low latency suitable for many baseband and IF signal chains. Key specifications include 14-bit resolution, 170 Msps sampling rate per channel, 70.1 dB SNR (with 100 MHz input) and 88 dB SFDR, plus a 1.4 GHz analog input bandwidth. The part supports both DDR (Double Data Rate) CMOS and DDR LVDS output modes, and accepts differential analog inputs, enabling direct interface to differential IF chains without external gain blocks. Internal PLL/VCO and clock duty-cycle stabilizer simplify board-level clocking, and per-channel gain/offset adjustment is supported via SPI. Typical applications include broadband communications receivers, LTE/4G base-station digitizers, software-defined radio (SDR), radar and electronic-warfare IF sampling, medical imaging front-ends, and high-speed data acquisition cards for test and measurement. Differential input topology and selectable output modes also simplify interface to Altera/Xilinx FPGAs and high-speed ASICs. When designing with the LTC2155CUP-14, observe proper analog/digital ground partitioning, place bypass capacitors as close as possible to AVDD/DVDD pins, and follow Analog Devices' differential input-balun network recommendations to realize the listed SNR/SFDR performance. Output data format and timing must match the chosen FPGA capture IP. This page synthesizes distributor pricing, drop-in alternatives drawn from the LTC2155 and pin-compatible Linear Technology/Analog Devices families, and practical design notes not consolidated in the manufacturer datasheet.
LTC2155IUP-12 - Dual 12-Bit 170Msps ADC, 1.8V, 64-QFN | Analog Devices
The Analog Devices LTC2155IUP-12 is a dual 12-bit, 170 Msps pipelined analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) package. It operates from a single 1.8V supply, dissipates approximately 545 mW total power, and supports differential input signals with an easy-to-drive 1.5 Vp-p input range. The converter delivers 68.5 dB SNR and 90 dB SFDR, making it suitable for high-frequency wide-dynamic-range signal acquisition. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a defined sample rate. Pipelined ADCs use a multi-stage architecture that enables high sampling rates while maintaining moderate resolution and low power. The LTC2155 belongs to the pipelined ADC sub-family of data converters, which sits within the broader category of mixed-signal ICs and signal-chain components. Key features of the LTC2155-12 family include DDR LVDS outputs for low-noise high-speed data transfer, an optional sample-and-hold front end, a clock duty-cycle stabilizer for jitter-tolerant sampling, and low-power Sleep and Nap modes. The 1.25 GHz full-power input bandwidth allows direct sampling of IF signals. A serial SPI port provides flexible configuration of output modes, gain, and channel selection. The 1.8V single-supply operation simplifies power-tree design in FPGA or ASIC co-located systems, while DDR LVDS outputs minimize pin count and reduce EMI by carrying data on differential edges. The pipelined core uses calibrated capacitor arrays and shared references between channels to keep channel-to-channel gain and offset matching tight. Typical applications include communications receivers (LTE/3G/4G base-station digitizers), radar and phased-array antenna IF sampling, broadband test-and-measurement instrumentation, medical imaging front-ends, and high-speed data acquisition systems. The wide input bandwidth also suits digital oscilloscope front-end channels. The pin-compatible 14-bit (LTC2155-14) and lower-speed family members provide upgrade and cost-down paths on the same PCB footprint. When designing with this device, route the differential analog inputs as length-matched 100-ohm transmission lines, keep the 1.8V analog supply isolated from noisy digital rails, and place the SPI configuration traces away from the LVDS output edges. The exposed pad must be soldered to a continuous ground plane for thermal dissipation and signal-return integrity. This page synthesizes distributor pricing, family upgrade/downgrade alternatives, and practical design notes not found in the manufacturer datasheet alone.
LTC2155IUP-14 - Dual 14-Bit 170Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2155IUP-14 is a dual-channel, 14-bit, 170 Msps analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm, UP suffix) package with an exposed thermal pad. Designed for digitizing high-frequency, wide-dynamic-range signals, it operates from a single 1.8 V supply and requires differential analog inputs to achieve specified performance. What is a high-speed pipelined ADC? A pipelined analog-to-digital converter is a multi-stage architecture where each stage converts a portion of the input then passes a residue to the next stage; this topology trades conversion latency (typically a few clock cycles) for very high sampling rates while keeping per-stage comparator resolution manageable. The LTC2155IUP-14 sits within the ADC -> high-speed ADC -> pipelined ADC -> dual-channel ADC -> data converter -> signal chain IC hierarchy, and belongs to the precision data-converter sub-family targeting communications and instrumentation. Key specifications include: 14-bit resolution per channel, 170 Msps sample rate per channel (two simultaneous channels), 1.8 V single supply, SNR of 74.5 dBFS and SFDR of 90 dBFS typical at 70 MHz input (per the LTC2155-14 datasheet), LVDS digital outputs with configurable termination, and an external/internal reference option. The device integrates a PLL and supports both CMOS and DDR LVDS output modes. Per the manufacturer datasheet 21576514fb, full-power analog input bandwidth exceeds 600 MHz, allowing undersampling of IF signals. Architecturally, the LTC2155IUP-14 uses two interleaved 170 Msps pipelined cores, front-end track-and-hold amplifiers, an optional on-chip dither generator for improved SFDR at small input levels, and a digital output serializer that presents data on a DDR LVDS or CMOS bus. The internal reference simplifies board design; the external reference option enables gain calibration or shared reference across multiple ADCs in a system. Typical applications include digital oscilloscopes, wideband communications receivers (LTE/GSM base-station digital pre-distortion feedback paths), radar IF sampling, cable-modem head-ends, spectral analysis / signal intelligence, and medical imaging front-ends. The dual simultaneous-sampling channels permit I/Q or in-phase/quadrature direct-conversion signal chains without skew correction. Design consideration: drive each analog input differentially through a balun or transformer to avoid second-harmonic distortion; route the 1.8 V analog and digital supplies through separate ferrites to break ground loops between the noisy serializer and the sensitive input front-end. Always capture the full ADC calibration on power-up by issuing the desired calibration mode before normal data capture. This page synthesizes distributor pricing snapshots, drop-in same-package pin-compatible alternatives (LTC2155CUP-14 family variants and same-package Linear Technology speed/replacement options), and practical layout notes not aggregated on a single manufacturer page.
LTC2156CUP-12 - Dual 12-Bit 210Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2156CUP-12 is a dual 12-bit, 210 Msps analog-to-digital converter designed for digitizing high-frequency, wide dynamic range signals in communications, radar, and test instrumentation. Each channel delivers 12-bit resolution at 210 Msps with a pipelined architecture and only five clock cycles of latency, packaged in a 64-lead QFN (UP package code, 9x9 mm) with an exposed pad for thermal dissipation. The part is part of the LTC2157-12 / LTC2156-12 / LTC2155-12 pin-compatible family, so 250 Msps and 170 Msps variants exist on the same footprint. A pipelined ADC is a successive-stage converter architecture that processes one sample per clock cycle after the initial pipeline fill, balancing high sampling rate with moderate die area. Pipelined ADCs sit within the broader hierarchy of analog-to-digital converter -> data converter -> signal chain IC -> mixed-signal semiconductor, and are the dominant topology for converter sampling rates above approximately 50 Msps where successive-approximation (SAR) and flash architectures become impractical. Key features of the LTC2156CUP-12 include typical DC linearity of ±0.26 LSB INL and ±0.16 LSB DNL, no missing codes over temperature, and a low transition noise of 0.54 LSBRMS. The differential analog inputs accept single-ended or differential drive, and the digital outputs are double-data-rate (DDR) LVDS for low-noise, high-speed interface to an FPGA or ASIC. The ENC+ and ENC- clock inputs can be driven differentially from a sine wave, PECL, LVDS, TTL, or CMOS source, simplifying clock distribution in multi-channel systems. Typical applications include multi-channel digital oscilloscopes, wideband radar digitizers, software-defined radio receivers, medical imaging front-ends (ultrasound beamformers), and communications test equipment such as vector signal analyzers. The dual-channel integration saves board area versus two discrete single-channel ADCs, and the pin-compatible family allows the same PCB to be populated with the 250 Msps LTC2157-12 or 170 Msps LTC2155-12 depending on system bandwidth needs. When designing with this part, follow the Analog Devices reference layout for the 64-QFN exposed-pad package: stitch the EP to a solid ground plane with multiple thermal vias, keep analog input traces length-matched and 100 ohm differential, and place the input network and reference decoupling capacitors as close to the pins as possible. The DDR LVDS interface requires careful length matching on the PCB to maintain the 210 Msps data eye margin.
LTC2156IUP-14 - Dual 14-Bit 210Msps ADC 64-QFN | Analog Devices
The Analog Devices LTC2156IUP-14 is a dual-channel, 14-bit, 210 Msps pipelined analog-to-digital converter (ADC) housed in a 64-pin (9 mm x 9 mm) QFN package, designed for the simultaneous sampling of high-frequency, wide dynamic-range signals. It draws 650 mW from a single 1.8 V supply and delivers 70 dB SNR with 90 dB SFDR, with DDR LVDS outputs and a serial SPI port for configuration. The -14 industrial temperature grade operates from -40 C to +85 C. A pipelined ADC is a multi-stage converter architecture that digitizes an analog input through a cascade of low-resolution flash sub-converter stages combined with inter-stage residue amplification and digital error correction. Pipelined ADCs occupy the middle ground between low-power successive-approximation (SAR) converters and very-high-speed flash ADCs, delivering hundreds of megasamples per second at moderate resolution. In a system hierarchy, the LTC2156IUP-14 belongs to the broader category of data converters -> analog-to-digital converters (ADCs) -> high-speed ADCs -> pipelined ADCs, which is one of the principal building blocks of modern signal acquisition and digital signal processing (DSP) systems. Key features include dual simultaneous-sampling channels, an easy-to-drive 1.5 V peak-to-peak differential input range, 1.25 GHz full-power sample-and-hold bandwidth, an optional on-chip clock duty-cycle stabilizer, and low-power Sleep and Nap modes for power-constrained systems. The serial SPI port enables register-level configuration of output formats, gain, and calibration, while DDR LVDS outputs ease the board-level routing of high-speed digital data into an FPGA or ASIC. Typical applications include communications basestations, radar digitizers, medical imaging front-ends, and high-end test and measurement instrumentation. The wide SFDR and fast sampling rate allow direct digitization of IF signals in software-defined radio (SDR), while the dual channels support MIMO or I/Q signal chains. A 1.5 Vp-p input range simplifies the front-end driver design relative to competitors that require 2 Vp-p swings. When designing with this device, place bypass capacitors as close as possible to the supply pins and route the differential analog inputs as a tightly-coupled pair to preserve common-mode rejection at the rated SFDR. The clock trace must be short and well-terminated to meet the 210 Msps conversion rate without violating setup-and-hold timing into the receiver.
LTC2157CUP-12 - Dual 12-bit 250Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2157CUP-12 is a dual-channel, 12-bit, 250 Msps pipelined analog-to-digital converter housed in a 64-lead 9mm x 9mm QFN package. It delivers 68.5 dB SNR and 90 dB SFDR, draws 628 mW total power from a single 1.8 V supply, and provides DDR LVDS digital outputs for high-speed downstream capture into FPGAs or ASICs. The device integrates two matched sample-and-hold front ends, an on-chip clock duty-cycle stabilizer, and a serial SPI port for per-channel configuration. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed successive-approximation architecture that processes each input sample through a cascade of low-resolution stages, each stage converting a residual and passing the amplified remainder to the next. This sub-ranging approach trades a small fixed conversion latency (typically a few clock cycles) for very high sampling rates - 100 Msps to over 1 Gsps - making pipelined ADCs the workhorse of communications, radar, medical imaging, and digital oscilloscope front ends. Key features of the LTC2157CUP-12 include an easy-to-drive 1.5 Vp-p input range that simplifies front-end driver selection, 1.25 GHz full-power input bandwidth, optional clock duty-cycle stabilizer for jitter-sensitive applications, and low-power Sleep and Nap modes for power-cycled receiver chains. The dual-channel integration halves board area versus two discrete ADCs, and the 64-pin QFN exposes two matched analog inputs that share a common reference and clock. Typical applications include multi-carrier wireless base-station receivers, radar signal acquisition, medical imaging front ends, cable-headend QAM demodulators, and high-speed digital oscilloscope input channels. Designers select this part when 12-bit resolution is sufficient and 250 Msps per channel is required in a tight footprint. When designing with the LTC2157CUP-12, ensure the LVDS output traces are length-matched within 25 mil to meet DDR timing and that the exposed pad is soldered with at least 4 thermal vias for the rated power dissipation. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
LTC2157CUP-14 - Dual 14-Bit 250Msps ADC | Analog Devices
The Analog Devices LTC2157CUP-14 (also marketed as LTC2157CUP-14#PBF) is a dual-channel, 14-bit, 250 Msps pipelined analog-to-digital converter (ADC) housed in a 64-pin QFN (9 mm x 9 mm) package. The converter is powered from a single 1.8 V supply, supports differential analog inputs, and provides DDR LVDS digital outputs. According to the manufacturer datasheet 21576514fb, the device achieves 70 dB SNR, 90 dB SFDR, and consumes 650 mW total power. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time analog signals into discrete digital codes. The LTC2157-14 belongs to the pipelined ADC sub-family, which uses multiple cascaded low-resolution stages to achieve high sample rates while maintaining 14-bit resolution. Within the broader taxonomy, this part is a data converter -> ADC -> high-speed pipelined ADC -> dual-channel simultaneous-sampling ADC. Pipelined ADCs are widely used in communications infrastructure, defense electronics, and test and measurement equipment where both speed and resolution matter. Key features of the LTC2157CUP-14 include a 1.5 Vp-p easy-to-drive input range, 1.25 GHz full-power sample-and-hold bandwidth, an optional clock duty cycle stabilizer, low-power sleep and nap modes, and a serial SPI port for per-channel configuration. The dual channels support either external or internal voltage reference and offer simultaneous sampling for I/Q or diversity receiver architectures. Pin-compatible 12-bit versions are available (LTC2157-12 family), allowing design scalability across resolution requirements. The architecture is a 14-stage pipelined ADC with proprietary internal calibration, supporting 250 Msps per channel and offering 1:1 S/H-to-ADC ratio. The LVDS DDR outputs ease FPGA/ASIC capture and reduce pin count on the board. The internal reference simplifies BOM, while the external reference option enables system-wide gain calibration in high-linearity applications. Typical applications include software-defined radio (SDR) receivers, MIMO LTE/WiMAX transceivers, multi-channel data acquisition systems, medical imaging front-ends, and radar/EW signal processing. The dual simultaneous-sampling channels also suit I/Q demodulation and direct-conversion receiver chains. When designing with this part, place the analog input traces as a 50 ohm differential pair with controlled 100 ohm differential impedance, and keep LVDS outputs length-matched to within 50 mil to preserve timing margin. A solid ground plane beneath the QFN exposed pad is required for thermal dissipation at full sample rate. This page synthesizes Analog Devices distributor pricing as of 2026-10-13, drop-in same-family alternatives from the LTC215x-14 series, and practical PCB/layout design notes not duplicated in the manufacturer datasheet.
LTC2157IUP-12 - Dual 12-Bit 250Msps ADC | Analog Devices
The Analog Devices LTC2157IUP-12#PBF is a dual-channel, 12-bit, 250 Msps analog-to-digital converter (ADC) housed in a 64-lead QFN (9 mm × 9 mm) package with exposed pad. The part accepts differential analog inputs with an easy-to-drive 1.5 Vp-p input range, samples both channels simultaneously, and outputs data on DDR LVDS rails from a single 1.8 V supply. The 'IUP' suffix designates the industrial temperature grade of -40 °C to +85 °C, while the 'CUP' commercial variant operates over 0 °C to +70 °C. An ADC (analog-to-digital converter) is a data-conversion IC that transforms continuous analog signals into discrete digital codes for downstream processing by an FPGA, ASIC, or DSP. Within the signal chain it sits between the analog front end (amplifier/filter) and the digital back end, and high-speed pipeline ADCs like the LTC2157 family target wideband IF sampling, communications receivers, and test instrumentation. In the broader taxonomy: ADC -> data converter -> mixed-signal IC -> semiconductor. Key headline specifications include 250 Msps per channel (500 Msps interleaved effective throughput), 70 dB SNR and 90 dB SFDR typical, an input full-power bandwidth of 1.25 GHz, and low power consumption of approximately 650 mW total for the dual-channel device. The part integrates a sample-and-hold, an optional clock duty-cycle stabilizer, low-power sleep and nap modes, and a serial SPI port for mode configuration, eliminating the need for external support logic. Architecturally, the LTC2157-12 uses a multi-stage pipelined converter core with digital error correction. The DDR LVDS interface halves the output pin count and lets the FPGA capture data on both clock edges, simplifying board routing at 250 Msps line rates. The pin-compatible family includes the 14-bit LTC2157-14 and the lower-speed LTC2156-12 (210 Msps) and LTC2155-12 (170 Msps), enabling system scaling without PCB rework. Typical applications include multi-channel communications receivers, MIMO radar digitizers, software-defined radio (SDR) front ends, medical imaging front ends, and high-speed data acquisition systems. The wide input bandwidth supports undersampling of IF signals centered well above Nyquist, while the low power simplifies thermal design in dense multi-channel arrays. When designing with this part, route the 1.8 V analog and digital supplies as separate islands joined at a single ferrite bead, place the 0.1 µF + 10 µF decoupling network within 2 mm of each supply pin, and provide a low-jitter differential clock (PECL/LVDS) to achieve the published SNR. Use the exposed pad as the primary thermal path, soldering it to a continuous ground plane with multiple thermal vias. This page synthesizes authorized distributor pricing, datasheet-cited specifications, and drop-in pin-compatible alternatives from the same LTC215x family - engineering information that helps select the right resolution/speed combination for your signal chain.