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EP910LC-35 - 24 Macrocell Classic EPLD, 35ns | Intel/Altera
EP910LC-35

EP910LC-35 - 24 Macrocell Classic EPLD, 35ns | Intel/Altera

The Intel/Altera EP910LC-35 is a 24-macrocell CMOS Erasable Programmable Logic Device (EPLD) from the Classic device family, housed in a 44-pin PLCC (J-lead) package and rated at 35ns pin-to-pin propagation delay. It belongs to the EP910 series that delivers 450 usable gates with 24 macrocells and operates from a single 5V supply, making it a direct ancestor of today's CPLD and FPGA families. What is an EPLD? An Erasable Programmable Logic Device is a non-volatile programmable logic IC that uses EPROM/EEPROM storage cells to retain configuration after power-down. In the system hierarchy, EPLDs sit between discrete TTL/CMOS glue logic and modern FPGAs: they replace multiple 74-series logic packages with one re-programmable device, are slower and lower density than CPLDs/FPGAs, but offer deterministic timing and instant-on behavior. The EP910 was one of the earliest commercially successful EPLDs. The EP910LC-35 integrates 24 macrocells, each combining a programmable AND/OR array with an output register, and supports toggle rates up to 28.6 MHz at the 35ns speed grade. It is built on a CMOS EPROM process, allowing windowed (ceramic) or one-time-programmable plastic package versions to be erased via UV light. I/O pins feature programmable macrocell flip-flops with individual output enable control. The architecture follows the classic sum-of-products PLA structure: a programmable AND plane feeds a fixed OR plane, with each macrocell containing a foldback path for implementing D, T, JK, or SR flip-flop functions. Pin-to-pin delay is uniform across all paths, simplifying timing closure compared to early FPGAs. Typical applications include glue logic replacement in industrial controllers, address decoding for legacy 8/16-bit microprocessor buses (8086, 68k, Z80), bus arbitration, state-machine controllers, and educational CPLD prototyping. It was widely designed into telecommunications, military, and aerospace systems in the late 1980s and 1990s. When designing with this device, verify timing closure against the 35ns worst-case propagation delay at 5V, ensure adequate decoupling on VCC, and use a programmer such as the Altera Logic Programmer or compatible third-party tools. Modern designs are strongly encouraged to migrate to MAX II/MAX V CPLDs for cost, density, and active lifecycle support. This page synthesizes Rochester Electronics authorized-stock data, Altera legacy datasheet parameters, drop-in alternatives from the same EP910 Classic family, and practical design guidance not found in any single distributor listing.

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EP910LC-35H - 24-Macrocell Classic EPLD, 35ns | Altera DIP-40
EP910LC-35H

EP910LC-35H - 24-Macrocell Classic EPLD, 35ns | Altera DIP-40

The Altera EP910LC-35H is a high-performance Classic EPLD from the EP910 family, featuring a 24-macrocell architecture housed in a 40-pin Ceramic DIP (J-Lead) package. It belongs to Altera's Classic EPLD family, which provides erasable programmable logic with 450 usable gates, 24 macrocells, and propagation delays of approximately 35 ns at commercial temperature grade. The 'LC' suffix indicates low-power CMOS technology and 'H' indicates the ceramic DIP package variant. A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that preceded modern CPLDs and FPGAs. Architecturally, an EPLD consists of an AND/OR logic array feeding a fixed number of macrocells, each containing a flip-flop and configurable output. Compared to a discrete TTL/CMOS logic implementation, an EPLD integrates equivalent gate counts (here ~450 gates) into a single reprogrammable IC, while compared to an FPGA, an EPLD offers non-volatile configuration (UV-erasable EPROM technology in this part) and deterministic, predictable timing that does not require external boot memory. The EP910 sits in the system hierarchy as: programmable logic -> EPLD/CPLD -> digital logic IC -> semiconductor. Key features include 24 macrocells, 36 user I/O pins, 10 dedicated inputs, a maximum propagation delay of 35 ns (tpd), and 5V CMOS operation. The EP910LC-35H also supports in-system UV erasure and reprogramming, has a maximum toggle frequency in the tens of MHz range, and is built on a low-power CMOS process that is compatible with TTL logic levels on its I/O pins. The device is suitable for legacy glue-logic and bus-interface designs. Architecturally, the EP910LC-35H uses a sum-of-products (AND-OR) PLA feeding a 24-macrocell register array, with a programmable interconnect that links each macrocell to one of 36 I/O pins. The 'LC' designation indicates the device is built on Altera's 0.8-micron CMOS EPROM process with low quiescent current (typically under 100 mA ICC). Programming is performed via a standard Altera programming algorithm on a hardware programmer; erasure requires approximately 20 minutes of UV exposure through the ceramic window (note: 'H' = ceramic DIP package with quartz window). Typical applications include legacy industrial controllers, 5V TTL bus-interface glue logic, military and aerospace systems (per /883 screening on related variants), vintage computing peripherals, and replacement of discrete 74LS TTL logic in board-level redesigns. The EP910LC-35H is also commonly used in retrocomputing projects and as a teaching vehicle in digital logic courses. When designing with this device, note that the EP910LC-35H is a legacy 5V part: ensure 4.75V-5.25V VCC, place a 0.1uF decoupling capacitor near each VCC pin, and avoid modern 3.3V logic interfaces without level shifters. The ceramic DIP package requires a socket for UV erasure programming. For new designs, consider modern MAX II or MAX V CPLDs which offer lower power, smaller packages, and in-system programmability. This page synthesizes distributor pricing (Rochester Electronics, LCSC, Jotrin, Censtry), drop-in alternatives within the Altera EP910 family, and practical design notes not consolidated in the manufacturer datasheet.

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EP910LC-35T - 24-Macrocell 35ns CMOS Classic EPLD | Altera
EP910LC-35T

EP910LC-35T - 24-Macrocell 35ns CMOS Classic EPLD | Altera

The Altera EP910LC-35T is a member of the Classic EPLD (Erasable Programmable Logic Device) family fabricated on an advanced CMOS process, delivering 450 usable gates and 24 macrocells with a 35ns pin-to-pin propagation delay in a 44-pin PLCC package. Designed for high-speed, low-power logic integration, this part operates from a single 5V supply and is packaged in a J-lead surface-mount PLCC outline suitable for socketed or soldered production assemblies. A Classic EPLD is a non-volatile, UV-erasable programmable logic device positioned historically between simple PAL/GAL devices and modern CPLDs/FPGAs. In the system hierarchy, EPLDs belong to the programmable logic family, sitting above discrete logic ICs and below today's high-density FPGAs. They are typically used for glue logic, address decoding, state machines, and bus interfacing in 5V legacy designs where deterministic pin-to-pin timing is required. Key features of the EP910LC-35T include 24 macrocells arranged in logic blocks, 36 user I/O pins, in-system programmability via the Altera EPROM-based architecture, and a 28.6MHz maximum operating frequency. The device consumes CMOS-level standby current, supports JTAG-compatible boundary-scan testing on selected package variants, and provides tri-state output control on every macrocell for bus-oriented applications. The EP910LC-35T utilizes Altera's Classic architecture combining a global interconnect with local macrocell feedback, allowing each macrocell to implement combinatorial or registered logic with configurable output polarity. The 35ns speed grade reflects the tPD (pin-to-pin delay) at 5V VCC, which is adequate for peripheral decode and slow-state-machine use cases rather than high-speed datapath logic. Typical applications include 5V address decoding in legacy microprocessor boards, glue-logic replacement of discrete 74LS/74HC gates, bus-interfacing adapters between 8-bit and 16-bit peripherals, and replacement of multiple PAL/GAL devices on industrial control boards. The PLCC-44 footprint also makes it a popular choice for socketed field-replacement scenarios. When designing with this device, ensure the design fits within 24 macrocells and uses the supplied Altera MAX+PLUS II development tools (legacy) for fitting, simulation, and programming file generation. Note that Classic EPLDs are mature/OEM-only devices; current production is limited to authorized distributors stocking legacy inventory. This page synthesizes distributor pricing, legacy cross-references, package-compatible alternatives, and practical design notes for engineers maintaining or replacing EP910-series devices in long-lifecycle equipment.

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EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40

EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera

The Altera EP910LC-40 (re-stocked by Rochester Electronics) is a 450-gate, 24-macrocell CMOS Erasable Programmable Logic Device (EPLD) from the Altera Classic EPLD family, packaged in a 44-pin Plastic Leaded Chip Carrier (PQCC-44) and specified for a 40ns propagation delay. It operates from a single 5V supply, is housed in a windowless plastic J-lead carrier, and is a member of the EP910 family that succeeded the EP610 and EP900 series as Altera's mainstream 5V CMOS EPLDs in the late 1980s and 1990s. An EPLD (Erasable Programmable Logic Device) is a type of non-volatile programmable logic that combines multiple PAL/GAL-like macrocell blocks on a single CMOS die. EPLDs sit in the hierarchy below modern CPLDs and FPGAs: macrocell -> PLD -> EPLD -> CPLD -> FPGA -> programmable logic -> semiconductor. Compared with bipolar PALs, EPLDs deliver lower power (CMOS), higher density (24 macrocells versus 8-16 in early PALs), and reprogrammability using either UV-erasable EPROM cells (windowed ceramic packages) or one-time-programmable EPROM cells (windowless plastic packages). Key features of the EP910LC-40 include 450 usable gates, 24 macrocells distributed across two logic blocks, a 40ns worst-case pin-to-pin propagation delay (tPD) at 5V, 25 MHz maximum toggle frequency, 36 user I/O pins, and 4 dedicated inputs. Architecture is a sum-of-products AND/OR array driving 24 D-type flip-flops with individual preset/reset, J-lead PQCC-44 surface-mount package, 5V single-supply operation, and CMOS power consumption typically under 200 mW. A pin-compatible industrial-temperature grade EP910LI-40 also exists for -40C to +85C deployments. The EP910 architecture combines a global interconnect with two Logic Array Blocks (LABs), each containing 12 macrocells fed by a programmable AND array. Configuration is stored in on-chip EPROM cells, so the device retains its pattern through power cycles without external boot memory - a key advantage over SRAM-based FPGAs of the era. Programming is performed using an Altera Logic Programmer (e.g., PLAD-J, PLAD-32) via the JTAG-like 4-wire serial interface, and the pattern can be erased with UV light through a quartz window (ceramic variants) or locked with security bit in windowless plastic variants. Typical applications for the EP910LC-40 include industrial control glue logic, address decoding for microprocessor and DSP buses, peripheral interface adaptation, vintage PC chipset replacement (e.g., ISA bus glue logic, DMA controller state machines), retro computing and arcade board repair, telecom backplane glue logic, and legacy test equipment. Its 36 I/O pins and 24 flip-flops are well matched to bus-controller state machines and small synchronous interfaces where a few PALs would otherwise be required. When designing with this device, note that 5V CMOS input thresholds are not 3.3V-tolerant - level shifting is required to interface with modern 3.3V logic. The PQCC-44 J-lead footprint needs a socket or careful reflow profile; the package is not pin-compatible with PLCC-44 sockets unless a J-to-PCB adaptor is used. Use the Altera MAX+PLUS II or classic A+PLUS design software for schematics, synthesis and programming file generation; modern toolchains can target EP910 via third-party synthesis flows.

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EP910LC-40H - 40ns Classic EPLD, 24 Macro Cells | Altera
EP910LC-40H

EP910LC-40H - 40ns Classic EPLD, 24 Macro Cells | Altera

The Altera EP910LC-40H is a member of the Classic EPLD (Erasable Programmable Logic Device) family, a high-speed, low-power CMOS programmable logic IC delivering 24 macro cells and 450 usable gates in a through-hole ceramic DIP package. The "-40" speed grade indicates a 40 ns maximum propagation delay (tPD), while the "LC" suffix denotes a low-power, low-cost variant and the "H" marking indicates a specific ceramic package option. It operates from a single 5 V supply and is built on UV-erasable CMOS technology that allows multiple design iterations during prototyping. What is a Classic EPLD? An EPLD is an Erasable Programmable Logic Device, a category that sits between simple PAL/GAL devices and modern CPLDs/FPGAs in the programmable logic taxonomy. EPLDs are non-volatile, contain a fixed AND/OR logic array with user-programmable interconnect, and were widely used in the 1980s and 1990s for glue logic, address decoding, state machines, and bus interface functions. The Classic family was Altera's flagship EPLD line before being superseded by MAX series CPLDs. Understanding this lineage helps engineers recognize the EP910 as an early-era programmable logic building block rather than a contemporary FPGA. Key features of the EP910LC-40H include 24 macro cells, 450 system gates, 40 ns pin-to-pin propagation delay (tPD), 5 V single-supply operation (VCC = 4.75 V to 5.25 V), low-power CMOS technology with typical ICC below 100 mA, and UV-erasable EPROM-based configuration. The device is packaged in a 40-pin ceramic DIP (JEDEC CDIP-40) suitable for prototyping, military, and high-reliability applications through-hole assembly. The "LC" (low-power, low-cost) variants consume less current than the original EP910, making them suitable for portable or power-sensitive systems. Typical applications include address decoding for microprocessor systems, bus arbitration glue logic, state machines and sequencers, peripheral interface controllers (e.g., custom UART, parallel I/O), and replacement of discrete TTL/CMOS logic in legacy industrial, military, and aerospace systems. The Classic EPLD architecture is well-suited to wide combinational decoding and registered logic functions, replacing multiple 74LS/74HC packages with a single programmable device. When designing with this part, engineers should note that it is a UV-erasable device requiring a quartz-windowed package for erasure, with an endurance of approximately 100 erase/program cycles. Modern design flows use the MAX+PLUS II or Quartus II Classic device support, or migrate new designs to MAX II/MAX V CPLDs with pin-compatible footprints. This page synthesizes distributor pricing, drop-in alternatives, and practical sourcing notes not found in the standalone manufacturer datasheet.

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EP910LC-40T - Classic EPLD, 24 Macrocells, 40ns, PLCC-44 | Altera
EP910LC-40T

EP910LC-40T - Classic EPLD, 24 Macrocells, 40ns, PLCC-44 | Altera

The Altera (Intel Programmable Solutions Group) EP910LC-40T is a member of the Altera Classic EPLD family, an erasable programmable logic device fabricated on advanced CMOS technology. It integrates 450 equivalent gates with 24 macrocells and 36 user I/O pins, operates from a single 5V supply, and is offered in a 44-pin Plastic Leaded Chip Carrier (PLCC) package. The -40 speed grade denotes a 40 ns pin-to-pin logic delay (tPD), and the T suffix indicates a tape-and-reel packing option. It is a through-hole or surface-mount device depending on socket choice, widely used for glue-logic integration in legacy industrial systems. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architecture of PAL/GAL with on-chip EEPROM or EPROM storage. Within the broader programmable logic hierarchy, CPLDs sit alongside FPGAs (Field-Programmable Gate Arrays) and SPLDs (Simple PLDs), with CPLDs typically offering faster deterministic pin-to-pin timing, lower power consumption, and instant-on behavior versus SRAM-based FPGAs that require a configuration bitstream. CPLDs are widely used for I/O expansion, bus interfacing, address decoding, and state-machine implementation in industrial, telecom, and military systems where deterministic timing is critical. Key features of the EP910LC-40T include 24 macrocells organized into four Logic Expandable AND-OR arrays, 36 dedicated I/O pins, a 40 ns maximum propagation delay (tPD), 25 MHz typical fMAX, and an erase/rewrite endurance of 100 cycles (windowed UV-erase device). The device is programmed using the Altera MAX+PLUS II or earlier APLUS development tools via a dedicated programming hardware interface. The architecture uses a programmable AND-OR array driving macrocell flip-flops with programmable output polarity. Each macrocell provides D, T, JK, or SR flip-flop modes with a dedicated product-term clock and asynchronous clear, giving the device deterministic timing suitable for replacing multiple discrete 22V10/16V8-style PALs. Typical applications include bus-interface glue logic for legacy 8086/Motorola 68k microprocessor systems, address decoding and chip-select generation, industrial control state machines, and replacement of multiple discrete TTL/CMOS logic gates. The wide supply tolerance and CMOS process make it well suited to noisy industrial environments. When designing with this part, note that it is a UV-erasable windowed device (no -J ceramic-window variant noted in this -LC family code, but the EP910 family includes windowed parts). Designers should verify programming socket compatibility and consider modern MAX II/MAX V CPLDs for new designs. This page synthesizes distributor availability, drop-in alternative MPNs from the same EP910 family, and practical design notes not found in the manufacturer datasheet alone.

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EP910LC30T - 24-Macrocell Classic EPLD, 30ns, PLCC-44 | Intel
EP910LC30T

EP910LC30T - 24-Macrocell Classic EPLD, 30ns, PLCC-44 | Intel

The Intel (formerly Altera) EP910LC30T is a 24-macrocell Classic-family Erasable Programmable Logic Device (EPLD) housed in a 44-pin PLCC package and rated for a 30 ns propagation delay. It belongs to the Altera Classic EPLD family fabricated on advanced CMOS technology and offers approximately 450 usable gates of low-power, high-speed logic integration in a single package. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines the non-volatility of EPROM-based configuration with combinational and registered logic blocks. Within the broader IC hierarchy, an EPLD sits below modern FPGAs and CPLDs in density but above simple PAL/GAL devices, providing deterministic pin-to-pin timing useful for glue logic, address decoding, and state-machine replacement. The EP910 is one of the longest-lived members of the Classic family, originally introduced by Altera in the late 1980s and now supported in long-term supply by Rochester Electronics. Key features include 24 macrocells, 450 equivalent gates, 33.3 MHz maximum operating frequency, 30 ns pin-to-pin propagation delay (commercial grade), 5 V CMOS supply, and erasable windowed UV-erase reprogrammability. The LC suffix indicates a low-power CMOS process variant, while the T suffix indicates Tape and Reel packaging. Pin counts include dedicated inputs, I/O pins, and global clock pins arranged around a central AND-OR programmable interconnect. Technically, the EP910 architecture centers on a programmable AND array feeding a fixed OR array, with each macrocell containing a configurable flip-flop, feedback path, and output enable. This architecture yields predictable, deterministic timing that simplifies timing closure compared with newer SRAM-based FPGA fabrics. The device is in-system programmable via the Altera programming algorithm and supports the industry-standard JTAG-style boundary-scan test. Typical applications include bus-interface glue logic, address decoding for legacy 80xx microprocessors, state-machine replacement, peripheral control logic, and industrial controller boards where 5 V-tolerant CMOS logic and deterministic timing are required. The 44-pin PLCC package suits both through-hole socket and surface-mount assembly. When designing with the EP910LC30T, plan for a single 5 V rail, a programming header compatible with the Altera ByteBlaster or equivalent, and proper decoupling of VCC pins. Note that newer Altera/Intel MAX-series CPLDs are recommended for new designs; the EP910 family is intended for legacy support and long-lifecycle maintenance.

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EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
EP910LC44

EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera

The Intel / Altera EP910LC44 is a 24-macrocell Classic EPLD from Altera's industry-defining Erasable Programmable Logic Device family, fabricated on advanced CMOS technology and housed in a 44-pin PLCC (J-leaded) package. The Classic architecture integrates up to 24 macrocells with 240 product terms and a programmable AND/OR array, providing a high-speed, low-power replacement for discrete TTL/CMOS glue logic on legacy boards. A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that sits in the historical hierarchy between simple PAL/GAL devices and modern FPGAs/CPLDs. Classic EPLDs use EPROM or EEPROM cells to store the AND/OR fuse matrix and offer one-time or reprogrammable logic integration with deterministic, pin-locked timing, making them ideal for state machines, address decoding, and bus-interface logic that requires predictable propagation delays. The EP910 family specifically belongs to the second-generation Classic family targeting higher integration with up to 36 inputs and 24 outputs in a single device. Key features of the EP910LC44 include 24 dedicated output macrocells, 12 dedicated inputs and 24 I/O lines (36 inputs total), 240 product terms for combinational logic, two global clock inputs, and propagation delay options down to 33 ns (LC grade). The device operates from a single 4.75 V to 5.25 V supply with low CMOS standby current, and the PLCC-44 footprint has remained a stable package choice for long-lifecycle industrial and military systems. The device is also available in speed grades denoted by a numeric suffix (e.g., -30, -40) where the suffix indicates the maximum propagation delay in nanoseconds under commercial test conditions. The architecture is a sum-of-products AND-OR array with feedback paths from each macrocell, supporting both registered and combinatorial outputs. Macrocells include programmable output polarity, D/T/J-K flip-flop modes, and dedicated clock/enable controls. This deterministic architecture makes the EP910LC44 particularly attractive for asynchronous designs where designers need to verify timing by hand without relying on synthesis-time place-and-route analysis. Typical applications for the EP910LC44 include address decoding and wait-state generation in legacy 80x86 and 68k processor boards, bus-interface logic between microprocessors and peripherals, glue-logic replacement for SSI/MSI TTL packages, state-machine controllers in industrial automation, and legacy industrial/military systems where long-term supply stability is essential. The 5 V CMOS interface is compatible with TTL logic levels, simplifying integration into existing 5 V designs without level shifters. When designing with the EP910LC44, engineers should verify the programming algorithm compatibility with their chosen device programmer (Altera-supported tools include the A+PLUS and MAX+PLUS legacy software flows plus modern retro-support via JTAG with appropriate adapters). The device is windowless (one-time-programmable in windowed ceramic variants; plastic PLCC versions are OTP-style or EPROM-based depending on lot). System designers should also confirm pinout compatibility when migrating to other 910-series speed grades, since pin assignments remain constant across the family. This page synthesizes the Altera EP910 family datasheet, distributor availability, and practical design notes into a single decision-ready reference - information not available from any single distributor page.

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EP910LC44-30T - 24-Macrocell CMOS EPLD, 33ns, PQCC-44 | Altera
EP910LC44-30T

EP910LC44-30T - 24-Macrocell CMOS EPLD, 33ns, PQCC-44 | Altera

The Altera EP910LC44-30T is a 33ns propagation-delay, PAL-type CMOS Erasable Programmable Logic Device (EPLD) from the Classic EPLD family, packaged in a 44-pin Plastic Leaded Chip Carrier (PQCC-44) with J-bend terminals. It integrates 24 macrocells and offers 240 product terms, providing a flexible logic-integration solution for glue-logic, bus decoding, and state-machine applications in 5V systems. A CMOS Erasable Programmable Logic Device (EPLD) is a non-volatile programmable logic IC that combines the architectural simplicity of PAL-type logic arrays with erasable programming. EPLDs sit in the programmable logic hierarchy between simple PAL/GAL devices and modern CPLDs/FPGAs: EPLD -> PLD -> programmable logic -> logic IC -> semiconductor. They retain the programming on-chip even when powered down, which makes them useful for bootstrap configuration and legacy system replacement. Key features include 12 dedicated inputs, 24 bidirectional I/O lines, and 2 external clock inputs that drive internal registers. The device supports a nominal 5V supply (4.75V to 5.25V) and offers 33ns pin-to-pin propagation delay (tPD) suitable for bus-interface and address-decoding tasks. It is built on advanced CMOS technology for low static power consumption and includes a programmable security bit to protect user logic from unauthorized readback. The PQCC-44 J-lead surface-mount package provides robust mechanical attachment and is rated for the commercial temperature grade. The EP910LC44-30T uses a sum-of-products macrocell architecture: each macrocell contains a programmable AND array feeding an OR gate with a configurable flip-flop, allowing combinational or registered output. The 240 product terms feed the 24 macrocells via a global interconnect, and the device supports asynchronous clear, synchronous preset, and output enable control. Together with the erasable windowed package option in the family, this architecture enables iterative design and field reprogramming. Typical applications include TTL/CMOS logic replacement, random-logic consolidation, address decoding for memory and peripheral buses, bus-multiplexing glue logic, and state-machine implementation in industrial control, telecom, and instrumentation equipment. The 33ns tPD also supports fairly high-speed control-plane paths in legacy 5V designs. When designing with this device, observe the 5V supply tolerance (4.75V to 5.25V) and add a 0.1uF decoupling capacitor close to each VCC pin to suppress switching transients on the parallel macrocell outputs. This page synthesizes distributor pricing, drop-in Altera/Intel Classic EPLD family alternatives, and practical design notes not found in the manufacturer datasheet alone.

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EP910LC44-35 - 24-Macrocell EPLD, 35ns, PLCC-44 | Altera Classic
EP910LC44-35

EP910LC44-35 - 24-Macrocell EPLD, 35ns, PLCC-44 | Altera Classic

The Altera (now Intel) EP910LC44-35 is a 24-macrocell CMOS Erasable Programmable Logic Device (EPLD) from the Classic EPLD family, housed in a 44-pin PLCC package. It provides 450 usable gates, 36 inputs, 24 I/O lines, and a worst-case propagation delay of 35 ns, with a maximum toggle frequency of 28.6 MHz on the device. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that uses floating-gate memory cells to store the AND/OR array configuration. EPLDs sit in the programmable logic hierarchy between simple PAL/GAL devices (small, one-time-programmable) and complex CPLDs/FPGAs (large, SRAM-based, requiring external boot memory). The EP910 family belongs to the OT (Output) sub-family, which features a PAL-type AND/OR architecture and is fabricated on advanced CMOS technology for high speed and low power consumption. Key features include 24 macrocells with configurable D/T/JK flip-flops, 2 global clock inputs with synchronous/asynchronous clocking options, programmable output enable per macrocell, and a JTAG-compatible in-system programmability interface on selected variants. The device operates from a single 5 V supply with low standby current and is windowed-ceramic (JEDEC standard UV-erasable), allowing re-programmability for prototyping. The EP910 architecture uses a single AND array feeding a fixed OR array, which simplifies timing analysis compared to CPLDs. All 24 macrocells share two global clock pins, and the device supports both combinatorial and registered outputs. The 35 ns speed grade makes it suitable for control logic, glue logic, and address decoding in systems where deterministic pin-to-pin timing is required. Typical applications include bus interface and address decoding in 8086/68000-based systems, state-machine controllers, peripheral glue logic, board-level control registers, and legacy industrial control retrofits. The 5 V supply and TTL-compatible I/O also make it a popular replacement for discrete 74LS logic clusters in older designs. When designing with this part, note that the 35 ns pin-to-pin delay imposes a ceiling on system clock frequency when used in synchronous logic paths; engineers targeting faster speeds should consider the EP910LC-30 or EP910LC-25 variants. The windowed-ceramic package requires a UV eraser for re-programming, while plastic OTP variants (-PC suffix) are single-programming for production. This page synthesizes distributor pricing, same-package EPLD drop-in alternatives, and practical design notes not found in a single manufacturer datasheet.

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EP910LC44-40 - 24-Macrocell Classic EPLD, 44-Pin PLCC | Intel / Altera
EP910LC44-40

EP910LC44-40 - 24-Macrocell Classic EPLD, 44-Pin PLCC | Intel / Altera

The Intel / Altera (formerly Altera Corporation) EP910LC44-40 is a member of the Altera Classic EPLD family, an erasable programmable logic device fabricated on advanced CMOS technology for high-speed, low-power logic integration. The EP910LC44-40 delivers 24 dedicated macrocells, 36 total inputs (12 dedicated inputs plus 24 I/O lines), and 240 product terms distributed across the AND/OR array. The "-40" speed suffix indicates a 40 ns pin-to-pin propagation delay (tPD) commercial timing grade, packaged in a 44-pin Plastic Leaded Chip Carrier (PLCC) with the "LC" pinout designation. The "L" prefix denotes low-power CMOS technology, and the device is supported by the legacy Altera MAX+PLUS II / MAX+PLUS development environment using JEDEC-compatible programming files. What is an EPLD? An Erasable Programmable Logic Device (EPLD) is a non-volatile programmable logic IC that uses EPROM/EEPROM storage cells to retain the user's logic configuration. EPLDs sit in the hierarchy: programmable logic -> PLD -> EPLD -> CMOS PLD -> programmable logic device -> semiconductor IC. The Classic EPLD family preceded modern CPLDs in Altera's roadmap, offering a CMOS PAL-type architecture with sum-of-products logic and a fixed AND-to-OR interconnect. EPLDs are typically used for glue logic, address decoding, bus interfacing, state-machine implementation, and peripheral control where deterministic 40 ns timing is acceptable and in-system reprogrammability is not required. Key features of the EP910LC44-40 include 24 macrocells, 240 product terms, 24 bidirectional I/O pins, 12 dedicated input pins, 2 global clock inputs, and TTL-compatible I/O. The device supports 100% TTL-level compatibility and operates from a single 5 V supply. Logic is configured via industry-standard JEDEC maps and may be programmed using Altera's legacy LP6, MP9, or third-party programmers; UV-erasable variants (windowed ceramic DIP/CLCC packages) coexist with one-time-programmable plastic packages in the same family. Architectural enhancements such as programmable macrocell flip-flops and configurable I/O architectures distinguish the Classic family from earlier PAL/GAL devices. Architecturally, the EP910LC44-40 uses a programmable AND array feeding a fixed OR array, with each macrocell containing a flip-flop, output enable, and feedback path. The 2 dedicated clock pins drive the global clock network that fans out to every macrocell flip-flop, while the 24 I/O pins can be individually configured as input, output, or bidirectional. Power consumption is reduced by CMOS technology compared with bipolar PAL parts, and the device operates across the commercial 0C to +70C temperature range. Programming is non-volatile in windowed packages, enabling multiple design iterations via UV erasure. Typical applications include legacy industrial control boards, address decoding for microprocessor/microcontroller systems, peripheral interface glue logic, bus arbitration circuits, and replacement of discrete 74LS/74F TTL logic. Engineers also deploy the EP910 in aerospace and defense sustainment programs, medical equipment long-life-cycle boards, and test & measurement instrumentation where original designs must be maintained for 20+ year product support windows. The 44-pin PLCC package is socket-compatible with production programmers and is footprint-compatible with other PLCC-44 EPLDs in the Classic family. When designing with the EP910LC44-40, note that propagation delay of 40 ns may not meet timing budgets in modern 33 MHz or faster microprocessors; verify setup/hold timing against the asynchronous or synchronous interface requirements. The device must be programmed before use with a JEDEC file generated by MAX+PLUS II (legacy) or compatible tools; designs not following the macrocell product-term limits must be recompiled for the target device. The plastic PLCC package is one-time programmable in non-windowed variants, so plan JTAG-free programming flow during manufacturing. This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving engineers a single-decision reference for legacy EPLD procurement.

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EP910LI-12 - 24-Macrocell Classic EPLD, 12ns PLCC-28 | Altera
EP910LI-12

EP910LI-12 - 24-Macrocell Classic EPLD, 12ns PLCC-28 | Altera

The Altera EP910LI-12 is a member of the Altera Classic EPLD (Erasable Programmable Logic Device) family, integrating 24 macrocells and 450 usable gates on a 1.0-micron CMOS EPROM process. Housed in a 28-pin PLCC windowed ceramic package with a 12 ns pin-to-pin propagation delay, it is intended for high-speed, low-power logic integration in glue-logic, bus arbitration, and state-machine roles. The 'LI' suffix denotes the PLCC windowed package and the 'I' suffix indicates the industrial operating temperature range of -40C to +85C, while '-12' marks the speed grade. Background: an EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that sits between simple SPLDs/CPLDs and high-density FPGAs. EPLDs use EPROM, EEPROM, or flash cells to retain configuration, combine AND/OR arrays with output macrocells, and historically delivered fast deterministic propagation delays in the 5-15 ns range. The EP910 belongs to the Classic EPLD family hierarchy: EPLD > programmable logic > PLD > digital IC > semiconductor. Classic EPLDs were widely deployed in the 1990s for glue logic, address decoding, and peripheral interfacing where speed and simplicity outweighed gate count. Key features of the EP910LI-12 include 24 macrocells, 36 inputs (with input registers), 24 I/O pins, 76.9 MHz maximum operating frequency, and 12 ns worst-case combinatorial propagation delay (tPD). Power consumption is specified at less than 200 mW typical at 5 V, with TTL-compatible I/O and a 5 V VCC supply. Programming uses the original Altera Master Programming Unit (MPU) or compatible third-party programmers via the dedicated program/erase pins, and the ceramic windowed package enables UV erasure for prototyping and design iteration. Typical applications include 5V bus arbitration, address decoding, peripheral interface glue logic, state machines, and legacy system retrofits. When designing, ensure all inputs are tied to a defined logic level to avoid floating-pin issues, observe the recommended decoupling scheme (one 0.1 uF capacitor per VCC pin), and verify that the chosen programmer supports the Classic EPLD JTAG/byte-blaster protocols before committing to the EP910LI-12. Note that Altera Classic EPLDs are mature EOL components - consult Rochester Electronics for current authorized inventory and lifecycle data. This page synthesizes distributor pricing, drop-in alternatives from the same Classic EPLD family, and practical design notes not found in the original Altera datasheet.

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EP910LI-15 - 15 ns Classic EPLD, 36 I/O | Altera | Logic Integration
EP910LI-15

EP910LI-15 - 15 ns Classic EPLD, 36 I/O | Altera | Logic Integration

Altera EP910LI-15 is a high-speed, low-power programmable logic device from the Altera Classic EPLD family, supplied in a 44-terminal J-lead ceramic chip carrier identified as PQCC44. The device operates from a 4.5 V to 5.5 V supply and supports an operating temperature range of -40 °C to +85 °C. It provides 12 dedicated inputs and 24 configurable input/output lines through its macrocell outputs. The “-15” ordering designation corresponds to a 15 ns speed grade in the available search context, while the exact device architecture and timing limits should be confirmed from the manufacturer datasheet before a new design. The EP910LI-15 is a programmable logic IC rather than a fixed-function gate array, combining logic integration with programmable configuration. Its PLD classification places it below general-purpose FPGA devices in flexibility but above discrete combinational logic for applications requiring compact, deterministic implementation of glue logic, state machines, decoders, and interface functions. The 36 available user-signal resources, comprising 12 dedicated inputs and 24 input/output lines, make the device useful for moderately complex board-level control logic. The Classic EPLD architecture is designed to provide predictable logic implementation while reducing the number of separate standard logic packages required on a PCB. CMOS technology supports the low-power logic integration described for the Altera Classic device family. In practice, the EP910LI-15 can consolidate random logic, registered control, and bus-interface functions into one programmable device. The 4.5 V to 5.5 V operating range is appropriate for 5 V logic systems, while the -40 °C to +85 °C range supports industrial-temperature deployments. The PQCC44 ceramic J-lead package is surface-mount technology with a larger ceramic carrier format, so land-pattern verification, mechanical inspection, and process compatibility are important for assembly. For a new production design, confirm the complete pin assignment, configuration procedure, supported design software, timing characteristics, and availability through the manufacturer or an authorized supplier. This page combines verified search facts, pricing and lead-time guidance, package details, and engineering-oriented design considerations for legacy programmable-logic sourcing and board support.

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EP910LI-20 - Classic EPLD 24 Macrocells, 20ns | Altera
EP910LI-20

EP910LI-20 - Classic EPLD 24 Macrocells, 20ns | Altera

The Altera EP910LI-20 is a member of the Altera Classic Erasable Programmable Logic Device (EPLD) family, integrating 24 macrocells in a high-speed, low-power CMOS architecture. It provides 16 dedicated input pins, 24 I/O pins, and operates at a tpd (pin-to-pin delay) of 20 ns with a maximum toggle frequency of 62 MHz. The part is supplied in a 40-pin ceramic DIP (Windowed) package, indicated by the 'L' package designator and 'I' industrial temperature grade. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that combines the non-volatility and reprogrammability of UV-erasable EPROM technology with the macrocell-based logic density of early PLDs. EPLDs sit in the hierarchy: programmable logic -> PLD -> EPLD -> CMOS EPLD -> logic integration IC, predating modern CPLDs and FPGAs. The Classic family was Altera's flagship high-speed, low-power logic integration platform in the late 1980s and 1990s. The EP910LI-20 is fabricated on an advanced CMOS process that delivers low static power consumption typical of the Classic family, typically 200 mA ICC at military/industrial operating conditions. The device is pin-compatible across the EP910 family, allowing designers to swap speed grades (EP910LC-40, EP910LC-35, EP910LC-30) without PCB rework. Each macrocell offers configurable combinatorial or registered logic, with dedicated product-term architecture supporting sum-of-products implementation typical of the Classic era. Typical applications for the EP910LI-20 include state-machine control, address decoding, glue logic replacement, and legacy system maintenance where modern FPGAs are unsuitable for form-factor or environmental reasons. The windowed ceramic DIP package supports field erasure via UV light, enabling iterative development cycles. The industrial temperature grade ('I' suffix) supports operation across -40C to +85C ambient environments. When designing with this EPLD, designers must respect the 5V VCC requirement and the 20 ns propagation delay budget. Power sequencing should ensure clean rise/fall on VCC to avoid latch-up. For new designs, the EP910LC series in plastic DIP packages is recommended; the EP910LI is preferred for long-lifecycle, harsh-environment, or field-reprogrammable applications.

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EP910LI-20T - Classic EPLD, 24 Macrocells, 20ns DIP-20 | Altera
EP910LI-20T

EP910LI-20T - Classic EPLD, 24 Macrocells, 20ns DIP-20 | Altera

The Intel / Altera EP910LI-20T is a member of the Classic EPLD (Erasable Programmable Logic Device) family, delivering 24 macrocells, 10 dedicated inputs, and 20 I/O pins in a 20-pin ceramic DIP (CDIP-20) through-hole package. It is fabricated on an advanced CMOS EPROM technology and offers a 20 ns pin-to-pin propagation delay with a 95 MHz maximum operating frequency, targeting high-speed, low-power logic integration. A Classic EPLD is a one-time or UV-erasable programmable logic device that sits between simple PLAs and modern FPGAs in the programmable-logic hierarchy. The Classic family provides deterministic pin-to-pin timing, non-volatile configuration storage on-chip, and a single +5 V supply requirement, which makes them attractive for legacy glue-logic, bus-interface, and state-machine designs where designers need predictable timing without a separate boot PROM. The EP910 is the highest-density member of the family and is pin-compatible with the lower-density EP610 within the Classic portfolio. Key features of the EP910LI-20T include 24 macrocells organised into four Logic Array Blocks (LABs), 20 bidirectional I/O pins, 10 dedicated input pins, a 20 ns combinatorial propagation delay, and an industry-standard JEDEC-standard programming algorithm that allows third-party programmers to configure the device. The ceramic DIP-20 package with the -20 speed grade is the slowest of the EP910 speed bins (which span -12, -15, and -20), making it suitable for cost-sensitive, lower-speed applications. The part is offered in industrial (-40 C to +85 C) and commercial (0 C to +70 C) operating ranges. Architecturally, the EP910 uses a sum-of-products AND/OR array feeding an expandable macrocell with a configurable flip-flop, XOR gate, and output enable. Its AND array is fully connected across all inputs and feedback terms, giving designers 100% product-term utilisation. The device is programmed with a 21 V programming voltage applied through industry-standard JTAG-like or third-party algorithms, and a windowed ceramic package variant allows UV erasure for prototyping. Typical applications include TTL/CMOS glue logic replacement, address decoding for microprocessor and memory systems, state machines for industrial control, bus-interface adaptation between different logic families, and legacy system maintenance where the original Altera Classic logic must be replicated. The EP910LI-20T is widely stocked in the long-lifecycle and mil-aero markets through distributors such as Rochester Electronics. When designing with the EP910LI-20T, treat the 20 ns propagation delay as a worst-case specification across temperature; derate by 20-30% when designing for the industrial temperature range. The ceramic DIP-20 footprint allows hand-soldering for prototypes, but designers targeting production should consider the plastic DIP-20 (PC-20) variant or migrate to a MAX series device if higher density is required. This page synthesises distributor pricing, drop-in same-family alternatives, and practical design notes not found in the original Altera datasheet, providing a modern procurement reference for engineers maintaining legacy systems built on the Classic EPLD family.

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EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera
EP910LI-30

EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera

The Rochester Electronics EP910LI-30 is a 24-macrocell Classic-series Erasable Programmable Logic Device (EPLD) with a 30ns propagation delay, housed in a 44-pin Plastic Leaded Chip Carrier (PQCC44 / PLCC-44) surface-mount package. The EP910 family delivers approximately 450 usable gates and 24 macrocells backed by non-volatile UV-erasable CMOS logic, targeting glue-logic replacement and medium-complexity state-machine integration on legacy +5V digital boards. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that sits in the design hierarchy between simple PLDs (PAL/GAL) and modern FPGAs/CPLDs. EPLDs use a sum-of-products AND/OR architecture with a programmable interconnect network and can be erased via ultraviolet light and re-programmed, making them ideal for prototyping and field updates. The EP910 occupies the mid-density tier of the Altera Classic family, providing more logic capacity than 22V10-style PALs while consuming far less board area than a discrete TTL/CMOS implementation. Key features of the EP910LI-30 include 24 macrocells, 10 dedicated input pins and 22 I/O pins, 450 equivalent gates, 30ns pin-to-pin propagation delay (tPD), and a 5V ±5% single supply. The 'L' suffix denotes the low-power CMOS process, and the 'I' suffix indicates the industrial operating temperature range of -40C to +85C. The PQCC44 J-leaded package supports standard surface-mount assembly and is socket-compatible with the EP910LC44 (commercial-temperature variant), simplifying qualification across product lines. Architecturally, the EP910 is implemented in 1.0-micron CMOS EPLD technology with EPROM-style programmable interconnect, providing non-volatile configuration retention without external configuration memory. Each macrocell contains a programmable flip-flop, feedback path, and output enable control. The device is programmed via a standard Altera/Altera-compatible programming algorithm and is fully supported by legacy MAX+PLUS II and classic Altera development toolchains. Typical applications include TTL/CMOS glue-logic integration, address decoding for legacy 8-bit and 16-bit microprocessors (8086, 68000, Z80, 8051), bus-interface state machines, peripheral controllers, and replacement of discrete 74LS/74HC logic on industrial control boards. Its 30ns tPD suits buses clocked up to approximately 16 MHz. As of 2026-09-10 the part is supplied exclusively through authorized and aftermarket channels stocking Rochester Electronics inventory, reflecting original Altera EOL of the EP910 family in the late 1990s. When designing with the EP910LI-30, allocate a 1.5 square-inch copper pour beneath the PLCC socket to keep junction temperature within industrial limits, and observe Altera's recommended programming algorithm for in-system or socket programming. Designers should also note that newer MAX II / MAX V CPLDs from Intel (formerly Altera) are NOT pin-compatible with the EP910 footprint. This page synthesizes distributor pricing, Rochester Electronics lifecycle status, drop-in alternatives, and practical design notes not consolidated in the original Altera datasheet.

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EP910LI-30T - 24-Macrocell Classic EPLD, 30ns, PQCC-44 | Altera
EP910LI-30T

EP910LI-30T - 24-Macrocell Classic EPLD, 30ns, PQCC-44 | Altera

The Altera EP910LI-30T is a member of the Altera Classic EPLD family, providing 24 macrocells (450 usable gates) of CMOS programmable logic in a 44-pin Plastic Leaded Chip Carrier (PQCC-44) package. The "LI" suffix denotes an industrial temperature range and 30 ns propagation delay (tPD), while the trailing "T" indicates a Tape and Reel packaging option for surface-mount assembly. What is a Classic EPLD? A Classic Erasable Programmable Logic Device (EPLD) is a type of programmable logic IC that combines AND/OR arrays with user-programmable macrocells, enabling the replacement of multiple discrete SSI/MSI logic gates with a single re-programmable device. EPLDs sit at the lower end of the programmable logic hierarchy below CPLDs and FPGAs, offering non-volatile (UV-erasable) configuration, predictable timing, and fast pin-to-pin propagation delays - ideal for glue-logic, state-machine, and bus-Interface applications. The EP910LI-30T delivers 24 macrocells, 10 dedicated input pins, 24 I/O pins (bidirectional), and operates over the industrial temperature range of -40°C to +85°C. It is fabricated on advanced CMOS technology, providing high-speed, low-power logic integration with tPD of 30 ns, tCO of 20 ns, and fMAX compatible with high-speed control logic. The device is housed in a J-leaded PQCC-44 surface-mount package. Architecturally, the EP910 uses a sum-of-products PLA structure feeding registered output macrocells, with each macrocell offering product-term allocation, output polarity control, and a flip-flop. Programming is performed via a standard EPROM programmer using the Altera Logic Programmer or compatible tools. Typical applications include bus-interface glue logic, state-machine replacement of discrete 74LS/74HC logic, address decoding in microprocessor systems, and timing-control circuits in industrial controllers. Designers often choose the EP910 family when non-volatile configuration, deterministic timing, and high I/O count in a small plastic package are required. When designing with this device, note that the PQCC-44 footprint requires socketed or reflow assembly; ensure proper handling of UV-erasable windowed versions if reprogramming is needed. For modern designs, verify that software tools (Altera MAX+PLUS II legacy support) are still accessible in your workflow. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the original Altera datasheet.

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EP910LI-35 - Classic EPLD, 24 Macrocells, 38ns PLCC-44 | Altera
EP910LI-35

EP910LI-35 - Classic EPLD, 24 Macrocells, 38ns PLCC-44 | Altera

The Altera EP910LI-35 is a 24-macrocell member of the Altera Classic EPLD family, delivering 900 usable gates in a 44-pin PLCC package with a 35 ns propagation delay. As an industrial-temperature variant (-40 °C to +85 °C) of the EP910 die, it provides 38 user I/O pins and operates from a single 5 V supply, targeting glue-logic replacement, address decoding, and state-machine consolidation in industrial and legacy systems. A CPLD (Complex Programmable Logic Device) is a non-volatile, electrically erasable programmable logic device that combines the instant-on characteristics of PAL/GAL with macrocell-level logic density. Within the broader taxonomy, the EP910 belongs to the Classic EPLD family (CPLD -> EPLD -> PLD -> programmable logic -> semiconductor), which Altera positioned as the forerunner of modern MAX-series CPLDs. The Classic family targets bus-interface logic, peripheral controllers, and high-speed state machines where low-cost, deterministic logic is required. Key features include a 76.9 MHz maximum counter frequency (f_CNT), 24 macrocells split across two Logic Array Blocks (LABs), a 24-pin input array, and a pin-locking architecture for predictable PCB layout reuse. EPROM-based configuration supports >100 erase/program cycles for prototyping iteration, and the device retains its logic configuration without external memory. The PLCC-44 (J-leaded) package provides surface-mount assembly with mechanical robustness suited to industrial sockets and field-replaceable modules. Architecturally, the EP910 uses sum-of-products logic feeding programmable output macrocells with configurable flip-flop polarity, feedback paths, and tri-state control. Each macrocell can be configured as registered or combinatorial, allowing sequential and combinational logic to be intermixed freely. The 38-ns t_PD reflects the older Classic CMOS process node, sufficient for buses under ~25 MHz but slower than modern MAX V or MAX 10 devices. Typical applications include peripheral glue logic, address decoding for microprocessor systems, bus arbitration, legacy industrial control boards, and retro-computing platforms. The wide supply tolerance (4.75 V to 5.25 V) simplifies integration with TTL/CMOS 5 V logic. Designers also use EP910 for state machines in CNC controllers, test equipment front panels, and aerospace ground-test instrumentation where deterministic timing matters more than raw speed. When designing with this device, observe the 35 ns propagation delay when computing set-up margins for downstream registers. The PLCC-44 footprint differs from modern 0.5 mm-pitch QFNs, so PCBs targeting EP910 family variants should accommodate the 1.27 mm J-lead pitch. Use Rochester Electronics as the authorized continuing source for end-of-life inventory. This page synthesizes distributor pricing, drop-in pin-compatible Classic-family alternatives, package diagrams, and PCB-layout guidance not consolidated in any single distributor catalog page.

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EP910LI-35BF - 24-Macrocell Classic EPLD, 35ns, PLCC-44 | Altera
EP910LI-35BF

EP910LI-35BF - 24-Macrocell Classic EPLD, 35ns, PLCC-44 | Altera

The Altera EP910LI-35BF is a member of the Altera Classic Erasable Programmable Logic Device (EPLD) family, delivering 24 macrocells and 450 usable gates in a 44-pin PLCC (Plastic Leaded Chip Carrier) package with industrial-grade speed grade tpd=35ns. It is fabricated on advanced CMOS technology and provides 100% TTL emulation with pin-to-pin compatibility across the EP910 family. The "LI" suffix indicates the PLCC package and industrial operating temperature range. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple PAL/GAL devices and complex FPGAs in the programmable logic hierarchy (PAL/GAL -> EPLD -> CPLD -> FPGA -> SoC FPGA). It offers erasable/reprogrammable combinational and registered logic, suitable for glue-logic, address decoding, state machines, and bus-interface functions that previously required multiple discrete SSI/MSI TTL parts. EPLDs are characterized by deterministic pin-to-pin timing, a macrocell-based architecture, and predictable routing delays, which is critical for asynchronous and memory-interface designs. Key features of the EP910LI-35BF include 24 macrocells, 450 usable gates, a maximum pin-to-pin propagation delay (tpd) of 35 ns, a maximum toggle frequency (fmax) of 28.6 MHz, and a 5V supply. The device supports in-system UV-erase (windowed) operation and is packaged in a 44-pin PLCC (J-lead) carrier. Compared with bipolar PAL/GAL devices, the CMOS EP910 offers substantially lower power dissipation, while providing higher integration for logic consolidation. Internally, the EP910LI-35BF uses a macrocell-based AND/OR array architecture: each macrocell contains a programmable AND-term array, an XOR gate for polarity control, and a flip-flop (D/T/JK/SR selectable). Output enable and feedback are fully programmable, and unused macrocells can be disabled to reduce quiescent current. The device is programmed via a standard EPROM/UV-erase programmer with a 20-pin programming algorithm compatible with the Altera Classic family. Typical applications include address decoding for 8/16-bit microprocessors and DMA controllers, glue-logic replacement for TTL/CMOS discrete gates, register/latch/FSM consolidation in industrial controllers, bus-interface adapters (e.g., legacy peripheral bus glue), and prototyping platforms where erasability is needed. Because of its 5V supply and TTL compatibility, the EP910 is also used to retrofit older designs that must remain 5V throughout the signal path. When designing with the EP910LI-35BF, ensure the device is decoded cleanly from other PLDs or memory maps to avoid bus contention, use a 0.1uF decoupling capacitor close to each VCC pin, and respect the IOL/IOH DC specifications (typically 4-8 mA per output) to avoid exceeding drive strength when interfacing to heavily loaded buses. This page synthesizes distributor pricing, drop-in alternatives, application guidance, and practical design notes not found in the standalone Altera datasheet, including a side-by-side comparison with sibling Classic EP910 speed grades and package options.

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EP910LI-35H - 900 Gates, 24-Macrocell Classic EPLD, 35ns PLCC-44
EP910LI-35H

EP910LI-35H - 900 Gates, 24-Macrocell Classic EPLD, 35ns PLCC-44

The Intel / Altera EP910LI-35H is a 900-gate, 24-macrocell member of the Altera Classic Erasable Programmable Logic Device (EPLD) family, fabricated in advanced CMOS technology and packaged in a 44-pin PLCC (J-lead) housing. The “-35” speed grade corresponds to a tPD of 35 ns, while the “H” suffix denotes the lead-free / industrial operating temperature option within the Classic EPLD roadmap. The part integrates 24 macrocells and approximately 900 usable gates of combinational and registered logic, supported by a programmable interconnect array (PIA), global and product-term clock networks, and a non-volatile EPROM cell that retains the user pattern with UV-erase reprogrammability. An EPLD (Erasable Programmable Logic Device) is a class of one-time- or erasable-programmable CMOS logic that historically preceded modern flash-based CPLDs and FPGAs. Within the programmable logic hierarchy, EPLDs sit above discrete 22V10-style PALs (in density and macrocell richness) but below contemporary non-volatile CPLDs and SRAM-based FPGAs in raw logic capacity, I/O count, and I/O standards support. The Classic EPLD family was Altera’s flagship low-power, high-speed glue-logic platform in the 1980s and 1990s, optimized for bus arbitration, address decoding, state-machine control, and peripheral interfacing on 5 V digital boards. Key features of the EP910LI-35H include 24 dedicated macrocells with configurable D/T/JK flip-flop behavior, a programmable AND/OR array with 36 inputs feeding the PIA, pin-compatible speed grades (tPD 12 to 40 ns) that allow easy in-family upgrades/downgrades, low CMOS standby current suitable for battery-backed systems, and JEDEC-standard programmer compatibility. The architecture separates input macrocells (with registers) from output macrocells (with feedback), enabling efficient bi-directional bus implementation without external transceivers. Typical applications include 5 V microprocessor glue logic (address decoding, wait-state insertion, interrupt prioritization), peripheral interface controllers (PIO, UART glue, custom IEEE-488 / GPIB state machines), industrial control sequencers, military and avionics legacy systems requiring MIL-STD-883 processing, and replacement designs for end-of-life discrete SSI/MSI logic. Because the part is widely second-sourced (Rochester Electronics, etc.) it remains attractive for long-lifecycle programs. Designers should note the EP910LI-35H is a mature, NRND/EOL part on most franchised distributor line cards; long-term programs typically procure through authorized aftermarket channels. Verify pinout (44-pin PLCC) and speed grade against the original datasheet before substituting with other -35 or -30 speed grades. This page synthesizes distributor pricing, in-family and cross-family drop-in alternatives, and practical design notes not consolidated on the manufacturer datasheet alone.

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EP910LI-35T - 24-Macrocell Classic EPLD 35ns 44-PLCC | Intel
EP910LI-35T

EP910LI-35T - 24-Macrocell Classic EPLD 35ns 44-PLCC | Intel

The Intel (formerly Altera) EP910LI-35T is a 24-macrocell Classic EPLD from the EP910 family, fabricated on advanced CMOS technology and offered in a 44-pin PLCC package with 35 ns pin-to-pin propagation delay. It delivers 450 usable gates, 24 macrocells, and a maximum toggle frequency of 28.6 MHz, all from a single 5 V supply. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC historically used as a glue-logic replacement for multiple TTL/CMOS SSI/MSI parts. Sitting in the taxonomy between PAL/GAL and modern CPLD/FPGA, EPLDs offer deterministic combinational and registered logic with EPROM- or EEPROM-based configuration. The EP910 family from Intel/Altera represents one of the industry-standard Classic EPLD lines used in long-life-cycle industrial, military, and aerospace systems. Key features include 24 macrocells with configurable I/O architecture, 450 usable gates, 35 ns tPD propagation delay, 28.6 MHz fMAX toggle frequency, and a single 5 V (4.75 V–5.25 V) supply. The device supports in-system programmability via Altera's classic programming algorithm and offers 10-year data retention thanks to EPROM-based configuration cells. The 44-pin PLCC package is JEDEC-standard and supports both socketed and surface-mount assembly. The EP910LI-35T architecture combines a global interconnect matrix with per-macrocell product-term arrays, allowing wide AND-OR logic and buried register feedback. Compared with discrete TTL/MSI replacement, it reduces board area by typically 5:1 to 10:1 while improving timing predictability and reducing power consumption to CMOS levels at idle. Typical applications include industrial control glue logic, military/aerospace retrofit boards, telecom interface adapters, and legacy peripheral controllers. The wide supply tolerance (4.75 V–5.25 V) makes it tolerant of legacy 5 V backplanes. The deterministic 35 ns delay simplifies worst-case timing closure in asynchronous control paths. Designers should note that the EP910 family is in long-term support status - new designs are not recommended, but Obsolescence/EOL notifications typically allow multi-year last-time-buy windows via franchised distributors and aftermarket suppliers like Rochester Electronics. Programming requires Altera-supported hardware (e.g., Altera Logic Programmer or compatible). This page synthesizes verified distributor pricing, drop-in replacement options (including the EP910LC and EP910ILC family variants), and practical design considerations not consolidated in the original datasheet.

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EP910LI-35Y - Classic EPLD 450 Gates 24 Macrocells 35ns | Altera/Intel
EP910LI-35Y

EP910LI-35Y - Classic EPLD 450 Gates 24 Macrocells 35ns | Altera/Intel

The Intel (formerly Altera) EP910LI-35Y is a member of the Altera Classic EPLD (Erasable Programmable Logic Device) family, fabricated on advanced CMOS technology to deliver high-speed, low-power logic integration in a 44-pin PLCC package. It integrates 450 usable gates and 24 macrocells with a worst-case propagation delay of 35 ns, making it one of the slowest (and therefore lowest-power) speed grades in the EP910 family. The device is offered in the industrial temperature range (the "I" suffix) and operates from a single 5 V supply. The "Y" suffix denotes a RoHS-compliant lead-free finish, while "L" identifies the low-power CMOS process option, and "35" indicates the 35 ns tpd speed grade. Architecture-wise, the EP910LI-35Y provides a programmable AND/OR array with shared logic expanders, a programmable macrocell flip-flop, and configurable output polarity, allowing designers to implement combinational and registered logic functions. The Altera Classic family is an early-generation programmable logic architecture that preceded the modern MAX series, designed for glue-logic, bus decoding, and state-machine replacement on 5 V systems. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines PAL-like AND/OR arrays with reprogrammable macrocells, offering a higher gate density than bipolar PALs while retaining non-volatile configuration. EPLDs belong to the broader hierarchy: programmable logic device (PLD) -> EPLD -> CMOS PLD -> Erasable PLD, sitting between simple PAL/GAL devices and modern CPLDs/FPGAs. Unlike SRAM-based FPGAs, Classic EPLDs retain their configuration in non-volatile memory and power up instantly to a known state, which simplifies system design in industrial controllers. Key features of the EP910LI-35Y include 24 macrocells (each with a flip-flop and I/O pin), 36 dedicated inputs, an internal feedback path that allows buried macrocell registers, and a programmable clock network. The device supports multiple I/O standards on its 24 I/O pins and includes a global clock input. The 44-pin PLCC (J-lead) package provides socket-friendly field upgrades, while the "I" industrial temperature grade covers -40 °C to +85 °C operation. The "Y" lead-free finish makes the part suitable for modern RoHS-compliant assemblies, although the underlying EP910 die is a mature 1980s-1990s architecture. Typical applications include 5 V glue logic replacement (decoders, multiplexers, comparators), address decoding in legacy microprocessor and microcontroller systems, industrial PLC interface logic, state-machine replacement in motor-control and instrumentation, and pin-compatible modernization of EP910-based designs where 35 ns timing is acceptable. The low-power "L" process makes the part attractive for power-sensitive systems that do not require higher speed grades (e.g., EP910LC-25 or EP910DC-25). When designing with the EP910LI-35Y, ensure that all inputs are properly terminated to avoid floating CMOS inputs and that the 5 V supply is well-decoupled with 0.1 µF ceramic capacitors close to VCC pins. Because the device is one of the older Classic EPLDs, programming is performed via legacy Altera programming hardware (e.g., the Altera Logic Programmer or compatible third-party tools) and the AHDL/ABEL hardware description languages that were current at the time of introduction. This page synthesizes distributor pricing, drop-in same-package alternatives from the EP910/EP610 family, and practical design notes not found in the original Altera datasheet.

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EP910LI-40 - 24 Macrocell CMOS EPLD, 40ns | Altera | PLCC-44
EP910LI-40

EP910LI-40 - 24 Macrocell CMOS EPLD, 40ns | Altera | PLCC-44

The Altera EP910LI-40 is a 24-macrocell Classic-series Erasable Programmable Logic Device (EPLD) fabricated on advanced CMOS technology and offered in a 44-pin PLCC package with a 40 ns propagation delay. The 'L' suffix denotes a low-power CMOS process variant, while the 'I' indicates the industrial operating temperature grade, making this device suitable for commercial and industrial control applications where power efficiency and -40C to +85C thermal tolerance are required. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines PAL-type AND-OR array logic with a programmable macrocell output stage. EPLDs sit in the broader hierarchy of programmable logic: simple PLD -> EPLD/CPLD -> FPGA. The EP910 family uses a unified architecture with a global programmable interconnect bus that ties 24 macrocells to 12 dedicated inputs and 24 bidirectional I/O pins, supporting up to 36 logic inputs and delivering 240 product terms for sum-of-products logic implementation. Erasable windowed packages allow design iteration via UV erasure, which was the standard development flow for this device family. Key features include 24 macrocells, 12 dedicated inputs, 24 I/O pins, 36 usable inputs, 240 product terms, a 40 ns tPD (pin-to-pin delay), and a low-power CMOS technology node. The PLCC-44 J-lead surface-mount package enables socketed programming and easy rework, an important feature for legacy designs still in production or maintenance. The device is non-volatile (UV-erasable) and supports JEDEC-standard programming algorithms via industry-standard PLD programmers. Typical applications include industrial control glue logic, address decoding and bus interface logic for legacy microprocessors (8086, 68000, Z80), state-machine controllers, peripheral chip replacement, and glue-logic consolidation in mixed-vintage PCB assemblies. The low-power CMOS 'L' variant is well suited to battery-backed or thermally-constrained enclosures where standard NMOS/CMOS EPLDs would exceed thermal budgets. When designing with this device, confirm programmer algorithm support because not all modern universal programmers retain the legacy Classic-series JEDEC file flow. For new designs, consider the modern equivalent EP910LC-40 or evaluate whether a low-density MAX II CPLD or CoolRunner-II family member offers equivalent logic density with lower power, in-system programmability, and a longer active lifecycle.

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EP910LI-40T - 24 Macrocells Classic EPLD, 40ns | Altera / Intel
EP910LI-40T

EP910LI-40T - 24 Macrocells Classic EPLD, 40ns | Altera / Intel

The Altera EP910LI-40T is a member of the Altera Classic EPLD (Erasable Programmable Logic Device) family, manufactured on advanced CMOS technology with a PAL-type architecture. It integrates 24 macrocells interconnected by a global programmable interconnect array, 12 dedicated inputs, and 24 bidirectional I/O lines, supporting up to 36 inputs and 24 outputs with 240 product terms distributed across the logic array. The "-40" speed grade denotes a 40 ns pin-to-pin propagation delay (tPD), and the "T" suffix denotes tape-and-reel packaging. The "L" grade indicates low-power CMOS operation, while "I" denotes the industrial operating temperature range of -40C to +85C. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that uses EPROM or EEPROM cells to store configuration, allowing the device to be erased with ultraviolet light and reprogrammed many times. EPLDs sit in the programmable logic hierarchy below modern CPLDs (Complex PLDs) and FPGAs, but they offer deterministic timing, low quiescent power, and simple development flows well suited to glue logic, state-machine replacement, and bus-interface decoding in legacy industrial systems. The EP910 family represents Altera's mid-density Classic tier above the EP610 and below the EP1800, providing balanced logic density for medium-complexity designs. Key features of the EP910LI-40T include 24 macrocells, 24 I/O pins, 12 dedicated inputs, 240 product terms, 40 ns tPD propagation delay, CMOS low-power technology, UV-erasable windowed ceramic or plastic package options, and JTAG-free programming via the Altera programming algorithm. The device operates from a single 5 V supply typical of TTL-era logic and is housed in a 40-pin ceramic DIP (J44) or PLCC (J68) package depending on suffix. Industrial temperature range (-40C to +85C) makes it suitable for factory automation and outdoor equipment. Typical applications include bus-interface decoding (address decoding for 8086, 68k, MIPS systems), state-machine replacement, custom peripheral controllers, vintage computer motherboard glue logic, and industrial control legacy equipment. Its deterministic 40 ns delay and 5 V CMOS compatibility make it ideal for replacing discrete 74LS/74HC logic arrays with a single integrated solution, simplifying PCB layout and reducing board area. When designing with the EP910LI-40T, engineers must use Altera's legacy MAX+PLUS II or AHDL development environment (modern Intel Quartus does not support Classic EPLDs), which requires Windows XP or DOS-era emulation. Programming requires a Master Programming Unit (MPU) or compatible third-party programmer, as the device predates JTAG and modern ISP interfaces. Designers should verify availability through authorized distributors as the Classic EPLD family has been NRND for over a decade.

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