EP910DI-35 vs EP910DC-40 비교
다음의 상세 나란히 비교: EP910DI-35 제조: Altera 및 EP910DC-40 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910DI-35 | EP910DC-40 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 활성 | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $35.20 | $13.95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Supply Current (ICC) | 40 mA typical | — |
| Dedicated Inputs | 10 | 12 |
| Bidirectional I/O Pins | 20 | 24 |
| Total Pins | 40 | — |
| 패키지 | CDIP-40 (Ceramic DIP with UV window) | DIP-40 (ceramic, through-hole) |
| 실장 유형 | Through-Hole | Through-Hole |
| 동작 온도 | -40C to +85C (industrial) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Programming Method | EPROM programmer + JEDEC fuse map | UV-erase + EPROM programmer; on-board logic test circuitry |
| Erasure Method | UV light through quartz window | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | [DATA_NEEDED: rohs_status] |
| Logic Family | PAL-type AND/OR array with D flip-flops | — |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | — |
| Device Family | — | Classic EPLD (EP910 series) |
| Architecture | — | PAL-type AND/OR, UV-erasable CMOS |
| Total Inputs to Logic Array | — | 36 |
| Product Terms | — | 240 maximum |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| 공급 전압 | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |