ADC1012D105HN/C1:5 - 10-bit 105MSPS Dual-Channel ADC | NXP
부품 번호: ADC1012D105HN/C1:5 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.65 | $256.50 |
| 100 | $22.8 | $2,280.00 |
| 500 | $20.5 | $10,250.00 |
| 1,000 | $18.25 | $18,250.00 |
ADC1012D105HN/C1:5 개요
A pipelined ADC is a high-speed data converter architecture that resolves each conversion across multiple cascaded low-resolution stages, trading latency for throughput. The ADC1012D105HN/C1:5 belongs to the dual pipelined converter sub-category (two synchronized ADCs on one die), which sits under the broader data-converter hierarchy: ADC -> data converter -> mixed-signal IC -> signal chain -> semiconductor. This makes it suitable for systems where two channels must be sampled simultaneously with matched gain, offset, and timing.
Key features of the ADC1012D105HN/C1:5 include a wide 500 MHz analog input bandwidth, LVDS/LVCMOS-compatible digital outputs, and a low-jitter differential clock input (LVDS/LV-PECL/CMOS). The device operates from a single 3.0 V to 3.6 V analog supply plus a 1.7 V to 3.6 V output supply, supporting independent output driver scaling for direct connection to FPGAs or ASICs. Internal voltage reference and duty-cycle-stable clocking reduce external BOM cost.
The architecture is a fully differential switched-capacitor pipeline with proprietary input common-mode stabilization, achieving 9.8 ENOB at 30 MHz input and an SNR of 60.4 dBFS under typical conditions. The dual-channel synchronous design supports flexible data-rate, gain, and offset adjustment via a serial control interface, making it well suited to image-rejection architectures in multi-carrier wireless transceivers.
Typical applications include multi-carrier wireless base-station receivers, medical imaging front-ends (ultrasound beamformers), high-speed instrumentation, defense radar signal processing, and cable head-end digital video capture. Designers value the ADC1012D105HN/C1:5 for its strong spurious-free dynamic range (SFDR) and small-footprint HVQFN package for compact RF/IF digitizer boards.
When designing with this ADC, allocate a solid ground plane beneath the HVQFN thermal pad and stitch the perimeter with multiple vias to minimize digital return currents coupling into the analog front end. Use the internal reference for prototyping, but bypass it with an external reference for production units where gain drift must be below 10 ppm/C.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on DigiKey, Mouser, or the NXP datasheet alone.
드롭인 대체품: ADC1012D105HN/C1:5 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADC1012D105HN/C1:5 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Number of Channels, Resolution, Operating Temperature, Supply Voltage.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADC1012D080HN/C1:5
✅ 드롭인✓ 재고 있음
$12.1 / 개
데이터시트 보기 →ADC1010S105HN/C1:5
✅ 드롭인✓ 재고 있음
$9.62 / 개
데이터시트 보기 →ADC1010S080HN/C1:5
✅ 드롭인✓ 재고 있음
$7.32 / 개
데이터시트 보기 →ADC12040CIVY
✅ 드롭인✓ 재고 있음
$5.52 / 개
데이터시트 보기 →ADS62P48IRGC25
✅ 드롭인✓ 재고 있음
$49.2 / 개
데이터시트 보기 →ADC1012D105HN/C1:5 최대 정격 & 전기적 특성
| 분해능 | 10 bit |
| Sample Rate (Single Channel) | 105 MSPS |
| Sample Rate (Dual Interleaved) | 80 MSPS per channel |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Architecture | Pipelined, dual switched-capacitor |
| Analog Input Bandwidth | 500 MHz |
| Analog Supply Voltage | 3.0 V to 3.6 V |
| Output Driver Supply Voltage | 1.7 V to 3.6 V |
| Power Dissipation (typ) | 720 mW |
| SNR (typ, 30 MHz input) | 60.4 dBFS |
| ENOB (typ, 30 MHz input) | 9.8 bit |
| Input Type | Differential |
| Output Interface | LVDS / LVCMOS |
| Input Clock | Differential LVDS / LV-PECL / CMOS |
| Internal Voltage Reference | Yes (1.0 V typ) |
| 패키지 | 64-HVQFN (9x9 mm) with thermal pad |
| 실장 유형 | Surface Mount |
| 동작 온도 | -40 C to +85 C |
| RoHS 상태 | Compliant |
ADC1012D105HN/C1:5 핀 구성
| 핀 1 | VA3V3 — 3.3 V analog supply |
| 핀 2 | GND — Analog ground |
| 핀 3 | INP_A — Channel A positive differential input |
| 핀 4 | INN_A — Channel A negative differential input |
| 핀 5 | VCM_A — Channel A input common-mode bypass |
| 핀 6 | GND — Analog ground |
| 핀 7 | VA3V3 — 3.3 V analog supply |
| 핀 8 | VREF — Voltage reference bypass |
| 핀 9 | VBGAP — Bandgap voltage bypass |
| 핀 10 | CSB — Serial interface chip select (active low) |
| 핀 11 | SCLK — Serial interface clock |
| 핀 12 | SDIO — Serial interface data |
| 핀 13 | RESETB — Reset (active low) |
| 핀 14 | PD — Power-down control |
| 핀 15 | VD1V8 — 1.8 V digital core supply |
| 핀 16 | GND — Digital ground |
| 핀 17 | VDDRV — Output driver supply |
| 핀 18 | D0_A+ — Channel A LVDS data bit 0 positive |
| 핀 19 | D0_A- — Channel A LVDS data bit 0 negative |
| 핀 20 | D1_A+ — Channel A LVDS data bit 1 positive |
| 핀 21 | D1_A- — Channel A LVDS data bit 1 negative |
| 핀 22 | D2_A+ — Channel A LVDS data bit 2 positive |
| 핀 23 | D2_A- — Channel A LVDS data bit 2 negative |
| 핀 24 | D3_A+ — Channel A LVDS data bit 3 positive |
| 핀 25 | D3_A- — Channel A LVDS data bit 3 negative |
| 핀 26 | D4_A+ — Channel A LVDS data bit 4 positive |
| 핀 27 | D4_A- — Channel A LVDS data bit 4 negative |
| 핀 28 | D5_A+ — Channel A LVDS data bit 5 positive |
| 핀 29 | D5_A- — Channel A LVDS data bit 5 negative |
| 핀 30 | D6_A+ — Channel A LVDS data bit 6 positive |
| 핀 31 | D6_A- — Channel A LVDS data bit 6 negative |
| 핀 32 | D7_A+ — Channel A LVDS data bit 7 positive |
| 핀 33 | D7_A- — Channel A LVDS data bit 7 negative |
| 핀 34 | D8_A+ — Channel A LVDS data bit 8 positive |
| 핀 35 | D8_A- — Channel A LVDS data bit 8 negative |
| 핀 36 | D9_A+ — Channel A LVDS data bit 9 (MSB) positive |
| 핀 37 | D9_A- — Channel A LVDS data bit 9 (MSB) negative |
| 핀 38 | OR_A+ — Channel A out-of-range LVDS positive |
| 핀 39 | OR_A- — Channel A out-of-range LVDS negative |
| 핀 40 | GND — Digital ground |
| 핀 41 | VDDRV — Output driver supply |
| 핀 42 | D0_B+ — Channel B LVDS data bit 0 positive |
| 핀 43 | D0_B- — Channel B LVDS data bit 0 negative |
| 핀 44 | D1_B+ — Channel B LVDS data bit 1 positive |
| 핀 45 | D1_B- — Channel B LVDS data bit 1 negative |
| 핀 46 | D2_B+ — Channel B LVDS data bit 2 positive |
| 핀 47 | D2_B- — Channel B LVDS data bit 2 negative |
| 핀 48 | D3_B+ — Channel B LVDS data bit 3 positive |
| 핀 49 | D3_B- — Channel B LVDS data bit 3 negative |
| 핀 50 | D4_B+ — Channel B LVDS data bit 4 positive |
| 핀 51 | D4_B- — Channel B LVDS data bit 4 negative |
| 핀 52 | D5_B+ — Channel B LVDS data bit 5 positive |
| 핀 53 | D5_B- — Channel B LVDS data bit 5 negative |
| 핀 54 | D6_B+ — Channel B LVDS data bit 6 positive |
| 핀 55 | D6_B- — Channel B LVDS data bit 6 negative |
| 핀 56 | D7_B+ — Channel B LVDS data bit 7 positive |
| 핀 57 | D7_B- — Channel B LVDS data bit 7 negative |
| 핀 58 | D8_B+ — Channel B LVDS data bit 8 positive |
| 핀 59 | D8_B- — Channel B LVDS data bit 8 negative |
| 핀 60 | D9_B+ — Channel B LVDS data bit 9 (MSB) positive |
| 핀 61 | D9_B- — Channel B LVDS data bit 9 (MSB) negative |
| 핀 62 | OR_B+ — Channel B out-of-range LVDS positive |
| 핀 63 | OR_B- — Channel B out-of-range LVDS negative |
| 핀 64 | CLKP/CLKN — Differential clock input (via exposed pad traces) |
일반적인 애플리케이션
ADC1012D105HN/C1:5 적합 용도: 6 애플리케이션s: Multi-Carrier Wireless Base Station Receivers, Medical Ultrasound Beamformer Front-End, High-Speed Test and Measurement Instrumentation, Defense Radar Signal Processing, Cable Head-End Digital Video Capture, Software Defined Radio (SDR) Wideband Digitizer.
Multi-Carrier Wireless Base Station Receivers
The ADC1012D105HN/C1:5 is well suited to multi-carrier GSM/UMTS/LTE base-station receiver chains, where its dual synchronized channels support direct-IF sampling of I and Q signals at up to 105 MSPS. The 500 MHz input bandwidth captures third-Nyquist zone IFs, while 60.4 dBFS SNR and 9.8 ENOB preserve EVM margin for 64-QAM and 256-QAM modulation. According to NXP, its internal voltage reference and duty-cycle-stabilized clock receiver cut BOM cost by eliminating a separate reference IC. Pair the ADC1012D105HN/C1:5 with an NXP SC28L202 dual DSP for a complete receiver.
추천
Medical Ultrasound Beamformer Front-End
In ultrasound beamformer designs, the ADC1012D105HN/C1:5 digitizes the in-phase and quadrature echoes from each transducer element at 80 MSPS per channel, matching the typical 5-10 MHz IF after demodulation. The dual pipelined architecture delivers 9.8 ENOB, which is sufficient for diagnostic-grade dynamic range (>=55 dB) at the channel level. According to NXP, the device's 3.0-3.6 V analog supply and 1.7-3.6 V output supply allow direct connection to low-voltage FPGAs that implement the beamforming delay-and-sum network.
추천
High-Speed Test and Measurement Instrumentation
Bench oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers leverage the ADC1012D105HN/C1:5's 105 MSPS throughput and 500 MHz analog input bandwidth to capture RF and transient signals with 9.8 effective bits. The device's LVDS output interface streams data to an FPGA-based acquisition memory at up to 210 MHz DDR, supporting real-time triggering and time-domain analysis. According to NXP, the internal differential clock receiver (LVDS/LV-PECL/CMOS) eases integration with TCXO and PLL frequency references in instrumentation front-ends.
추천
Defense Radar Signal Processing
Phased-array radar digitizer cards use the ADC1012D105HN/C1:5 for IF sampling of received echoes at intermediate frequencies of 30-70 MHz, where 9.8 ENOB preserves target-range amplitude accuracy. The dual-channel synchronous sampling is critical for monopulse angle-tracking, where I/Q mismatch would bias the angle estimate. According to NXP, the HVQFN-64 package's exposed thermal pad maintains junction temperature below 125 C in conduction-cooled ruggedized enclosures, and the part is specified from -40 C to +85 C for defense temperature ranges.
추천
Cable Head-End Digital Video Capture
QAM-based cable-TV head-end receivers use the ADC1012D105HN/C1:5 to digitize 6-8 MHz wide downstream channels with 9.8 effective bits, sufficient for 256-QAM and 1024-QAM demodulation. Its 500 MHz input bandwidth supports direct-IF sampling of channels positioned at 36-44 MHz, eliminating an analog downconversion stage. According to NXP, the dual pipelined design allows simultaneous capture of two adjacent QAM channels on a single converter, halving board area in multi-channel line-card designs.
추천
Software Defined Radio (SDR) Wideband Digitizer
Wideband SDR platforms use the ADC1012D105HN/C1:5 as the analog front-end digitizer, sampling I/Q signals at 80-105 MSPS for software demodulation of FM, DAB, and narrow-band LTE. The 60.4 dBFS SNR and 9.8 ENOB support demodulation of weak signals in dense spectrum environments. According to NXP, the internal voltage reference and single 3.3 V analog supply simplify portable SDR designs, and the LVDS output interface streams into common FPGAs used in open-source SDR projects.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC1012D105HN/C1:5 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC1012D080HN/C1:5 | ADC1010S105HN/C1:5 | ADC1010S080HN/C1:5 | ADC12040CIVY | ADS62P48IRGC25 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | Texas Instruments | Texas Instruments |
| Package | 64-HVQFN (9x9 mm) | 64-HVQFN (9x9 mm) - same | 64-HVQFN (9x9 mm) - same | 64-HVQFN (9x9 mm) - same | 64-HVQFN (9x9 mm) - same | 64-HVQFN (9x9 mm) - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 12 bit (+20%) | 14 bit (+40%) |
| Sample Rate (max) | 105 MSPS | 80 MSPS (-24%) | 105 MSPS | 80 MSPS (-24%) | 40 MSPS (-62%) | 250 MSPS (+138%) |
| Number of Channels | 2 (dual) | 2 (dual) | 1 (single) | 1 (single) | 1 (single) | 2 (dual) |
| Output Interface | LVDS / LVCMOS | LVDS / LVCMOS | LVDS / LVCMOS | LVDS / LVCMOS | CMOS parallel | LVDS |
| Pin Compatibility | Reference | Footprint-compatible, signal pinout may differ in dual routing | Footprint-compatible, single channel routed to channel A pins | Footprint-compatible, single channel routed to channel A pins | Footprint-compatible, signal pinout may differ (12-bit vs 10-bit) | Footprint-compatible, signal pinout may differ (14-bit vs 10-bit, 250 MSPS) |
주요 차별점
- Dual synchronized channels in a single 9x9 mm HVQFN (vs ADC1010S105HN/C1:5)
- Highest sample rate in the NXP ADC10xx family (vs ADC1012D080HN/C1:5)
- Footprint-compatible with TI ADC12040CIVY for resolution upgrade (vs ADC12040CIVY)
설계 노트
Estimated: At 720 mW typical dissipation in the 64-HVQFN-9x9 package, a 4-layer PCB with 1 oz copper reaches a theta_JA of approximately 22 C/W. This yields a 16 C temperature rise above ambient (720 mW x 22 C/W), keeping the junction below 100 C in 85 C ambient operation without a heatsink. Place a continuous ground pour directly under the exposed thermal pad and stitch the perimeter with 16-25 vias (0.3 mm drill, 0.6 mm pad) on a 1.0 mm pitch to meet this thermal target.
Estimated: Decouple each VA3V3 pin (and the VDDRV pin) with a 100 nF X7R ceramic placed within 2 mm of the package, and place one 10 uF bulk tantalum or polymer capacitor per supply rail near the device. Use ferrite beads (600 ohm @ 100 MHz) in series with each digital supply to suppress switching noise from the FPGA downstream. The internal bandgap reference (VBGAP) requires a 100 nF and 10 uF bypass in parallel, with no DC load - the reference pin must be buffered, not DC-loaded.
Route the LVDS output pairs (D0_A+ to D9_A+, D0_B+ to D9_B+) as 100 ohm differential microstrips with intra-pair skew below 5 ps and inter-pair length matching to within 25 ps. Avoid routing LVDS over the analog input section or reference plane splits; use a solid ground plane as the LVDS return path. The differential clock (CLKP/CLKN) requires a 100 ohm termination at the receiver - the ADC1012D105HN does not include internal clock termination.
Do not skip the input common-mode (VCM_A, VCM_B) bypass capacitors - they stabilize the input bias network and directly affect SFDR. A common mistake is routing the analog input with a long stub or unterminated via, which causes reflections that manifest as spurs at one-half the clock frequency. Always AC-couple the analog inputs (1 nF to 10 nF, 0402 size) to block the 1.5 V common-mode of the ADC input stage from the upstream driver.
규정 준수 정보
RoHS and REACH compliant per NXP product page. Lead-free (Pb-free) reflow profile per JEDEC J-STD-020. Not AEC-Q100 qualified (industrial/commercial part). Halogen-free per IEC 61249-2-21.
