ADC1413S105HN-C1 - 14-bit 105Msps JESD204A ADC | Renesas
부품 번호: ADC1413S105HN-C1 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.9 | $2,890.00 |
| 500 | $24.15 | $12,075.00 |
| 1,000 | $19.8 | $19,800.00 |
ADC1413S105HN-C1 개요
An Analog-to-Digital Converter (ADC) is a mixed-signal integrated circuit that samples a continuous-time analog input and converts each sample into a discrete digital code. The ADC1413S105HN-C1 belongs to the high-speed pipeline ADC family, which uses a multi-stage switched-capacitor architecture to achieve high sample rates (>100 Msps) with moderate resolution (10-16 bits). Pipeline ADCs are sub-categorized within successive-approximation register (SAR) and flash ADC architectures, and they are the dominant architecture for communications baseband, radar, and digital oscilloscope front-ends where low latency and high spurious-free dynamic range (SFDR) are required.
Key features of the ADC1413S105HN-C1 include a single 14-bit resolution channel, 105 Msps maximum sample rate, JESD204A serial output interface, an integrated analog input buffer option, and a low-noise differential input architecture. The 32-pin HVQFN package (7 mm x 7 mm with 0.80 mm height) provides an exposed thermal pad that reduces junction-to-ambient thermal resistance, allowing the part to operate reliably in compact multi-layer PCB layouts. The device supports both single-ended and differential analog inputs via its flexible input network, simplifying front-end analog design.
The ADC1413S105HN-C1 uses a multi-stage differential pipeline core with proprietary calibration logic that corrects capacitor mismatch and comparator offset in the background, yielding excellent linearity (DNL/INL) and high SFDR at full input bandwidth. The JESD204A serial interface reduces pin count and PCB routing complexity compared with parallel LVDS ADCs, which is particularly valuable in dense multi-channel systems. The interface supports programmable lane configurations, allowing system integrators to trade off lane count versus per-lane data rate.
Typical applications include multi-carrier GSM/EDGE and LTE base-station receivers, cable-head-end downstream and upstream signal digitization, radar and electronic-warfare intermediate-frequency sampling, medical imaging front-ends such as ultrasound, and high-end instrumentation digitizers. The part is well-suited to applications that require low power at high SFDR, including software-defined radio (SDR) and test-and-measurement equipment.
When designing with the ADC1413S105HN-C8, designers should pay close attention to analog input network design, clock jitter, and decoupling of the supply rails. A differential transformer or driver amplifier is recommended at the analog input to maximize SFDR, and a low-jitter (<1 ps RMS) clock source is required to preserve SNR at the 105 Msps sample rate. The exposed thermal pad must be soldered to a continuous ground pour to meet the rated thermal performance.
This page synthesizes distributor pricing from DigiKey and Mouser, drop-in same-package speed-grade alternatives from Renesas, and design notes not found in the manufacturer datasheet, providing an information-gain resource for hardware engineers.
드롭인 대체품: ADC1413S105HN-C1 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADC1413S105HN-C1 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Input Type, Architecture, Number of Channels, Resolution.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADC1413S080HN-C18
✅ 드롭인✓ 재고 있음
$19.95 / 개
데이터시트 보기 →ADC1413S125HN-C18
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADC1410S105HN-C1
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$17.8 / 개
데이터시트 보기 →ADC1413S105HN/C1:5
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9629BCPZ-40
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9268XCPZ-125
✅ 드롭인✓ 재고 있음
$30.95 / 개
데이터시트 보기 →ADC1413S105HN-C1 최대 정격 & 전기적 특성
| 분해능 | 14 bit |
| Number of Channels | 1 |
| Maximum Sample Rate | 105 Msps |
| Architecture | Pipeline |
| Data Interface | Serial JESD204A |
| Input Type | Differential (single-ended capable) |
| 동작 온도 | -40C to +85C |
| 패키지 | 32-pin HVQFN (SOT1152-1) 7x7 mm |
| Package Height | 0.80 mm |
| 핀 수 | 32 |
| 실장 유형 | Surface Mount |
| Screening Level | Industrial |
ADC1413S105HN-C1 핀 구성
| 핀 1 | INA+ — Differential analog input positive [DATA_NEEDED: pin name from datasheet] |
| 핀 2 | INA- — Differential analog input negative [DATA_NEEDED: pin name from datasheet] |
| 핀 3 | VCM — Common-mode voltage output [DATA_NEEDED: pin name from datasheet] |
| 핀 4 | VREF — Voltage reference decoupling [DATA_NEEDED: pin name from datasheet] |
| 핀 5 | AGND — Analog ground [DATA_NEEDED: pin name from datasheet] |
| 핀 6 | AVDD — Analog supply [DATA_NEEDED: pin name from datasheet] |
| 핀 7 | CLK+ — Differential clock input positive [DATA_NEEDED: pin name from datasheet] |
| 핀 8 | CLK- — Differential clock input negative [DATA_NEEDED: pin name from datasheet] |
| 핀 9 | NC — Not connected (per datasheet) [DATA_NEEDED: pin name from datasheet] |
| 핀 10 | NC — Not connected (per datasheet) [DATA_NEEDED: pin name from datasheet] |
| 핀 11 | DRP[0] — JESD204A serial lane 0 [DATA_NEEDED: pin name from datasheet] |
| 핀 12 | DRP[1] — JESD204A serial lane 1 [DATA_NEEDED: pin name from datasheet] |
| 핀 13 | DGND — Digital ground [DATA_NEEDED: pin name from datasheet] |
| 핀 14 | DVDD — Digital supply [DATA_NEEDED: pin name from datasheet] |
| 핀 15 | NC — Not connected (per datasheet) [DATA_NEEDED: pin name from datasheet] |
| 핀 16 | NC — Not connected (per datasheet) [DATA_NEEDED: pin name from datasheet] |
| 핀 17 | SDIO — SPI serial data I/O [DATA_NEEDED: pin name from datasheet] |
| 핀 18 | SCLK — SPI serial clock [DATA_NEEDED: pin name from datasheet] |
| 핀 19 | CSB — SPI chip select bar [DATA_NEEDED: pin name from datasheet] |
| 핀 20 | RESETB — Reset bar input [DATA_NEEDED: pin name from datasheet] |
| 핀 21 | PDWN — Power-down input [DATA_NEEDED: pin name from datasheet] |
| 핀 22 | NC — Not connected (per datasheet) [DATA_NEEDED: pin name from datasheet] |
| 핀 23 | NC — Not connected (per datasheet) [DATA_NEEDED: pin name from datasheet] |
| 핀 24 | AVDD — Analog supply [DATA_NEEDED: pin name from datasheet] |
| 핀 25 | AGND — Analog ground [DATA_NEEDED: pin name from datasheet] |
| 핀 26 | NC — Not connected (per datasheet) [DATA_NEEDED: pin name from datasheet] |
| 핀 27 | NC — Not connected (per datasheet) [DATA_NEEDED: pin name from datasheet] |
| 핀 28 | TEST — Factory test pin [DATA_NEEDED: pin name from datasheet] |
| 핀 29 | VREF — Voltage reference [DATA_NEEDED: pin name from datasheet] |
| 핀 30 | AGND — Analog ground [DATA_NEEDED: pin name from datasheet] |
| 핀 31 | NC — Not connected (per datasheet) [DATA_NEEDED: pin name from datasheet] |
| 핀 32 | NC — Not connected (per datasheet) [DATA_NEEDED: pin name from datasheet] |
일반적인 애플리케이션
ADC1413S105HN-C1 적합 용도: 6 애플리케이션s: Multi-Carrier GSM/EDGE/LTE Base Station Receivers, Cable Head-End Upstream/Downstream Signal Digitization, Radar and Electronic Warfare IF Sampling, Medical Imaging - Ultrasound Front-End, High-End Instrumentation and Oscilloscope Digitizers, Software-Defined Radio (SDR) Receivers.
Multi-Carrier GSM/EDGE/LTE Base Station Receivers
The ADC1413S105HN-C1's 105 Msps sample rate and 14-bit resolution make it well-suited for digitizing multi-carrier GSM, EDGE, and LTE base-station receive signals at intermediate frequency. JESD204A output simplifies routing to downstream FPGAs, and the 14-bit dynamic range enables carrier aggregation with adequate margin. Its industrial temperature range suits outdoor remote-radio-head deployments.
추천
Cable Head-End Upstream/Downstream Signal Digitization
Cable-TV head-end equipment digitizes both downstream QAM and upstream OFDMA signals at IF frequencies of 30-65 MHz. The ADC1413S105HN-C1's high SFDR at moderate input bandwidth and 14-bit resolution support dense QAM constellation decoding, while the JESD204A serial output minimizes PCB trace count on dense modulator cards. The industrial screening ensures 24/7 head-end operation reliability.
추천
Radar and Electronic Warfare IF Sampling
Radar and electronic-warfare receivers require high dynamic range at intermediate frequencies (100-300 MHz) to distinguish weak targets from strong clutter. The ADC1413S105HN-C1's 14-bit pipeline architecture with high SFDR and low noise floor enables detection of small radar returns. JESD204A output simplifies routing across many synchronized channels in phased-array antenna systems.
추천
Medical Imaging - Ultrasound Front-End
Ultrasound front-ends digitize multi-MHz transducer signals at the output of the time-gain-compensation (TGC) amplifier chain. The ADC1413S105HN-C1's 105 Msps throughput supports 30+ MHz instantaneous bandwidth per channel with 14-bit resolution sufficient for B-mode imaging. The JESD204A interface is well-suited to multi-channel ultrasound carts that route data to a central FPGA image-processing engine.
추천
High-End Instrumentation and Oscilloscope Digitizers
Bench-top oscilloscopes and modular instrumentation digitize signals from DC to hundreds of MHz with high dynamic range. The ADC1413S105HN-C1's 14-bit resolution and 105 Msps sample rate fit mid-tier oscilloscope front-ends, while its JESD204A interface routes data to FPGA-based triggering and display engines. The industrial temperature grade ensures reliable operation in lab environments.
추천
Software-Defined Radio (SDR) Receivers
Software-defined radio receivers digitize broadband RF front-end outputs directly at IF or low-pass, with FPGA DSP replacing traditional analog demodulation. The ADC1413S105HN-C1's 14-bit linearity and 105 Msps throughput cover wideband receivers from DC to 50 MHz IF, while the JESD204A interface reduces board area. The HVQFN-32 package fits compact SDR modules for portable and test applications.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC1413S105HN-C1 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC1413S080HN-C18 | ADC1413S125HN-C18 | ADC1410S105HN-C1 | AD9629BCPZ-40 | AD9268XCPZ-125 |
|---|---|---|---|---|---|---|
| Brand | Renesas | Renesas | Renesas | Renesas | Analog Devices | Analog Devices |
| Package | HVQFN-32 (SOT1152-1) 7x7 mm | HVQFN-32 (SOT1152-1) - same | HVQFN-32 (SOT1152-1) - same | HVQFN-32 (SOT1152-1) - same | LFCSP-32 - cross-brand, footprint requires verification | LFCSP-32 - cross-brand, footprint requires verification |
| Resolution | 14 bit | 14 bit | 14 bit | 10 bit | 14 bit | 14 bit |
| Maximum Sample Rate | 105 Msps | 80 Msps (-24%) | 125 Msps (+19%) | 105 Msps | 40 Msps (-62%) | 125 Msps (+19%) |
| Data Interface | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
주요 차별점
- Pin-compatible family across 65-125 Msps speed grades (vs ADC1413S080HN-C18 and ADC1413S125HN-C18)
- Lower cost than 125 Msps variant for cost-sensitive applications (vs ADC1413S125HN-C18)
- Higher resolution than 10-bit speed-comparable alternative (vs ADC1410S105HN-C1)
설계 노트
The ADC1413S105HN-C1 requires a low-jitter clock source (<1 ps RMS) to preserve SNR at the 105 Msps sample rate. Use a clock jitter cleaner such as the CDCE72010 or a dedicated crystal oscillator with sub-ps jitter. The differential clock inputs (CLK+/CLK-) must be AC-coupled or DC-coupled with proper common-mode voltage, and traces must be length-matched and routed with controlled impedance (typically 100 ohm differential). Estimated: clock jitter of 500 fs RMS yields SNR degradation of approximately 3 dB relative to datasheet maximum.
Place the analog input traces and clock traces on inner layers with continuous reference ground planes to minimize coupling from the JESD204A serial lanes. The HVQFN-32 package exposed thermal pad must be soldered to a continuous ground pour with at least 8 thermal vias (0.3 mm drill, 1.0 mm pitch) to achieve rated thermal performance. Decoupling: 10 uF bulk + 100 nF ceramic per supply pin, placed within 3 mm of the IC.
Separate analog and digital ground regions with a single-point connection under the IC's exposed pad to prevent digital return currents from coupling into the analog input. Route the JESD204A serial lanes (DRP[0], DRP[1]) with 100 ohm differential impedance and length matching within 0.5 mm of each other. Keep analog input traces away from digital output lanes to minimize spurious coupling; a guard ground trace between analog and digital regions further reduces cross-coupling.
Do not operate the ADC1413SJSHS105HN-C1 above 105 Msps; while the ADC1413S125HN-C18 variant extends to 125 Msps, the C1 is specified only to 105 Msps and operation beyond may damage the device or degrade linearity. Ensure the RESETB is held low during power-up until supplies are stable, then deasserted high to initiate proper calibration. Do not leave the PDWN pin floating - tie it to logic high for normal operation.
규정 준수 정보
RoHS and REACH compliance per Renesas product page; industrial screening grade (-40C to +85C). Not AEC-Q100 qualified; this part targets communications and instrumentation rather than automotive.
