ADS5546IRGZ25 - 14-Bit 190 MSPS ADC, LVDS/CMOS | Texas Instruments
부품 번호: ADS5546IRGZ25 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.65 | $346.50 |
| 100 | $30.8 | $3,080.00 |
| 500 | $27.55 | $13,775.00 |
| 1,000 | $24.95 | $24,950.00 |
ADS5546IRGZ25 개요
What is a high-speed pipelined ADC? A pipelined analog-to-digital converter (ADC) is a type of data converter that achieves high sample rates by dividing the conversion task into multiple cascaded low-resolution stages, each stage producing a sub-ADC result before passing a residue to the next stage. Within the broader hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Pipelined ADCs sit at the top of the speed-resolution pyramid and dominate communications, instrumentation, and imaging markets.
Key features of the ADS5546IRGZ25 include a maximum sample rate of 190 MSPS, 14-bit resolution with no missing codes, 73.2-dBFS SNR at 70-MHz IF input, and 87-dBc SFDR at the same IF with 0 dB gain. Total power dissipation is 1.1 W when operating at full sample rate, with an internal sample-and-hold front end and Double Data Rate (DDR) LVDS outputs that halve the output bus width compared to CMOS.
Architecturally, the device uses a multi-stage pipelined core with proprietary error correction to guarantee no-missing-codes performance across the full operating range. The selectable LVDS/CMOS output interface is configurable per design, allowing designers to trade off I/O count against signal integrity and board complexity. A 3.3V analog supply and an internal reference simplify board design.
Typical applications include multi-carrier wireless base-station receivers, test and measurement digitizers, medical ultrasound beamformers, defense radar digitizers, and high-speed data acquisition front ends. The wide input bandwidth and excellent linearity also suit software-defined radio (SDR) platforms and high-end oscilloscope front ends.
When designing with this converter, allocate a low-noise 3.3V LDO for AVDD, enforce strict ground partitioning between analog and digital grounds joined only under the EPAD, and use controlled-impedance differential routing for the analog input. Decouple each supply pin with a 0.1 uF ceramic plus a 10 uF bulk capacitor to preserve SNR.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers evaluate the ADS5546IRGZ25 for production designs.
드롭인 대체품: ADS5546IRGZ25 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADS5546IRGZ25 (동일 폼 팩터 및 풋프린트) — 차이점: Package, SFDR, SNR, Input Type, Operating Temperature Range.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADS5546IRGZR
✅ 드롭인✓ 재고 있음
$24.95 / 개
데이터시트 보기 →ADS5547IRGZ25
✅ 드롭인✓ 재고 있음
$24.5 / 개
데이터시트 보기 →ADS5547IRGZR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS5545IRGZ25
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ADS5546IRGZT
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ADS5546IRGZTG4
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS5546IRGZ25 최대 정격 & 전기적 특성
| 분해능 | 14 bit |
| Sample Rate (Max) | 190 MSPS |
| Number of Inputs | 1 |
| Architecture | Pipelined |
| Input Type | Differential |
| SNR | 73.2 dBFS at 70 MHz IF |
| SFDR | 87 dBc at 70 MHz IF, 0 dB gain |
| Total Power Dissipation | 1.1 W |
| Missing Codes | None (no missing codes guaranteed) |
| Output Interface | DDR LVDS / Parallel CMOS (selectable) |
| Analog Supply Voltage | 3.3 V |
| 동작 온도 범위 | -40 C to +85 C |
| 패키지 | 48-VQFN (7x7 mm) with exposed pad |
| 실장 유형 | Surface Mount |
| MSL 레벨 | 3 |
| RoHS 상태 | Compliant |
ADS5546IRGZ25 핀 구성
| 핀 1 | DRVDD — Digital output driver supply (3.3V) |
| 핀 2 | GND — Ground |
| 핀 3 | D0+/CMOS_D0 — LVDS data output pair 0 positive / CMOS D0 |
| 핀 4 | D0-/CMOS_DGND — LVDS data output pair 0 negative / CMOS D-GND reference |
| 핀 5 | D1+/CMOS_D1 — LVDS data output pair 1 positive / CMOS D1 |
| 핀 6 | D1-/CMOS_DGND — LVDS data output pair 1 negative / CMOS D-GND reference |
| 핀 7 | D2+/CMOS_D2 — LVDS data output pair 2 positive / CMOS D2 |
| 핀 8 | D2-/CMOS_DGND — LVDS data output pair 2 negative / CMOS D-GND reference |
| 핀 9 | D3+/CMOS_D3 — LVDS data output pair 3 positive / CMOS D3 |
| 핀 10 | D3-/CMOS_DGND — LVDS data output pair 3 negative / CMOS D-GND reference |
| 핀 11 | D4+/CMOS_D4 — LVDS data output pair 4 positive / CMOS D4 |
| 핀 12 | D4-/CMOS_DGND — LVDS data output pair 4 negative / CMOS D-GND reference |
| 핀 13 | D5+/CMOS_D5 — LVDS data output pair 5 positive / CMOS D5 |
| 핀 14 | D5-/CMOS_DGND — LVDS data output pair 5 negative / CMOS D-GND reference |
| 핀 15 | D6+/CMOS_D6 — LVDS data output pair 6 positive / CMOS D6 |
| 핀 16 | D6-/CMOS_DGND — LVDS data output pair 6 negative / CMOS D-GND reference |
| 핀 17 | DRVDD — Digital output driver supply (3.3V) |
| 핀 18 | GND — Ground |
| 핀 19 | CLKOUT+ — Clock output positive (data-rate clock) |
| 핀 20 | CLKOUT- — Clock output negative |
| 핀 21 | D7+/CMOS_D7 — LVDS data output pair 7 positive / CMOS D7 |
| 핀 22 | D7-/CMOS_DGND — LVDS data output pair 7 negative / CMOS D-GND reference |
| 핀 23 | D8+/CMOS_D8 — LVDS data output pair 8 positive / CMOS D8 |
| 핀 24 | D8-/CMOS_DGND — LVDS data output pair 8 negative / CMOS D-GND reference |
| 핀 25 | D9+/CMOS_D9 — LVDS data output pair 9 positive / CMOS D9 |
| 핀 26 | D9-/CMOS_DGND — LVDS data output pair 9 negative / CMOS D-GND reference |
| 핀 27 | D10+/CMOS_D10 — LVDS data output pair 10 positive / CMOS D10 |
| 핀 28 | D10-/CMOS_DGND — LVDS data output pair 10 negative / CMOS D-GND reference |
| 핀 29 | D11+/CMOS_D11 — LVDS data output pair 11 positive / CMOS D11 |
| 핀 30 | D11-/CMOS_DGND — LVDS data output pair 11 negative / CMOS D-GND reference |
| 핀 31 | D12+/CMOS_D12 — LVDS data output pair 12 positive / CMOS D12 |
| 핀 32 | D12-/CMOS_DGND — LVDS data output pair 12 negative / CMOS D-GND reference |
| 핀 33 | D13+/CMOS_D13 — LVDS data output pair 13 positive / CMOS D13 |
| 핀 34 | D13-/CMOS_DGND — LVDS data output pair 13 negative / CMOS D-GND reference |
| 핀 35 | GND — Ground |
| 핀 36 | DRVDD — Digital output driver supply (3.3V) |
| 핀 37 | CLKM — Differential clock input negative |
| 핀 38 | CLKP — Differential clock input positive |
| 핀 39 | GND — Ground |
| 핀 40 | AVDD — Analog supply (3.3V) |
| 핀 41 | AINN — Differential analog input negative |
| 핀 42 | AINP — Differential analog input positive |
| 핀 43 | VCM — Common-mode voltage output (analog input bias) |
| 핀 44 | AVDD — Analog supply (3.3V) |
| 핀 45 | REFM — Reference decoupling (-) / bottom of internal reference ladder |
| 핀 46 | REFP — Reference decoupling (+) / top of internal reference ladder |
| 핀 47 | AVDD — Analog supply (3.3V) |
| 핀 48 | RESET — Reset / synchronization input |
일반적인 애플리케이션
ADS5546IRGZ25 적합 용도: 7 애플리케이션s: Multi-Carrier Wireless Base-Station Receiver, Test and Measurement Digitizer Front End, Medical Ultrasound Beamformer Receive Path, Defense Radar and EW Digitizer, High-Speed Data Acquisition Card, Software-Defined Radio (SDR) IF Sampling, Portable Spectrum Analyzer Front End.
Multi-Carrier Wireless Base-Station Receiver
The ADS5546IRGZ25 is well matched to multi-carrier base-station receiver IF sampling because the 14-bit, 190 MSPS pipeline delivers 73.2-dBFS SNR and 87-dBc SFDR at a 70-MHz IF, which is sufficient to digitize multiple WCDMA/LTE carriers placed across a 60 MHz IF bandwidth without dynamic range loss. The DDR LVDS output bus minimizes the number of FPGA pin pairs needed, easing routing on congested receiver boards. With 1.1 W dissipation in a 7x7 mm VQFN, the converter fits dense 4x4 or 8x8 remote-radio-head designs where board real estate is scarce. Designers typically place a low-noise 3.3V LDO such as TPS7A4701 or TPS7A3301 upstream to preserve SNR.
추천
Test and Measurement Digitizer Front End
Bench-top and modular digitizers benefit from the ADS5546IRGZ25's 190 MSPS sample rate and 14-bit resolution, capturing signals up to the Nyquist frequency of 95 MHz with linearity sufficient for oscilloscope, spectrum analyzer, and arbitrary-waveform-recorder front ends. The 87-dBc SFDR at 70 MHz IF supports spurious-free dynamic range needed in production-test equipment. The selectable CMOS output mode simplifies use with lower-cost FPGA or DSP back ends, while the LVDS mode suits high-channel-count modular instruments. Care must be taken to enforce analog/digital ground separation and provide a stable low-jitter clock from a TCXO or PLL such as LMK04803.
추천
Medical Ultrasound Beamformer Receive Path
The ADS5546IRGZ25 is widely used in medical ultrasound receiver arrays because the 14-bit resolution and 190 MSPS sample rate comfortably satisfy the bandwidth and dynamic-range requirements of beamformer channels operating at 10-15 MHz center frequencies. The pipelined architecture's low latency suits real-time beam steering, and the LVDS output packs the ADC's full 14-bit data plus a frame flag into a compact DDR interface that is easily aggregated across 16, 32, 64, or 128 channels. The 1.1 W dissipation is acceptable within a multi-channel chassis with forced-air cooling. Heisener distributor listings confirm 3,568-piece stock as of 2026-10-11 for production builds.
추천
Defense Radar and EW Digitizer
Defense and electronic-warfare digitizers benefit from the ADS5546IRGZ25's 190 MSPS sample rate and excellent wideband linearity, capturing intermediate-frequency radar returns where 14-bit dynamic range and high SFDR matter most. The differential analog input accepts signal-source impedances easily driven by a balun or a fully-differential amplifier such as the THS4509. The DDR LVDS output reduces FPGA pin count, allowing compact PCI-Express or VPX module layouts. Across -40 C to +85 C operation the device meets industrial-grade environmental specs suitable for vehicle-mounted and shipboard platforms.
추천
High-Speed Data Acquisition Card
Modular data acquisition cards for industrial and laboratory use leverage the ADS5546IRGZ25's 190 MSPS throughput to digitize transient signals from sensors, photodiodes, or accelerometers. The 14-bit resolution provides >84 dB theoretical dynamic range, which combined with 87-dBc SFDR gives clean spectral captures of wideband signals. Pipelined ADCs like this also exhibit low kickback and low aperture jitter, simplifying front-end analog design versus older flash or successive-approximation architectures. The 48-VQFN exposed pad eases PCB thermal management in sealed card-edge modules.
추천
Software-Defined Radio (SDR) IF Sampling
Software-defined radio platforms use the ADS5546IRGZ25 to digitize IF stages between 30 and 90 MHz, enabling a single ADC to cover wide tuning ranges for amateur, commercial, and military waveforms. The combination of 73.2-dBFS SNR and 87-dBc SFDR at 70 MHz provides sufficient dynamic range for narrowband demodulation while sharing the front end across multiple modes. The selectable CMOS or DDR LVDS output allows integration with low-cost FPGA-based SDR boards or higher-performance DSP/FPGA designs. Care should be taken to place the ADC clock source close to the device to minimize aperture-jitter-induced SNR degradation.
추천
Portable Spectrum Analyzer Front End
Portable spectrum analyzers and RF test gear between 9 kHz and 95 MHz use the ADS5546IRGZ25's 190 MSPS rate to directly digitize analyzer IF bands without analog preselectors. The 14 bits and 87-dBc SFDR are sufficient for analyzer amplitude accuracy of approximately +/-0.5 dB at 70 MHz. The 1.1 W dissipation is reasonable for battery-powered analyzer designs, while the small 7x7 mm VQFN footprint leaves room for additional signal-conditioning circuitry. The selectable LVDS/CMOS output tailors the data interface to low-power or high-channel-count architectures.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADS5546IRGZ25 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADS5546IRGZR | ADS5547IRGZ25 | ADS5545IRGZ25 | ADS5546IRGZT | ADS5546IRGZTG4 |
|---|---|---|---|---|---|---|
| Package | 48-VQFN (7x7) | 48-VQFN (7x7) - same | 48-VQFN (7x7) - same | 48-VQFN (7x7) - same | 48-VQFN (7x7) - same | 48-VQFN (7x7) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Sample Rate | 190 MSPS | 190 MSPS | 210 MSPS | 170 MSPS | 190 MSPS | 190 MSPS |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Output Interface | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Packaging Form | Tray | Tape & Reel | Tray | Tray | Small Reel | Tape & Reel (Pb-free grade) |
주요 차별점
- Tray packaging optimized for engineering builds (vs ADS5546IRGZR)
- 190 MSPS sample rate occupies family mid-range (vs ADS5547IRGZ25 and ADS5545IRGZ25)
- DDR LVDS output reduces FPGA pin count (vs Most competitor ADCs with parallel CMOS only)
설계 노트
Use a low-noise LDO such as TPS7A4701 for the 3.3V AVDD rail. Decouple each supply pin with a 0.1 uF X7R ceramic placed within 3 mm of the pin, plus a 10 uF bulk capacitor. Separate analog (AVDD) and digital (DRVDD) supply domains should be powered from independent LDOs to prevent digital switching noise from coupling into the analog front end and degrading SNR.
Estimated: at 1.1 W dissipation in the 48-VQFN (7x7), with a typical theta_JA of about 28 C/W on a 4-layer JEDEC test board, the junction temperature rise is approximately 31 C above ambient. With a 85 C upper ambient rating this yields a max junction near 116 C, comfortably below the 150 C datasheet limit, but a continuous-duty application in a sealed enclosure may require additional PCB copper area or airflow.
Enforce strict ground partitioning with a single connection point between analog and digital grounds, ideally under or near the exposed pad (EP). Use controlled-impedance differential routing (100 ohm differential) for AINP/AINN and CLKP/CLKM, keeping trace lengths matched within 0.13 mm to preserve SNR. Place the VCM bypass capacitor (0.1 uF) adjacent to the VCM pin to provide a stable common-mode bias for the analog input stage.
Do not exceed the absolute maximum analog input of +/-2 V or apply DC before the part is powered; a 50 ohm termination at the analog input is recommended. The RESET pin must be de-asserted only after AVDD is stable, and clock sources must have low phase noise (below 1 ps RMS jitter) to avoid degrading SNR. Use a high-performance clock generator such as LMK04803 if the system oscillator is not adequate.
Match the lengths of all LVDS output pairs to within the timing budget of your FPGA. Keep DDR LVDS traces at 100-ohm differential impedance and avoid sharp 90-degree bends; use rounded or 45-degree bends instead. If using CMOS mode, add 22-33 ohm series resistors to dampen reflections on the longer parallel bus; LVDS mode typically does not need series resistors due to its current-mode drivers.
규정 준수 정보
Texas Instruments confirms RoHS and REACH compliance per the TI ADS5546 datasheet and product page. The part is not AEC-Q100 qualified - for automotive applications use the qualified version if available, or consult TI for an automotive-grade equivalent. The Z25 suffix denotes tray packaging but is fully Pb-free/lead-free.
