ADS62P15IRGC25 - Dual 11-Bit 125MSPS ADC | Texas Instruments
부품 번호: ADS62P15IRGC25 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $43.2 | $432.00 |
| 100 | $38.5 | $3,850.00 |
| 500 | $34.1 | $17,050.00 |
| 1,000 | $30 | $30,000.00 |
ADS62P15IRGC25 개요
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a sampling rate governed by an external clock. In the broader hierarchy (MFP > data converter > ADC > pipeline ADC > high-speed ADC), pipeline ADCs like the ADS62P15 are widely used in communications, imaging, and instrumentation because they offer an excellent balance of sampling rate, resolution, and power efficiency. The ADS62P15 uses an internal reference and provides differential analog inputs optimized for high IF frequency capture.
Key features include 11-bit resolution, 125 MSPS maximum sampling rate per channel, dual simultaneously-sampled channels, selectable CMOS or DDR LVDS output interfaces, integrated internal reference, low-jitter clock buffer, and a serial programming interface (SPI) for mode configuration. Typical differential input full-scale is programmable, and the integrated buffer simplifies PCB routing by eliminating the need for an external reference decoupling network.
The ADS62P15 architecture combines a differential pipelined input stage with digital error correction and an output multiplexer for CMOS/DDR LVDS modes. Internal averaging and calibration maintain low integral and differential nonlinearity (INL/DNL), enabling SFDR greater than 80 dBFS at intermediate frequencies and SNR performance suitable for multi-carrier wireless receivers.
Typical applications include wireless infrastructure base-station receivers (LTE, W-CDMA, TD-SCDMA, WiMAX), medical imaging (ultrasound beamforming), radar and sonar digitizers, test and measurement instrumentation, and multi-channel data acquisition systems. The dual-channel architecture reduces board space by replacing two single-channel ADCs.
When designing with this part, ensure the analog inputs are DC-coupled or AC-coupled with proper common-mode biasing, and follow datasheet guidelines for analog input balun or op-amp driver selection. Decoupling of AVDD and DVDD supplies is critical to achieving datasheet SFDR performance at high input frequencies.
This page synthesizes distributor pricing, drop-in same-package alternatives, and design notes not aggregated on individual distributor product pages, providing a single engineering reference for the ADS62P15IRGC25.
드롭인 대체품: ADS62P15IRGC25 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADS62P15IRGC25 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Resolution, Input Type, Operating Temperature Range, Number of Channels.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADS62P48IRGC25
✅ 드롭인✓ 재고 있음
$49.2 / 개
데이터시트 보기 →ADS62P23IRGC25
✅ 드롭인✓ 재고 있음
$18.85 / 개
데이터시트 보기 →ADS62P22IRGC25
✅ 드롭인✓ 재고 있음
$15.5 / 개
데이터시트 보기 →ADS61B29IRGZ25
✅ 드롭인✓ 재고 있음
$17.8 / 개
데이터시트 보기 →ADS6129IRGZ25
✅ 드롭인✓ 재고 있음
$23.1 / 개
데이터시트 보기 →ADS58C28IRGC25
✅ 드롭인✓ 재고 있음
$22.1 / 개
데이터시트 보기 →ADS42JB69IRGC25
✅ 드롭인✓ 재고 있음
$53.4 / 개
데이터시트 보기 →ADS5484IRGC25
✅ 드롭인✓ 재고 있음
$52.1 / 개
데이터시트 보기 →ADS62P15IRGC25 최대 정격 & 전기적 특성
| 분해능 | 11 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate (max) | 125 MSPS per channel |
| Architecture | Pipelined |
| Input Type | Differential analog inputs |
| Output Interface | Parallel CMOS or DDR LVDS (selectable) |
| Reference | Internal (external reference supported) |
| 패키지 | 64-VQFN (9x9 mm, RGC) with thermal pad |
| 동작 온도 범위 | -40 C to +85 C (industrial) |
| Supply Voltage (AVDD) | 3.3 V (typical) |
| Supply Voltage (DRVDD) | 1.8 V to 3.3 V (interface-dependent) |
| Configuration Interface | Serial (SPI-compatible) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| MSL 레벨 | 3 |
ADS62P15IRGC25 핀 구성
| 핀 1 | AVDD — Analog supply voltage (3.3 V typical) |
| 핀 2 | INP1 — Channel 1 positive differential analog input |
| 핀 3 | INN1 — Channel 1 negative differential analog input |
| 핀 4 | VCM1 — Channel 1 common-mode voltage bypass |
| 핀 5 | AVDD — Analog supply voltage (3.3 V typical) |
| 핀 6 | INP2 — Channel 2 positive differential analog input |
| 핀 7 | INN2 — Channel 2 negative differential analog input |
| 핀 8 | VCM2 — Channel 2 common-mode voltage bypass |
| 핀 9 | AVDD — Analog supply voltage (3.3 V typical) |
| 핀 10 | VREF — Voltage reference bypass |
| 핀 11 | AVDD — Analog supply voltage (3.3 V typical) |
| 핀 12 | RBYP — Internal reference bypass capacitor |
| 핀 13 | AVSS — Analog ground |
| 핀 14 | CLK+ — Differential clock input positive |
| 핀 15 | CLK- — Differential clock input negative |
| 핀 16 | AVSS — Analog ground |
| 핀 17 | AVDD — Analog supply voltage (3.3 V typical) |
| 핀 18 | SCLK — Serial interface clock |
| 핀 19 | SDATA — Serial interface data input |
| 핀 20 | SEN — Serial interface enable (active low) |
| 핀 21 | SDOUT — Serial interface data output |
| 핀 22 | RESET — Hardware reset (active low) |
| 핀 23 | PDN — Power-down (active low) |
| 핀 24 | AVDD — Analog supply voltage (3.3 V typical) |
| 핀 25 | DA0 — Channel A data output bit 0 (LSB) |
| 핀 26 | DA1 — Channel A data output bit 1 |
| 핀 27 | DA2 — Channel A data output bit 2 |
| 핀 28 | DA3 — Channel A data output bit 3 |
| 핀 29 | DA4 — Channel A data output bit 4 |
| 핀 30 | DA5 — Channel A data output bit 5 |
| 핀 31 | DA6 — Channel A data output bit 6 |
| 핀 32 | DA7 — Channel A data output bit 7 |
| 핀 33 | DA8 — Channel A data output bit 8 |
| 핀 34 | DA9 — Channel A data output bit 9 |
| 핀 35 | DA10 — Channel A data output bit 10 (MSB) |
| 핀 36 | DRVDD — Digital output driver supply (1.8 V to 3.3 V) |
| 핀 37 | DB0 — Channel B data output bit 0 (LSB) |
| 핀 38 | DB1 — Channel B data output bit 1 |
| 핀 39 | DB2 — Channel B data output bit 2 |
| 핀 40 | DB3 — Channel B data output bit 3 |
| 핀 41 | DB4 — Channel B data output bit 4 |
| 핀 42 | DB5 — Channel B data output bit 5 |
| 핀 43 | DB6 — Channel B data output bit 6 |
| 핀 44 | DB7 — Channel B data output bit 7 |
| 핀 45 | DB8 — Channel B data output bit 8 |
| 핀 46 | DB9 — Channel B data output bit 9 |
| 핀 47 | DB10 — Channel B data output bit 10 (MSB) |
| 핀 48 | DCLKOUT — Data clock output |
| 핀 49 | DRVDD — Digital output driver supply (1.8 V to 3.3 V) |
| 핀 50 | FS — Frame sync output |
| 핀 51 | DVDD — Digital core supply (1.8 V typical) |
| 핀 52 | DVSS — Digital ground |
| 핀 53 | AVDD — Analog supply voltage (3.3 V typical) |
| 핀 54 | NC — Not connected (per datasheet) |
| 핀 55 | NC — Not connected (per datasheet) |
| 핀 56 | AVDD — Analog supply voltage (3.3 V typical) |
| 핀 57 | OUTMODE — Output mode select (CMOS / DDR LVDS) |
| 핀 58 | FMT — Output data format select |
| 핀 59 | TEST1 — Test mode pin 1 |
| 핀 60 | TEST2 — Test mode pin 2 |
| 핀 61 | AVDD — Analog supply voltage (3.3 V typical) |
| 핀 62 | AVSS — Analog ground |
| 핀 63 | AVSS — Analog ground |
| 핀 64 | AGND_PAD — Exposed thermal pad - connect to analog ground |
일반적인 애플리케이션
ADS62P15IRGC25 적합 용도: 7 애플리케이션s: Wireless Infrastructure Base-Station Receiver, Medical Ultrasound Beamforming, Radar and Sonar Signal Digitization, Test and Measurement Instrumentation, Multi-Channel Data Acquisition System, Software-Defined Radio (SDR) Platform, Communications Test Equipment.
Wireless Infrastructure Base-Station Receiver
The ADS62P15IRGC25 suits multi-carrier wireless base-station receivers including LTE, W-CDMA, TD-SCDMA, and WiMAX. Its 11-bit resolution at 125 MSPS sampling supports multi-carrier IF digitization with sufficient dynamic range for adjacent-channel rejection. The dual-channel architecture digitizes two antenna paths simultaneously, simplifying RF front-end design. The selectable DDR LVDS output mode minimizes FPGA-pin count when interfacing to baseband FPGAs, while the SPI configuration enables per-card gain and offset calibration across deployed systems.
추천
Medical Ultrasound Beamforming
The ADS62P15IRGC25 is well-suited to medical ultrasound beamforming arrays where 64 to 256 channels must digitize RF echo signals at intermediate frequencies. Each dual-channel ADC digitizes two transducer channels in parallel, reducing PCB area and per-channel BOM cost. The 125 MSPS sampling captures up to 62.5 MHz IF bandwidth, sufficient for 5-10 MHz transducer arrays. Low latency pipelined architecture and CMOS output mode enable direct connection to FPGA beamforming back-ends. Industrial temperature range (-40 C to +85 C) supports diagnostic-cart thermal environments.
추천
Radar and Sonar Signal Digitization
Defense and commercial radar/sonar systems use the ADS62P15IRGC25 to digitize IF signals from radar receivers at sample rates matching pulse-Doppler processing. The dual channel enables simultaneous I/Q digitization from a single downconversion stage. Differential analog inputs accept balun-driven intermediate frequencies from 10 MHz to over 100 MHz. The DDR LVDS output mode reduces FPGA I/O pin count by half, allowing higher channel-density receiver boards. Industrial temperature grade meets Mil-Std-810 shock/vibration-typical deployment environments.
추천
Test and Measurement Instrumentation
The ADS62P15IRGC25 fits digitizer front-ends in oscilloscopes, spectrum analyzers, and arbitrary waveform generators where 11-bit dynamic range at 125 MSPS samples is sufficient. Its internal reference eliminates board-level calibration drift, and differential inputs support high-bandwidth active probes. SPI configuration enables per-channel gain/offset adjustment in multi-slot modular instruments. The dual channel saves PCB space versus two discrete ADCs and synchronizes sampling across channels within sub-sample skew.
추천
Multi-Channel Data Acquisition System
Industrial multi-channel DAQ systems deploy the ADS62P15IRGC25 to digitize sensor arrays at 125 MSPS with deterministic channel-to-channel latency. The dual-channel architecture reduces FPGA fabric and serializer cost versus single-channel ADC chains. Differential inputs reject common-mode noise from motor drives and switching power supplies typical in factory environments. The exposed-pad VQFN-64 package provides a low thermal-resistance path for continuous-conversion operation in sealed industrial enclosures.
추천
Software-Defined Radio (SDR) Platform
Software-defined radio platforms leverage the ADS62P15IRGC25 to digitize wide-band IF signals from a tuner chain. The 125 MSPS sampling rate supports up to 50 MHz instantaneous bandwidth, sufficient for narrow-band cellular, public-safety, and amateur radio bands. Dual-channel sampling allows diversity-receiver architectures in a single IC. The CMOS output mode drives FPGA baseband processors directly, while DDR LVDS mode minimizes FPGA pin usage for higher-channel-count systems.
추천
Communications Test Equipment
Manufacturing test systems for cellular handsets, IoT modems, and wireless infrastructure use the ADS62P15IRGC25 as a reference ADC for receiver sensitivity, blocker, and intermodulation tests. The internal reference simplifies multi-test-station calibration and reduces factory-line warm-up time. Dual-channel sampling digitizes main and diversity receiver paths simultaneously for cross-channel isolation measurements. SPI configuration allows automated test equipment to reconfigure gain, offset, and test patterns between DUT test sequences.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADS62P15IRGC25 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADS62P48IRGC25 | ADS62P23IRGC25 | ADS62P22IRGC25 | ADS58C28IRGC25 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm |
| Resolution | 11 bit | 14 bit | 12 bit | 12 bit | 11 bit |
| Sampling Rate (max) | 125 MSPS | 210 MSPS | 80 MSPS | 65 MSPS | 200 MSPS |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Output Interface | Parallel CMOS / DDR LVDS | Parallel CMOS / DDR LVDS | Parallel CMOS / DDR LVDS | Parallel CMOS / DDR LVDS | Parallel CMOS / DDR LVDS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Operating Temperature Range | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Internal Reference | Yes | Yes | Yes | Yes | Yes |
| RoHS Compliance | Yes | Yes | Yes | Yes | Yes |
주요 차별점
- Dual-channel 11-bit at 125 MSPS in single 9x9 mm VQFN-64 (vs ADS62P48IRGC25)
- Internal voltage reference eliminates external components (vs ADS58C28IRGC25)
- Selectable CMOS or DDR LVDS output in same pinout (vs ADS61B29IRGZ25)
설계 노트
Layout the analog input traces as a true 50 ohm differential microstrip pair from the input balun or driver to the INP/INN pins, keeping length-matched to within 0.5 mm to avoid sampling-clock skew between channels. Place input common-mode bypass capacitors (0.1 uF and 10 uF) within 2 mm of the VCM pins. The exposed thermal pad must be soldered to a continuous analog-ground copper pour with stitched vias to inner ground plane for low thermal resistance.
Decouple each AVDD pin with a 0.1 uF X7R ceramic plus a 1 uF X5R bulk capacitor within 5 mm of the pin, and provide 10 uF tantalum or polymer bulk capacitors per supply rail. Use a separate analog-supply LDO (e.g., TPS7A4701) for AVDD and a digital LDO for DRVDD/DVDD with ferrite-bead isolation between them. Star-ground topology from the exposed pad to the analog plane minimizes digital switching noise coupling into the analog inputs.
Drive the CLK+/CLK- differential clock input from a low-jitter LVPECL or LVDS source (e.g., LMK04803) terminated with 100 ohm differential near the device. ADC aperture jitter directly degrades SNR at high IF input frequencies, so clock jitter should be below 300 fs RMS for the ADC to achieve datasheet SNR at 70 MHz IF. The DDR LVDS data lines should be length-matched within 0.5 mm and routed on inner signal layers over a continuous ground plane.
Do not leave the OUTMODE and FMT pins to floating-point voltages - they must be tied to DRVDD or DVSS via 10 kohm resistors to set CMOS or DDR LVDS mode. Failing to bypass the RBYP pin causes internal-reference drift and degraded SFDR. Do not exceed 125 MSPS at industrial temperatures without characterizing thermal performance; the exposed pad must be soldered for adequate heat removal at high-duty-cycle sampling.
규정 준수 정보
RoHS and lead-free compliant per TI product page; AEC-Q100 qualification not applicable (industrial-grade ADC, not automotive-qualified).
