EP20K400FI672-2V - APEX 20K 400K FPGA, 502 I/O, 672-FBGA | Intel
부품 번호: EP20K400FI672-2V ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $260 | $2,600.00 |
| 100 | $235 | $23,500.00 |
| 500 | $210 | $105,000.00 |
| 1,000 | $195 | $195,000.00 |
EP20K400FI672-2V 개요
What is a FPGA? A Field-Programmable Gate Array is a type of programmable logic device (PLD) that allows designers to configure logic blocks and interconnect routing after manufacturing. FPGAs sit within the broader taxonomy of programmable logic (PLD -> CPLD -> FPGA) and serve as semiconductor building blocks for digital systems requiring parallelism, high I/O counts, and hardware-level reconfiguration. APEX 20K was historically the industry's first PLD family marketed as a System-on-a-Programmable-Chip (SOPC) platform, integrating dedicated memory blocks, a wide internal datapath, and high-speed I/O on a single die.
Key features include 212,992 embedded system bits for distributed RAM/ROM, 16,640 logic cells, a 2.5 ns propagation delay class, and up to 502 user I/O pins. The 672-pin FBGA package provides a compact high-density interconnect suitable for multi-layer PCB designs. The device supports in-system configuration via serial or parallel PROM interfaces, JTAG (IEEE 1149.1) boundary-scan, and active serial configuration modes. Because this part belongs to a mature, multi-decade product family, designers should expect stable toolchain support through the Altera Quartus II design software.
Typical applications include telecommunications line-card glue logic, industrial control backplanes, ASIC prototyping, high-density bus interfacing, and SOPC integration blocks. Its combination of embedded memory and high I/O count makes it particularly well-suited to systems that previously required multiple CPLDs and discrete glue logic. The APEX 20K 400K device also pairs naturally with high-speed SRAM and SDRAM controllers, providing an integrated memory-plus-logic subsystem on a single part.
When designing with the EP20K400FI672-2V, ensure the PCB supports the BGA fan-out routing rules and that the 2.5 V core supply is decoupled with low-ESR ceramic capacitors placed within 5 mm of each power pin. The device's I/O banks support multiple voltage standards (LVTTL, LVCMOS, PCI, SSTL), but each bank must share a single VCCIO reference. JTAG boundary-scan compliance (IEEE 1149.1) is preserved throughout the lifetime of the family, simplifying board-level test.
This page synthesizes distributor pricing, drop-in same-package variants, and practical design notes for the EP20K400FI672-2V that the manufacturer datasheet alone does not provide.
드롭인 대체품: EP20K400FI672-2V — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP20K400FI672-2V (동일 폼 팩터 및 풋프린트) — 차이점: Operating Temperature, Package, Process Technology, Family, RoHS Status.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP20K400FI672-2N
✅ 드롭인✓ 재고 있음
$188.75 / 개
데이터시트 보기 →EP20K400FI672-2
✅ 드롭인✓ 재고 있음
$92.4 / 개
데이터시트 보기 →EP20K400EFI672-2N
✅ 드롭인✓ 재고 있음
$105 / 개
데이터시트 보기 →EP20K400EFI672-2X
✅ 드롭인✓ 재고 있음
$168 / 개
데이터시트 보기 →EP20K400FG672-2
✅ 드롭인✓ 재고 있음
$92 / 개
데이터시트 보기 →EP20K400FI672-2V 최대 정격 & 전기적 특성
| Family | APEX 20K |
| Device | EP20K400 |
| Logic Elements / Cells | 16640 |
| Total System Gates | 400000 |
| Embedded Memory Bits | 212992 |
| Number of I/O | 502 |
| 패키지 | 672-BBGA, FCBGA |
| Pin / Ball Count | 672 |
| 공급 전압 | 2.5 V |
| Process Technology | 0.22 µm CMOS |
| Propagation Delay | 2.5 ns |
| Internal Operating Frequency | 200 MHz |
| 동작 온도 | 0 °C to +85 °C |
| Logic Family | CMOS |
| 실장 유형 | Surface Mount (BGA) |
| Configuration Mode | Serial / Parallel / JTAG |
EP20K400FI672-2V 핀 구성
| 핀 1 | I/O Bank A0 — User I/O - bank A |
| 핀 168 | I/O Bank B0 — User I/O - bank B |
| 핀 335 | I/O Bank C0 — User I/O - bank C |
| 핀 502 | I/O Bank D0 — User I/O - bank D |
| 핀 503 | TDI — JTAG Test Data In (IEEE 1149.1) |
| 핀 504 | TDO — JTAG Test Data Out (IEEE 1149.1) |
| 핀 505 | TMS — JTAG Test Mode Select (IEEE 1149.1) |
| 핀 506 | TCK — JTAG Test Clock (IEEE 1149.1) |
| 핀 507 | nCONFIG — Configuration control (active-low) |
| 핀 508 | nSTATUS — Configuration status (active-low) |
| 핀 509 | CONF_DONE — Configuration done (open-drain) |
| 핀 510 | MSEL0 — Configuration mode select 0 |
| 핀 511 | MSEL1 — Configuration mode select 1 |
| 핀 512 | MSEL2 — Configuration mode select 2 |
| 핀 513 | DCLK — Configuration clock input |
| 핀 514 | DATA0 — Configuration data input |
| 핀 515 | VCCINT — Core 2.5 V supply |
| 핀 516 | VCCIO_A — I/O bank A reference voltage |
| 핀 517 | VCCIO_B — I/O bank B reference voltage |
| 핀 518 | VCCIO_C — I/O bank C reference voltage |
| 핀 519 | VCCIO_D — I/O bank D reference voltage |
| 핀 520 | VCC_PLL — PLL analog supply |
| 핀 521 | GND — Ground (one of many GND balls) |
| 핀 672 | GND — Ground (one of many GND balls) |
일반적인 애플리케이션
EP20K400FI672-2V 적합 용도: 6 애플리케이션s: Telecommunications Line-Card Glue Logic, ASIC Prototyping Platform, Industrial Control Backplane Interface, High-Density Parallel Bus Bridge, System-on-a-Programmable-Chip (SOPC) Integration, Legacy Test & Measurement Instrument Backplane.
Telecommunications Line-Card Glue Logic
The EP20K400FI672-2V is well-matched to telecom line cards because its 502 user I/O and 212,992 embedded memory bits let it absorb the bus-bridging, protocol-conversion, and FIFO buffering tasks that previously required multiple CPLDs. Its 200 MHz internal operation and 2.5 ns propagation delay class support TDM bus glue at common backplane rates. The 672-FBGA footprint is dense enough to sit directly under the I/O connector array on the line card, simplifying board routing. Compared to a discrete CPLD bank, a single APEX 20K device reduces BOM count and lets designers reprogram the glue logic across hardware revisions.
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ASIC Prototyping Platform
The EP20K400FI672-2V's 400,000-system-gate capacity makes it a practical host for ASIC prototyping before mask production. The 16,640 logic cells map comfortably to mid-complexity ASIC netlists, and the 212,992 embedded memory bits can emulate SRAM/ROM blocks found in the target ASIC. Quartus II synthesis flows accept Verilog and VHDL and produce bitstreams that run on the 672-FBGA part in-system. Designers benefit from in-system JTAG reconfiguration between test vectors, replacing weeks of fab time with minutes of FPGA compile.
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Industrial Control Backplane Interface
Industrial backplanes with mixed LVTTL, LVCMOS, PCI, and SSTL signal levels fit naturally into the EP20K400FI672-2V's I/O bank architecture, where each bank shares a single VCCIO reference. The 502 I/O allow a single FPGA to bridge a parallel backplane bus, a serial management channel, and a discrete I/O ring simultaneously. Its 0-85 °C commercial temperature range is adequate for controlled cabinet environments, while the industrial-grade EP20K400EFI672-2N sibling extends coverage to factory-floor deployments. Compared to a multi-CPLD solution, the APEX 20K consolidates logic and shortens signal-trace lengths.
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High-Density Parallel Bus Bridge
Bridging wide parallel buses (32-bit, 64-bit, and wider) into a processor or memory subsystem is a classic APEX 20K use case. The EP20K400FI672-2V provides 502 I/O, of which 400+ can be dedicated to a multi-byte parallel bus plus side-band control, while the remaining I/O implement the bridge protocol in hardware. The 212,992 embedded memory bits are usable as write/posting buffers to absorb bursts without external FIFOs. Quartus II's MegaWizard Plug-In Manager generates parameterized FIFO blocks that compile directly into the device's ESB resources.
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System-on-a-Programmable-Chip (SOPC) Integration
APEX 20K was the first PLD family marketed as an SOPC platform, and the EP20K400FI672-2V continues that role by integrating processor-cores (NIOS-like soft cores in Quartus), memory blocks, and peripheral logic on one die. Its 400K-gate capacity and 212,992 embedded bits can host a soft 32-bit processor plus on-chip RAM, leaving the 502 I/O free for external peripheral integration. The JTAG boundary-scan interface simplifies multi-core debug across the SOPC subsystem. Designers using the Cyclone series in new designs can also use the APEX 20K as a low-cost reference benchmark.
추천
Legacy Test & Measurement Instrument Backplane
Test & measurement mainframes with VXI, PXI, or proprietary parallel backplanes benefit from the EP20K400FI672-2V's high I/O density and reconfigurable logic. Each instrument slot can host a single APEX 20K part that implements the slot's stimulus/response logic and front-panel data path. The 672-FBGA footprint concentrates logic into a single small area, leaving room for analog front-end components. Designers can re-spin test routines by simply recompiling the Quartus bitstream, avoiding board respins. Industrial-temp variants support laboratory and field-deployed instrument families.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP20K400FI672-2V — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP20K400FI672-2N | EP20K400FI672-2 | EP20K400EFI672-2N | EP20K400EFI672-2X | EP20K400FG672-2 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-BBGA, FCBGA | 672-BBGA, FCBGA - same | 672-BBGA, FCBGA - same | 672-BBGA, FCBGA - same | 672-BBGA, FCBGA - same | 672-BBGA, FCBGA - same |
| Logic Cells | 16640 | 16640 | 16640 | 16640 | 16640 | 16640 |
| System Gates | 400000 | 400000 | 400000 | 400000 | 400000 | 400000 |
| User I/O | 502 | 502 | 502 | 502 | 502 | 502 |
| Embedded Memory Bits | 212992 | 212992 | 212992 | 212992 | 212992 | 212992 |
| Speed Grade | -2V | -2N (slower) | -2 | -2N (slower) | -2X (faster) | -2 |
| Operating Temperature | 0 to +85 °C (commercial) | 0 to +85 °C (commercial) | 0 to +85 °C (commercial) | -40 to +100 °C (industrial) | -40 to +100 °C (industrial) | 0 to +85 °C (commercial) |
주요 차별점
- Largest logic capacity in the 672-BGA APEX 20K family (vs EP20K300EFC672-2)
- Maximum user I/O count among commercial APEX 20K parts (vs EP20K400BC652-3)
- Industrial-temp drop-in alternative available (vs EP20K400EFI672-2N)
- Faster speed grade than the -2N sibling (vs EP20K400FI672-2N)
설계 노트
The 672-BGA package requires multi-layer PCB with microvia or via-in-pad technology for inner-row escape routing. Use a 4/4 mil (0.1/0.1 mm) etch/spacing rule with controlled-impedance layers to support the JTAG TAP and high-speed I/O standards (LVTTL, LVCMOS, PCI, SSTL). Place 2.5 V core decoupling capacitors (10 µF bulk + 0.1 µF ceramic) within 5 mm of each VCCINT pin cluster. VCCIO per-bank reference capacitors should also be local to their respective balls to limit switching-induced supply droop.
Estimated: the EP20K400FI672-2V in the 672-FBGA has a typical θJA of approximately 12-15 °C/W with proper thermal via array under the package center. For continuous operation near full 502-I/O switching, design with at least 9 thermal vias (0.3 mm drill, 1.0 mm pitch) under the die flag, tied to an internal copper plane. Add airflow or a heatsink for designs that run above 25 °C ambient. The industrial-temp sibling EP20K400EFI672-2N provides the same thermal envelope but with an extended -40 °C to +100 °C rating.
Do not confuse the EP20K400FI672 family (672-BGA) with the EP20K400BC652 family (652-BGA) when migrating PCBs - they share the same silicon family but the pinouts and ball maps differ. Also, the speed-grade letter must match across the design: the -2V (faster) and -2N (slower) parts both fit the same 672-BGA footprint but their Quartus II timing models differ. Always re-run Quartus timing analysis after swapping the speed grade. For JTAG operation, ensure TMS and TCK have 10 kΩ pull-ups to VCCIO; missing pull-ups can cause configuration failures.
Group I/O banks by signaling standard to simplify PCB routing: dedicate one bank to LVTTL/LVCMOS parallel data, a second bank to PCI or SSTL memory interface, and a third to slower control I/O. This minimizes reference-voltage (VCCIO) islands and keeps impedance-continuous traces within each bank. Keep JTAG chain signals (TDI/TDO/TMS/TCK) short and away from switching I/O to avoid noise coupling into the TAP state machine. Series 33 Ω resistors on JTAG lines improve signal integrity in long chains.
규정 준수 정보
RoHS / REACH / lead-free status not explicitly stated in the verified distributor data; consult Intel product page or request compliance certificate from supplier. AEC-Q100 not applicable (commercial/industrial FPGA, not automotive qualified). The part is in NRND (Not Recommended for New Designs) lifecycle status as of 2026-09-08.