EP910JC-30 - 30ns 24-Macrocell Classic EPLD | Intel / Altera
부품 번호: EP910JC-30 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $9.75 | $9,750.00 |
EP910JC-30 개요
An EPLD (Erasable Programmable Logic Device) is a one-time-factory-or-window-erasable member of the programmable logic hierarchy that sits below modern CPLDs and FPGAs in capacity. The category chain is: programmable logic device (PLD) -> EPLD -> MAX-style architecture -> CMOS EPROM-based logic block. EPLDs historically served as glue-logic replacements for multiple 74-series TTL/CMOS packages in bus-interface, address-decoding and state-machine designs.
Key headline parameters: 30 ns maximum propagation delay (tpd), 33.3 MHz maximum internal clock frequency (Fmax), 24 macrocells, 36 inputs, 240 product terms, and 10 dedicated output macrocells. The device operates from a single 5V supply and is built on a non-volatile UV-erasable CMOS process, so logic configuration is retained without a configuration memory download at power-up.
Architecturally, the EP910 combines a programmable AND array feeding a fixed OR array with output macrocells that can be configured as registered, combinatorial, or bidirectional I/O. The 24 macrocells are organized to deliver up to 10 dedicated outputs plus 24 I/O pins, and the 240 product terms support sum-of-product logic minimization typical of state-machine and decoder implementations.
Typical applications include legacy glue-logic replacement for 74LS/74HC discrete packages, microprogram sequencers, bus address decoders, peripheral chip-select generators, and CMOS-to-TTL level translation interfaces. Because the part is UV-erasable, it is favored for prototyping and field-reprogrammable industrial controllers.
When designing with this part, plan for a 200 mA typical Icc budget, provide a 0.1 uF decoupling capacitor on every VCC pin pair, and respect the 30 ns propagation delay when computing worst-case setup margins. Logic fitting must observe the 240 product-term limit per macrocell to avoid synthesis overflow.
This page combines distributor pricing, drop-in alternatives, and design notes not aggregated on the manufacturer datasheet.
드롭인 대체품: EP910JC-30 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP910JC-30 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Mounting Type, Operating Temperature, Propagation Delay (tPD), Supply Voltage (VCC).
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP910LC-30
✅ 드롭인✓ 재고 있음
$22.5 / 개
데이터시트 보기 →EP910LC-35
✅ 드롭인✓ 재고 있음
$18.75 / 개
데이터시트 보기 →EP910LC-40
✅ 드롭인✓ 재고 있음
$52 / 개
데이터시트 보기 →EP910LI-35
✅ 드롭인✓ 재고 있음
$25.8 / 개
데이터시트 보기 →EP910ILC-15
✅ 드롭인✓ 재고 있음
$16.1 / 개
데이터시트 보기 →EP900ILC-50
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP910JC-30 최대 정격 & 전기적 특성
| Family | Classic EPLD (MAX-style) |
| Propagation Delay (tpd) | 30 ns |
| Maximum Internal Frequency (Fmax) | 33.3 MHz |
| Macrocells | 24 |
| Inputs | 36 |
| Product Terms | 240 |
| Outputs | 10 dedicated |
| Supply Voltage (Vcc) | 5 V |
| Technology | CMOS EPROM, UV-erasable |
| 패키지 | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| 실장 유형 | Surface Mount (socket-mountable) |
| Logic Blocks | 24 macrocells (AND/OR array architecture) |
EP910JC-30 핀 구성
| 핀 1 | I/O — Input/Output pin |
| 핀 2 | I/O — Input/Output pin |
| 핀 3 | I/O — Input/Output pin |
| 핀 4 | I/O — Input/Output pin |
| 핀 5 | I/O — Input/Output pin |
| 핀 6 | I/O — Input/Output pin |
| 핀 7 | VCC — +5V supply |
| 핀 8 | I/O — Input/Output pin |
| 핀 9 | I/O — Input/Output pin |
| 핀 10 | I/O — Input/Output pin |
| 핀 11 | I/O — Input/Output pin |
| 핀 12 | GND — Ground |
| 핀 13 | I/O — Input/Output pin |
| 핀 14 | I/O — Input/Output pin |
| 핀 15 | I/O — Input/Output pin |
| 핀 16 | I/O — Input/Output pin |
| 핀 17 | I/O — Input/Output pin |
| 핀 18 | I/O — Input/Output pin |
| 핀 19 | I/O — Input/Output pin |
| 핀 20 | VCC — +5V supply |
| 핀 21 | I/O — Input/Output pin |
| 핀 22 | I/O — Input/Output pin |
| 핀 23 | I/O — Input/Output pin |
| 핀 24 | GND — Ground |
| 핀 25 | I/O — Input/Output pin |
| 핀 26 | I/O — Input/Output pin |
| 핀 27 | I/O — Input/Output pin |
| 핀 28 | I/O — Input/Output pin |
| 핀 29 | I/O — Input/Output pin |
| 핀 30 | I/O — Input/Output pin |
| 핀 31 | GND — Ground |
| 핀 32 | I/O — Input/Output pin |
| 핀 33 | I/O — Input/Output pin |
| 핀 34 | I/O — Input/Output pin |
| 핀 35 | I/O — Input/Output pin |
| 핀 36 | VCC — +5V supply |
| 핀 37 | I/O — Input/Output pin |
| 핀 38 | I/O — Input/Output pin |
| 핀 39 | I/O — Input/Output pin |
| 핀 40 | I/O — Input/Output pin |
| 핀 41 | I/O — Input/Output pin |
| 핀 42 | I/O — Input/Output pin |
| 핀 43 | GND — Ground |
| 핀 44 | I/O — Input/Output pin |
일반적인 애플리케이션
EP910JC-30 적합 용도: 6 애플리케이션s: Legacy Glue Logic Replacement, Bus Address Decoding, Microprogram Sequencer / State Machine, Peripheral Chip-Select Generator, Industrial Field-Programmable Controller, CMOS-to-TTL Level Translation Interface.
Legacy Glue Logic Replacement
The EP910JC-30's 24 macrocells, 240 product terms, and 36 inputs let designers consolidate several 74LS/74HC discrete packages into one device for bus-interface glue logic. With 30 ns propagation delay the part still meets 8 MHz 8086/68000-era timing margins, and the UV-erasable ceramic JLCC-44 supports rapid prototype iteration. Compared to a discrete TTL solution the EP910 reduces board area and power while keeping timing predictable. Drop-in compatibility with the EP910LC-30 (plastic JLCC) lets volume builds move off ceramic once prototypes are validated.
추천
Bus Address Decoding
The EP910JC-30 excels at address decoding for legacy 8/16-bit microcomputer systems, generating chip-select signals for memory and peripheral banks. Each macrocell can decode a full address range with up to 16 product terms, and 24 macrocells comfortably cover 8-12 chip-select outputs plus wait-state and interrupt logic. The 30 ns delay fits within typical memory-access windows for 8 MHz Z80/6502/8088 systems, and the non-volatile UV-EPROM configuration eliminates boot-time PLD programming. Compatible sockets accept EP910LC variants for cost-reduced production builds.
추천
Microprogram Sequencer / State Machine
Implementing complex multi-state controllers is straightforward in the EP910JC-30 because each macrocell provides a registered D flip-flop with feedback, and 240 product terms support deeply encoded next-state logic. A 30 ns propagation delay corresponds to roughly 33 MHz state-machine throughput, adequate for legacy industrial controllers and instrumentation sequencers. Registered outputs and buried macrocells enable Mealy/Moore designs without external latches. The UV-erasable ceramic package suits design revisions during prototyping cycles.
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Peripheral Chip-Select Generator
Generate 8-12 chip-select outputs for memory banks, peripheral controllers, and I/O devices using the 10 dedicated outputs of the EP910JC-30 plus I/O pins configured as combinatorial outputs. The 24-macrocell capacity supports decoding of full 24-bit address ranges with overlapping bank windows, and the 30 ns delay ensures chip-select signals are valid before memory access cycles begin. Compared to discrete 74LS138/139 decoder trees the EP910 reduces IC count, board space, and propagation delay skew across decoded outputs.
추천
Industrial Field-Programmable Controller
The EP910JC-30's UV-erasable windowed ceramic package supports in-the-field reprogramming by erasing under a UV lamp and re-loading via an Altera programming adapter, which is valuable for industrial controllers deployed at remote sites. 24 macrocells cover typical PLC-style logic for sensor-debouncing, actuator control, and safety interlocks, while the 5V CMOS supply matches existing industrial backplanes. With operating life rated for decades, the EP910JC-30 remains a long-lifecycle choice for legacy factory automation retrofits.
추천
CMOS-to-TTL Level Translation Interface
Use the EP910JC-30 as a programmable level-translation buffer between 5V CMOS logic and 3.3V TTL peripherals, with configurable output drive strengths and registered or combinatorial paths. 36 inputs can be partitioned for multiple translation channels, and the 30 ns propagation delay adds minimal latency to bus transactions. The non-volatile EPROM-based configuration means translation logic is available at power-up with no FPGA-style boot time, ideal for legacy peripheral interfaces in mixed-voltage designs. The JLCC-44 ceramic package provides mechanical robustness for industrial environments.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP910JC-30 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP910LC-30 | EP910LC-35 | EP910LC-40 | EP910LI-35 | EP910ILC-15 | EP900ILC-50 |
|---|---|---|---|---|---|---|---|
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Package | JLCC-44 (windowed ceramic) | JLCC-44 (windowed plastic) - same | JLCC-44 (windowed plastic) - same | JLCC-44 (windowed plastic) - same | JLCC-44 (industrial temp) - same | JLCC-44 (industrial ceramic) - same | JLCC-44 (industrial ceramic) - same |
| Propagation Delay (tpd) | 30 ns | 30 ns | 35 ns | 40 ns | 35 ns | 15 ns | 50 ns |
| Max Internal Frequency | 33.3 MHz | 33.3 MHz | 28.6 MHz | 25 MHz | 28.6 MHz | 66.7 MHz | 20 MHz |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 16 (EP900 family) |
| Product Terms | 240 | 240 | 240 | 240 | 240 | 240 | 192 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
주요 차별점
- Lowest-cost same-footprint 30ns drop-in (vs EP910ILC-15)
- Windowed ceramic package for UV erasure (vs EP910LC-30)
- Same pinout as EP900 family for backward compatibility (vs EP900ILC-50)
설계 노트
Estimated: The windowed ceramic JLCC-44 package of the EP910JC-30 has a typical junction-to-ambient thermal resistance (theta_JA) of approximately 45-55 C/W. At 200 mA Icc and 5V supply, internal dissipation is roughly 1.0 W, yielding a junction temperature rise of 45-55 C above ambient. For industrial deployments above 70C ambient, consider the EP910LI-35 industrial-temperature variant which is specified for -40C to +85C operation. Verify thermal margins with the manufacturer datasheet thermal characteristics before finalizing industrial designs.
Mount the EP910JC-30 in a 44-pin JLCC socket (e.g. 3M Textool or equivalent) to enable UV erasure and reprogramming during development. Place 0.1 uF ceramic decoupling capacitors within 5 mm of every VCC pin and a single 10 uF tantalum bulk capacitor near the device. Keep high-speed output traces short and routed over a continuous ground plane to minimize inductive ringing on the 30 ns edges. Reserve a clear keep-out area above the ceramic window for UV erasure lamp access during prototyping.
Do not assume the EP910JC-30 logic fits unlimited complexity; each macrocell has a 16-product-term ceiling and total resource is 240 product terms. Synthesis overflow will produce 'unfittable' errors that the Altera MAX+PLUS II or AHDL toolchain flags. Also note that UV erasure requires a 254 nm UV lamp at 20-30 minutes exposure; partial erasure leaves residual programming that causes erratic logic. For new designs, consider migrating to a MAX V CPLD (5M80ZE64) which offers JTAG programming and modern I/O standards at lower cost than obsolete EP910 stock.
규정 준수 정보
Compliance data not provided in the verified web sources. The EP910 family predates current RoHS compliance documentation; lead-free and halogen-free status are unknown for this part.
