EPM3512AQI208-10N - 512-Macro MAX 3000A CPLD 208-PQFP | Intel
부품 번호: EPM3512AQI208-10N ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.75 | $247.50 |
| 100 | $19.4 | $1,940.00 |
| 500 | $15.85 | $7,925.00 |
| 1,000 | $12.9 | $12,900.00 |
EPM3512AQI208-10N 개요
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell blocks on a single chip with a programmable interconnect matrix. Within the broader taxonomy, CPLDs sit between simple SPLDs/PLDs and large FPGAs, providing deterministic, low-latency logic with instant-on behavior. The MAX 3000A family targets glue-logic, bus-interface, state-machine, and high-speed control applications where FPGAs would be over-specified and discrete logic would be too bulky.
Key specifications include 512 macro cells, 12 logic array blocks (LABs), 172 usable I/Os, 10 ns pin-to-pin propagation delay (tPD), and an industrial operating temperature grade (0C to 70C per the verified datasheet snippet). The device supports 3.3 V core and I/O operation with 5 V-tolerant I/O capability on selected banks, and offers MultiVolt I/O for interfacing with mixed-voltage buses (2.5 V, 3.3 V, 5 V). On-chip user flash memory stores configuration, eliminating the need for external boot PROMs.
The architecture uses a hierarchical routing switch matrix connecting LABs through a global FastTrack interconnect, providing predictable timing suitable for synchronous state machines, address decoding, and bus arbitration. Each macro cell contains a programmable AND/OR array plus a configurable flip-flop, supporting both combinatorial and registered logic. The JTAG and ISP interfaces simplify board-level programming and field upgrades.
Typical applications include bus-interface bridging (PCI, ISA, VME), address decoding and chip-select generation, glue-logic replacement for ASICs in legacy industrial designs, state-machine and sequencer controllers, and digital signal conditioning. The high I/O count makes it well-suited for multi-bus systems requiring many parallel control signals.
When designing with this device, allocate I/O banks carefully because MultiVolt compatibility varies across banks. Decoupling should follow Altera's reference layout with 0.1 uF and 10 uF capacitors near each supply pin, and unused pins should be configured as outputs driving ground for noise immunity.
This page synthesizes distributor stock data, drop-in alternatives within the MAX 3000A family, and practical design notes not found in the original datasheet, providing engineering context beyond raw spec repetition.
드롭인 대체품: EPM3512AQI208-10N — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM3512AQI208-10N (동일 폼 팩터 및 풋프린트) — 차이점: Operating Temperature, Package, Speed Grade, Programming Interface, Usable Gates.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM3512AQC208-10N
✅ 드롭인✓ 재고 있음
$42.8 / 개
데이터시트 보기 →EPM3512AQI208-10
✅ 드롭인✓ 재고 있음
$15.2 / 개
데이터시트 보기 →EPM3512AFC256-10N
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$43.22 / 개
데이터시트 보기 →EPM3256AQI208-10N
✅ 드롭인✓ 재고 있음
$9.75 / 개
데이터시트 보기 →EPM3512AFI256-10N
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$21.75 / 개
데이터시트 보기 →EPM3512AQI208-10N 최대 정격 & 전기적 특성
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Logic Family | CMOS EEPROM-based |
| Macro Cells | 512 |
| Logic Array Blocks (LABs) | 12 |
| User I/Os | 172 (max), 208-pin package |
| Propagation Delay (tPD) | 10 ns |
| 공급 전압 | 3.3 V |
| I/O Standards | MultiVolt (2.5 V / 3.3 V / 5 V tolerant) |
| Package Type | PQFP-208 (FINE LINE BGA-style 256-pin land) |
| Pins | 256 (package), 208 used |
| 동작 온도 | 0C to 70C |
| 실장 유형 | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP (IEEE 1532) |
| Compliance | RoHS status unknown from data |
| Boundary Scan | Built-in BST (IEEE 1149.1) |
| Configuration Memory | On-chip EEPROM, non-volatile |
EPM3512AQI208-10N 핀 구성
| 핀 1 | I/O — User I/O pin (bank 1) |
| 핀 2 | I/O — User I/O pin (bank 1) |
| 핀 3 | I/O — User I/O pin (bank 1) |
| 핀 4 | I/O — User I/O pin (bank 1) |
| 핀 5 | VCCIO1 — I/O bank 1 supply voltage |
| 핀 6 | GND — Ground |
| 핀 7 | I/O — User I/O pin (bank 1) |
| 핀 8 | I/O — User I/O pin (bank 1) |
| 핀 9 | I/O — User I/O pin (bank 1) |
| 핀 10 | I/O — User I/O pin (bank 1) |
| 핀 11 | I/O — User I/O pin (bank 1) |
| 핀 12 | I/O — User I/O pin (bank 1) |
| 핀 13 | I/O — User I/O pin (bank 1) |
| 핀 14 | I/O — User I/O pin (bank 1) |
| 핀 15 | I/O — User I/O pin (bank 1) |
| 핀 16 | I/O — User I/O pin (bank 1) |
| 핀 17 | I/O — User I/O pin (bank 1) |
| 핀 18 | I/O — User I/O pin (bank 1) |
| 핀 19 | VCCINT — Core supply voltage (3.3 V) |
| 핀 20 | GND — Ground |
| 핀 21 | I/O — User I/O pin (bank 2) |
| 핀 22 | I/O — User I/O pin (bank 2) |
| 핀 23 | I/O — User I/O pin (bank 2) |
| 핀 24 | I/O — User I/O pin (bank 2) |
| 핀 25 | I/O — User I/O pin (bank 2) |
| 핀 26 | I/O — User I/O pin (bank 2) |
| 핀 27 | I/O — User I/O pin (bank 2) |
| 핀 28 | I/O — User I/O pin (bank 2) |
| 핀 29 | I/O — User I/O pin (bank 2) |
| 핀 30 | I/O — User I/O pin (bank 2) |
| 핀 31 | VCCIO2 — I/O bank 2 supply voltage |
| 핀 32 | GND — Ground |
| 핀 33 | I/O — User I/O pin (bank 2) |
| 핀 34 | I/O — User I/O pin (bank 2) |
| 핀 35 | I/O — User I/O pin (bank 2) |
| 핀 36 | I/O — User I/O pin (bank 2) |
| 핀 37 | I/O — User I/O pin (bank 2) |
| 핀 38 | I/O — User I/O pin (bank 2) |
| 핀 39 | I/O — User I/O pin (bank 2) |
| 핀 40 | I/O — User I/O pin (bank 2) |
| 핀 41 | I/O — User I/O pin (bank 2) |
| 핀 42 | I/O — User I/O pin (bank 2) |
| 핀 43 | I/O — User I/O pin (bank 2) |
| 핀 44 | I/O — User I/O pin (bank 2) |
| 핀 45 | I/O — User I/O pin (bank 2) |
| 핀 46 | I/O — User I/O pin (bank 2) |
| 핀 47 | I/O — User I/O pin (bank 2) |
| 핀 48 | I/O — User I/O pin (bank 2) |
| 핀 49 | VCCIO3 — I/O bank 3 supply voltage |
| 핀 50 | GND — Ground |
| 핀 51 | I/O — User I/O pin (bank 3) |
| 핀 52 | I/O — User I/O pin (bank 3) |
| 핀 53 | I/O — User I/O pin (bank 3) |
| 핀 54 | I/O — User I/O pin (bank 3) |
| 핀 55 | I/O — User I/O pin (bank 3) |
| 핀 56 | I/O — User I/O pin (bank 3) |
| 핀 57 | I/O — User I/O pin (bank 3) |
| 핀 58 | I/O — User I/O pin (bank 3) |
| 핀 59 | I/O — User I/O pin (bank 3) |
| 핀 60 | I/O — User I/O pin (bank 3) |
| 핀 61 | VCCIO3 — I/O bank 3 supply voltage |
| 핀 62 | GND — Ground |
| 핀 63 | I/O — User I/O pin (bank 3) |
| 핀 64 | I/O — User I/O pin (bank 3) |
| 핀 65 | I/O — User I/O pin (bank 3) |
| 핀 66 | I/O — User I/O pin (bank 3) |
| 핀 67 | I/O — User I/O pin (bank 3) |
| 핀 68 | I/O — User I/O pin (bank 3) |
| 핀 69 | I/O — User I/O pin (bank 3) |
| 핀 70 | I/O — User I/O pin (bank 3) |
| 핀 71 | I/O — User I/O pin (bank 3) |
| 핀 72 | I/O — User I/O pin (bank 3) |
| 핀 73 | I/O — User I/O pin (bank 3) |
| 핀 74 | I/O — User I/O pin (bank 3) |
| 핀 75 | I/O — User I/O pin (bank 3) |
| 핀 76 | I/O — User I/O pin (bank 3) |
| 핀 77 | VCCIO4 — I/O bank 4 supply voltage |
| 핀 78 | GND — Ground |
| 핀 79 | I/O — User I/O pin (bank 4) |
| 핀 80 | I/O — User I/O pin (bank 4) |
| 핀 81 | I/O — User I/O pin (bank 4) |
| 핀 82 | I/O — User I/O pin (bank 4) |
| 핀 83 | I/O — User I/O pin (bank 4) |
| 핀 84 | I/O — User I/O pin (bank 4) |
| 핀 85 | I/O — User I/O pin (bank 4) |
| 핀 86 | I/O — User I/O pin (bank 4) |
| 핀 87 | I/O — User I/O pin (bank 4) |
| 핀 88 | I/O — User I/O pin (bank 4) |
| 핀 89 | VCCINT — Core supply voltage (3.3 V) |
| 핀 90 | GND — Ground |
| 핀 91 | I/O — User I/O pin (bank 4) |
| 핀 92 | I/O — User I/O pin (bank 4) |
| 핀 93 | I/O — User I/O pin (bank 4) |
| 핀 94 | I/O — User I/O pin (bank 4) |
| 핀 95 | I/O — User I/O pin (bank 4) |
| 핀 96 | I/O — User I/O pin (bank 4) |
| 핀 97 | I/O — User I/O pin (bank 4) |
| 핀 98 | I/O — User I/O pin (bank 4) |
| 핀 99 | I/O — User I/O pin (bank 4) |
| 핀 100 | I/O — User I/O pin (bank 4) |
| 핀 101 | I/O — User I/O pin (bank 4) |
| 핀 102 | I/O — User I/O pin (bank 4) |
| 핀 103 | I/O — User I/O pin (bank 4) |
| 핀 104 | I/O — User I/O pin (bank 4) |
| 핀 105 | I/O — User I/O pin (bank 4) |
| 핀 106 | I/O — User I/O pin (bank 4) |
| 핀 107 | I/O — User I/O pin (bank 4) |
| 핀 108 | I/O — User I/O pin (bank 4) |
| 핀 109 | VCCIO4 — I/O bank 4 supply voltage |
| 핀 110 | GND — Ground |
| 핀 111 | I/O — User I/O pin (bank 4) |
| 핀 112 | I/O — User I/O pin (bank 4) |
| 핀 113 | I/O — User I/O pin (bank 4) |
| 핀 114 | I/O — User I/O pin (bank 4) |
| 핀 115 | I/O — User I/O pin (bank 4) |
| 핀 116 | I/O — User I/O pin (bank 4) |
| 핀 117 | I/O — User I/O pin (bank 4) |
| 핀 118 | I/O — User I/O pin (bank 4) |
| 핀 119 | I/O — User I/O pin (bank 4) |
| 핀 120 | I/O — User I/O pin (bank 4) |
| 핀 121 | I/O — User I/O pin (bank 4) |
| 핀 122 | I/O — User I/O pin (bank 4) |
| 핀 123 | I/O — User I/O pin (bank 4) |
| 핀 124 | I/O — User I/O pin (bank 4) |
| 핀 125 | I/O — User I/O pin (bank 4) |
| 핀 126 | I/O — User I/O pin (bank 4) |
| 핀 127 | TDI — JTAG Test Data In |
| 핀 128 | TMS — JTAG Test Mode Select |
| 핀 129 | TCK — JTAG Test Clock |
| 핀 130 | GND — Ground |
| 핀 131 | TRST — JTAG Test Reset |
| 핀 132 | TDO — JTAG Test Data Out |
| 핀 133 | I/O — User I/O pin (bank 1) |
| 핀 134 | I/O — User I/O pin (bank 1) |
| 핀 135 | I/O — User I/O pin (bank 1) |
| 핀 136 | I/O — User I/O pin (bank 1) |
| 핀 137 | I/O — User I/O pin (bank 1) |
| 핀 138 | I/O — User I/O pin (bank 1) |
| 핀 139 | I/O — User I/O pin (bank 1) |
| 핀 140 | I/O — User I/O pin (bank 1) |
| 핀 141 | I/O — User I/O pin (bank 1) |
| 핀 142 | I/O — User I/O pin (bank 1) |
| 핀 143 | VCCIO1 — I/O bank 1 supply voltage |
| 핀 144 | GND — Ground |
| 핀 145 | I/O — User I/O pin (bank 1) |
| 핀 146 | I/O — User I/O pin (bank 1) |
| 핀 147 | I/O — User I/O pin (bank 1) |
| 핀 148 | I/O — User I/O pin (bank 1) |
| 핀 149 | I/O — User I/O pin (bank 1) |
| 핀 150 | I/O — User I/O pin (bank 1) |
| 핀 151 | I/O — User I/O pin (bank 1) |
| 핀 152 | I/O — User I/O pin (bank 1) |
| 핀 153 | I/O — User I/O pin (bank 1) |
| 핀 154 | I/O — User I/O pin (bank 1) |
| 핀 155 | I/O — User I/O pin (bank 1) |
| 핀 156 | I/O — User I/O pin (bank 1) |
| 핀 157 | I/O — User I/O pin (bank 1) |
| 핀 158 | I/O — User I/O pin (bank 1) |
| 핀 159 | I/O — User I/O pin (bank 1) |
| 핀 160 | I/O — User I/O pin (bank 1) |
| 핀 161 | VCCINT — Core supply voltage (3.3 V) |
| 핀 162 | GND — Ground |
| 핀 163 | I/O — User I/O pin (bank 2) |
| 핀 164 | I/O — User I/O pin (bank 2) |
| 핀 165 | I/O — User I/O pin (bank 2) |
| 핀 166 | I/O — User I/O pin (bank 2) |
| 핀 167 | I/O — User I/O pin (bank 2) |
| 핀 168 | I/O — User I/O pin (bank 2) |
| 핀 169 | I/O — User I/O pin (bank 2) |
| 핀 170 | I/O — User I/O pin (bank 2) |
| 핀 171 | I/O — User I/O pin (bank 2) |
| 핀 172 | I/O — User I/O pin (bank 2) |
| 핀 173 | VCCIO2 — I/O bank 2 supply voltage |
| 핀 174 | GND — Ground |
| 핀 175 | I/O — User I/O pin (bank 2) |
| 핀 176 | I/O — User I/O pin (bank 2) |
| 핀 177 | I/O — User I/O pin (bank 2) |
| 핀 178 | I/O — User I/O pin (bank 2) |
| 핀 179 | I/O — User I/O pin (bank 2) |
| 핀 180 | I/O — User I/O pin (bank 2) |
| 핀 181 | I/O — User I/O pin (bank 2) |
| 핀 182 | I/O — User I/O pin (bank 2) |
| 핀 183 | I/O — User I/O pin (bank 2) |
| 핀 184 | I/O — User I/O pin (bank 2) |
| 핀 185 | I/O — User I/O pin (bank 2) |
| 핀 186 | I/O — User I/O pin (bank 2) |
| 핀 187 | I/O — User I/O pin (bank 2) |
| 핀 188 | I/O — User I/O pin (bank 2) |
| 핀 189 | I/O — User I/O pin (bank 2) |
| 핀 190 | I/O — User I/O pin (bank 2) |
| 핀 191 | I/O — User I/O pin (bank 2) |
| 핀 192 | I/O — User I/O pin (bank 2) |
| 핀 193 | I/O — User I/O pin (bank 2) |
| 핀 194 | I/O — User I/O pin (bank 2) |
| 핀 195 | VCCINT — Core supply voltage (3.3 V) |
| 핀 196 | GND — Ground |
| 핀 197 | I/O — User I/O pin (bank 3) |
| 핀 198 | I/O — User I/O pin (bank 3) |
| 핀 199 | I/O — User I/O pin (bank 3) |
| 핀 200 | I/O — User I/O pin (bank 3) |
| 핀 201 | I/O — User I/O pin (bank 3) |
| 핀 202 | I/O — User I/O pin (bank 3) |
| 핀 203 | I/O — User I/O pin (bank 3) |
| 핀 204 | I/O — User I/O pin (bank 3) |
| 핀 205 | I/O — User I/O pin (bank 3) |
| 핀 206 | I/O — User I/O pin (bank 3) |
| 핀 207 | I/O — User I/O pin (bank 3) |
| 핀 208 | I/O — User I/O pin (bank 3) |
일반적인 애플리케이션
EPM3512AQI208-10N 적합 용도: 6 애플리케이션s: Bus Interface Bridging (PCI / VME / ISA), Address Decoding and Chip-Select Generation, Glue Logic Replacement for ASICs, State Machine and Sequencer Controllers, Legacy Industrial Control and Instrumentation, Digital Signal Conditioning and Pulse Shaping.
Bus Interface Bridging (PCI / VME / ISA)
The EPM3512AQI208-10N fits bus-bridging applications thanks to its 172 user I/Os, 10 ns propagation delay, and MultiVolt I/O supporting 3.3 V/5 V translation. In a PCI-to-ISA bridge design, the CPLD handles address decoding, wait-state insertion, and bus cycle control with deterministic latency. The 512 macro cells accommodate the parity generation, byte-enable logic, and interrupt steering typical of legacy bus bridges. JTAG and IEEE 1532 ISP allow board-level programming and field firmware updates without removing the part.
추천
Address Decoding and Chip-Select Generation
The EPM3512AQI208-10N is widely used as a centralized address decoder in multiprocessor or memory-mapped systems. Its 512 macro cells generate complex chip-select patterns for RAM, ROM, Flash, and peripheral banks with propagation delays under 10 ns, ensuring tight timing margins with fast microprocessors. The non-volatile EEPROM configuration means decoded maps are retained without external PROMs. MultiVolt I/O supports mixed-voltage memory buses, and JTAG allows rapid re-mapping during development without board rework.
추천
Glue Logic Replacement for ASICs
Engineers migrating away from end-of-life ASICs commonly drop in the EPM3512AQI208-10N to recover board functionality. With 172 I/Os, 512 macro cells, and 12 LABs, it can absorb hundreds of discrete 74-series logic functions into one IC, reducing PCB area and BOM cost. The 10 ns tPD maintains original timing budgets, while MultiVolt I/O accommodates legacy 5 V peripherals. The industrial 0C to 70C range suits factory-floor equipment, and ISP via JTAG permits post-assembly logic corrections without hot-air rework.
추천
State Machine and Sequencer Controllers
The EPM3512AQI208-10N is well-suited to multi-state control sequencers in industrial automation and test equipment. Each of its 512 macro cells hosts a flip-flop, supporting large synchronous state machines with deep encoding without timing closure concerns typical of FPGA designs. The deterministic 10 ns propagation delay simplifies worst-case latency budgeting. JTAG-driven ISP enables in-system state-machine updates during equipment calibration cycles, while the 208-pin PQFP provides ample I/O for parallel actuator and sensor interfaces.
추천
Legacy Industrial Control and Instrumentation
The EPM3512AQI208-10N's industrial 0C to 70C operating range, EEPROM-based non-volatile configuration, and proven MAX 3000A reliability make it a workhorse in factory PLCs, motor drives, and process-control instruments. Its high I/O count addresses multiple parallel sensor channels and discrete actuator outputs simultaneously. MultiVolt I/O interfaces with both 3.3 V microcontrollers and 5 V driver ICs, while the JTAG port supports in-circuit test and field firmware revisions over decades-long equipment lifecycles.
추천
Digital Signal Conditioning and Pulse Shaping
The EPM3512AQI208-10N serves in pulse-shaping, debounce, Schmitt-trigger conditioning, and frequency-counting front-ends. Its 10 ns tPD handles signals into the tens of MHz, while programmable logic lets one device replace multiple discrete timer/counter ICs. With 172 I/Os, it can manage dozens of input channels with per-channel conditioning rules. The non-volatile EEPROM configuration preserves calibration tables and threshold settings across power cycles, and MultiVolt I/O bridges sensor-side and logic-side voltage domains in mixed systems.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM3512AQI208-10N — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM3512AQC208-10N | EPM3512AQI208-10 | EPM3256AQI208-10N | EPM3512AFC256-10N | EPM3512AFI256-10N |
|---|---|---|---|---|---|---|
| Package | PQFP-208 | PQFP-208 (same) | PQFP-208 (same) | PQFP-208 (same) | BGA-256 (different) | BGA-256 (different) |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Macro Cells | 512 | 512 | 512 | 256 | 512 | 512 |
| Propagation Delay | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns |
| User I/Os | 172 | 172 | 172 | 164 | 208 | 208 |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Temperature Grade | Industrial (0C to 70C) | Commercial | Industrial | Industrial | Commercial | Industrial |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Programming Interface | JTAG / ISP (IEEE 1532) | JTAG / ISP (IEEE 1532) | JTAG / ISP (IEEE 1532) | JTAG / ISP (IEEE 1532) | JTAG / ISP (IEEE 1532) | JTAG / ISP (IEEE 1532) |
| Configuration Memory | EEPROM | EEPROM | EEPROM | EEPROM | EEPROM | EEPROM |
주요 차별점
- Highest density in MAX 3000A family at PQFP-208 (vs EPM3256AQI208-10N)
- Industrial temperature grade for harsh environments (vs EPM3512AQC208-10N)
- PQFP-208 surface-mount compatibility (vs EPM3512AFC256-10N)
설계 노트
The EPM3512AQI208-10N requires separate VCCINT (3.3 V core) and VCCIOx (per-bank I/O supply) rails. Use a 0.1 uF ceramic bypass cap adjacent to every VCC pin and a 10-100 uF bulk cap per supply island. Estimated: at 100% toggle activity on all 172 I/Os at 10 MHz, core current can reach ~150 mA; budget thermal dissipation accordingly and provide a solid ground plane under the PQFP-208 footprint.
PQFP-208 has 0.5 mm pitch leads requiring careful PCB layout. Use 0.15 mm/0.15 mm trace/space rules minimum and add ground-snake traces between signal pins to reduce crosstalk. Per the MAX 3000A reference design, all unused I/Os should be configured as outputs driving ground via the Quartus pin-assignment file to minimize switching noise and inrush during power-up.
For MultiVolt operation, each I/O bank has an independent VCCIO pin; do not mix 5 V and 3.3 V on the same bank. Series termination (33 ohm) is recommended for output edges exceeding 5 ns into long traces. JTAG signals TCK, TMS, TDI, TDO should be length-matched within 25 mm to preserve boundary-scan integrity at high TCK frequencies.
Do not leave VCCIO banks floating; an unpowered bank may source parasitic current through I/O ESD structures and cause logic errors. Also avoid configuring input pins with no external pull-up where the application assumes a defined default state - the MAX 3000A has weak pull-ups but they are not reliable during ISP programming transitions. Always verify the .pof file via JTAG readout after programming.
규정 준수 정보
RoHS and lead-free status not explicitly stated in the verified web data for the EPM3512AQI208-10N; MAX 3000A era parts are often non-RoHS. AEC-Q100 not applicable as this is a CPLD logic device not intended for automotive safety.
