EPM3512AQI208-10N - 512-Macro MAX 3000A CPLD 208-PQFP | Intel
N.º da peça: EPM3512AQI208-10N ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $28.5 | $28,50 |
| 10 | $24.75 | $247,50 |
| 100 | $19.4 | $1.940,00 |
| 500 | $15.85 | $7.925,00 |
| 1.000 | $12.9 | $12.900,00 |
EPM3512AQI208-10N Visão geral
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell blocks on a single chip with a programmable interconnect matrix. Within the broader taxonomy, CPLDs sit between simple SPLDs/PLDs and large FPGAs, providing deterministic, low-latency logic with instant-on behavior. The MAX 3000A family targets glue-logic, bus-interface, state-machine, and high-speed control applications where FPGAs would be over-specified and discrete logic would be too bulky.
Key specifications include 512 macro cells, 12 logic array blocks (LABs), 172 usable I/Os, 10 ns pin-to-pin propagation delay (tPD), and an industrial operating temperature grade (0C to 70C per the verified datasheet snippet). The device supports 3.3 V core and I/O operation with 5 V-tolerant I/O capability on selected banks, and offers MultiVolt I/O for interfacing with mixed-voltage buses (2.5 V, 3.3 V, 5 V). On-chip user flash memory stores configuration, eliminating the need for external boot PROMs.
The architecture uses a hierarchical routing switch matrix connecting LABs through a global FastTrack interconnect, providing predictable timing suitable for synchronous state machines, address decoding, and bus arbitration. Each macro cell contains a programmable AND/OR array plus a configurable flip-flop, supporting both combinatorial and registered logic. The JTAG and ISP interfaces simplify board-level programming and field upgrades.
Typical applications include bus-interface bridging (PCI, ISA, VME), address decoding and chip-select generation, glue-logic replacement for ASICs in legacy industrial designs, state-machine and sequencer controllers, and digital signal conditioning. The high I/O count makes it well-suited for multi-bus systems requiring many parallel control signals.
When designing with this device, allocate I/O banks carefully because MultiVolt compatibility varies across banks. Decoupling should follow Altera's reference layout with 0.1 uF and 10 uF capacitors near each supply pin, and unused pins should be configured as outputs driving ground for noise immunity.
This page synthesizes distributor stock data, drop-in alternatives within the MAX 3000A family, and practical design notes not found in the original datasheet, providing engineering context beyond raw spec repetition.
Alternativas drop-in para EPM3512AQI208-10N — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM3512AQI208-10N (mesmo formato e footprint) — diferindo em Operating Temperature, Package, Speed Grade, Programming Interface, Usable Gates.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM3512AQC208-10N
✅ Drop-In✓ Em estoque
$42.8 / unidade
Ver ficha técnica →EPM3512AQI208-10
✅ Drop-In✓ Em estoque
$15.2 / unidade
Ver ficha técnica →EPM3512AFC256-10N
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$43.22 / unidade
Ver ficha técnica →EPM3256AQI208-10N
✅ Drop-In✓ Em estoque
$9.75 / unidade
Ver ficha técnica →EPM3512AFI256-10N
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$21.75 / unidade
Ver ficha técnica →EPM3512AQI208-10N Classificações máximas e características elétricas
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Logic Family | CMOS EEPROM-based |
| Macro Cells | 512 |
| Logic Array Blocks (LABs) | 12 |
| User I/Os | 172 (max), 208-pin package |
| Propagation Delay (tPD) | 10 ns |
| Tensão de alimentação | 3.3 V |
| I/O Standards | MultiVolt (2.5 V / 3.3 V / 5 V tolerant) |
| Package Type | PQFP-208 (FINE LINE BGA-style 256-pin land) |
| Pins | 256 (package), 208 used |
| Temperatura de operação | 0C to 70C |
| Tipo de montagem | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP (IEEE 1532) |
| Compliance | RoHS status unknown from data |
| Boundary Scan | Built-in BST (IEEE 1149.1) |
| Configuration Memory | On-chip EEPROM, non-volatile |
Configuração de pinos do EPM3512AQI208-10N
| Pino 1 | I/O — User I/O pin (bank 1) |
| Pino 2 | I/O — User I/O pin (bank 1) |
| Pino 3 | I/O — User I/O pin (bank 1) |
| Pino 4 | I/O — User I/O pin (bank 1) |
| Pino 5 | VCCIO1 — I/O bank 1 supply voltage |
| Pino 6 | GND — Ground |
| Pino 7 | I/O — User I/O pin (bank 1) |
| Pino 8 | I/O — User I/O pin (bank 1) |
| Pino 9 | I/O — User I/O pin (bank 1) |
| Pino 10 | I/O — User I/O pin (bank 1) |
| Pino 11 | I/O — User I/O pin (bank 1) |
| Pino 12 | I/O — User I/O pin (bank 1) |
| Pino 13 | I/O — User I/O pin (bank 1) |
| Pino 14 | I/O — User I/O pin (bank 1) |
| Pino 15 | I/O — User I/O pin (bank 1) |
| Pino 16 | I/O — User I/O pin (bank 1) |
| Pino 17 | I/O — User I/O pin (bank 1) |
| Pino 18 | I/O — User I/O pin (bank 1) |
| Pino 19 | VCCINT — Core supply voltage (3.3 V) |
| Pino 20 | GND — Ground |
| Pino 21 | I/O — User I/O pin (bank 2) |
| Pino 22 | I/O — User I/O pin (bank 2) |
| Pino 23 | I/O — User I/O pin (bank 2) |
| Pino 24 | I/O — User I/O pin (bank 2) |
| Pino 25 | I/O — User I/O pin (bank 2) |
| Pino 26 | I/O — User I/O pin (bank 2) |
| Pino 27 | I/O — User I/O pin (bank 2) |
| Pino 28 | I/O — User I/O pin (bank 2) |
| Pino 29 | I/O — User I/O pin (bank 2) |
| Pino 30 | I/O — User I/O pin (bank 2) |
| Pino 31 | VCCIO2 — I/O bank 2 supply voltage |
| Pino 32 | GND — Ground |
| Pino 33 | I/O — User I/O pin (bank 2) |
| Pino 34 | I/O — User I/O pin (bank 2) |
| Pino 35 | I/O — User I/O pin (bank 2) |
| Pino 36 | I/O — User I/O pin (bank 2) |
| Pino 37 | I/O — User I/O pin (bank 2) |
| Pino 38 | I/O — User I/O pin (bank 2) |
| Pino 39 | I/O — User I/O pin (bank 2) |
| Pino 40 | I/O — User I/O pin (bank 2) |
| Pino 41 | I/O — User I/O pin (bank 2) |
| Pino 42 | I/O — User I/O pin (bank 2) |
| Pino 43 | I/O — User I/O pin (bank 2) |
| Pino 44 | I/O — User I/O pin (bank 2) |
| Pino 45 | I/O — User I/O pin (bank 2) |
| Pino 46 | I/O — User I/O pin (bank 2) |
| Pino 47 | I/O — User I/O pin (bank 2) |
| Pino 48 | I/O — User I/O pin (bank 2) |
| Pino 49 | VCCIO3 — I/O bank 3 supply voltage |
| Pino 50 | GND — Ground |
| Pino 51 | I/O — User I/O pin (bank 3) |
| Pino 52 | I/O — User I/O pin (bank 3) |
| Pino 53 | I/O — User I/O pin (bank 3) |
| Pino 54 | I/O — User I/O pin (bank 3) |
| Pino 55 | I/O — User I/O pin (bank 3) |
| Pino 56 | I/O — User I/O pin (bank 3) |
| Pino 57 | I/O — User I/O pin (bank 3) |
| Pino 58 | I/O — User I/O pin (bank 3) |
| Pino 59 | I/O — User I/O pin (bank 3) |
| Pino 60 | I/O — User I/O pin (bank 3) |
| Pino 61 | VCCIO3 — I/O bank 3 supply voltage |
| Pino 62 | GND — Ground |
| Pino 63 | I/O — User I/O pin (bank 3) |
| Pino 64 | I/O — User I/O pin (bank 3) |
| Pino 65 | I/O — User I/O pin (bank 3) |
| Pino 66 | I/O — User I/O pin (bank 3) |
| Pino 67 | I/O — User I/O pin (bank 3) |
| Pino 68 | I/O — User I/O pin (bank 3) |
| Pino 69 | I/O — User I/O pin (bank 3) |
| Pino 70 | I/O — User I/O pin (bank 3) |
| Pino 71 | I/O — User I/O pin (bank 3) |
| Pino 72 | I/O — User I/O pin (bank 3) |
| Pino 73 | I/O — User I/O pin (bank 3) |
| Pino 74 | I/O — User I/O pin (bank 3) |
| Pino 75 | I/O — User I/O pin (bank 3) |
| Pino 76 | I/O — User I/O pin (bank 3) |
| Pino 77 | VCCIO4 — I/O bank 4 supply voltage |
| Pino 78 | GND — Ground |
| Pino 79 | I/O — User I/O pin (bank 4) |
| Pino 80 | I/O — User I/O pin (bank 4) |
| Pino 81 | I/O — User I/O pin (bank 4) |
| Pino 82 | I/O — User I/O pin (bank 4) |
| Pino 83 | I/O — User I/O pin (bank 4) |
| Pino 84 | I/O — User I/O pin (bank 4) |
| Pino 85 | I/O — User I/O pin (bank 4) |
| Pino 86 | I/O — User I/O pin (bank 4) |
| Pino 87 | I/O — User I/O pin (bank 4) |
| Pino 88 | I/O — User I/O pin (bank 4) |
| Pino 89 | VCCINT — Core supply voltage (3.3 V) |
| Pino 90 | GND — Ground |
| Pino 91 | I/O — User I/O pin (bank 4) |
| Pino 92 | I/O — User I/O pin (bank 4) |
| Pino 93 | I/O — User I/O pin (bank 4) |
| Pino 94 | I/O — User I/O pin (bank 4) |
| Pino 95 | I/O — User I/O pin (bank 4) |
| Pino 96 | I/O — User I/O pin (bank 4) |
| Pino 97 | I/O — User I/O pin (bank 4) |
| Pino 98 | I/O — User I/O pin (bank 4) |
| Pino 99 | I/O — User I/O pin (bank 4) |
| Pino 100 | I/O — User I/O pin (bank 4) |
| Pino 101 | I/O — User I/O pin (bank 4) |
| Pino 102 | I/O — User I/O pin (bank 4) |
| Pino 103 | I/O — User I/O pin (bank 4) |
| Pino 104 | I/O — User I/O pin (bank 4) |
| Pino 105 | I/O — User I/O pin (bank 4) |
| Pino 106 | I/O — User I/O pin (bank 4) |
| Pino 107 | I/O — User I/O pin (bank 4) |
| Pino 108 | I/O — User I/O pin (bank 4) |
| Pino 109 | VCCIO4 — I/O bank 4 supply voltage |
| Pino 110 | GND — Ground |
| Pino 111 | I/O — User I/O pin (bank 4) |
| Pino 112 | I/O — User I/O pin (bank 4) |
| Pino 113 | I/O — User I/O pin (bank 4) |
| Pino 114 | I/O — User I/O pin (bank 4) |
| Pino 115 | I/O — User I/O pin (bank 4) |
| Pino 116 | I/O — User I/O pin (bank 4) |
| Pino 117 | I/O — User I/O pin (bank 4) |
| Pino 118 | I/O — User I/O pin (bank 4) |
| Pino 119 | I/O — User I/O pin (bank 4) |
| Pino 120 | I/O — User I/O pin (bank 4) |
| Pino 121 | I/O — User I/O pin (bank 4) |
| Pino 122 | I/O — User I/O pin (bank 4) |
| Pino 123 | I/O — User I/O pin (bank 4) |
| Pino 124 | I/O — User I/O pin (bank 4) |
| Pino 125 | I/O — User I/O pin (bank 4) |
| Pino 126 | I/O — User I/O pin (bank 4) |
| Pino 127 | TDI — JTAG Test Data In |
| Pino 128 | TMS — JTAG Test Mode Select |
| Pino 129 | TCK — JTAG Test Clock |
| Pino 130 | GND — Ground |
| Pino 131 | TRST — JTAG Test Reset |
| Pino 132 | TDO — JTAG Test Data Out |
| Pino 133 | I/O — User I/O pin (bank 1) |
| Pino 134 | I/O — User I/O pin (bank 1) |
| Pino 135 | I/O — User I/O pin (bank 1) |
| Pino 136 | I/O — User I/O pin (bank 1) |
| Pino 137 | I/O — User I/O pin (bank 1) |
| Pino 138 | I/O — User I/O pin (bank 1) |
| Pino 139 | I/O — User I/O pin (bank 1) |
| Pino 140 | I/O — User I/O pin (bank 1) |
| Pino 141 | I/O — User I/O pin (bank 1) |
| Pino 142 | I/O — User I/O pin (bank 1) |
| Pino 143 | VCCIO1 — I/O bank 1 supply voltage |
| Pino 144 | GND — Ground |
| Pino 145 | I/O — User I/O pin (bank 1) |
| Pino 146 | I/O — User I/O pin (bank 1) |
| Pino 147 | I/O — User I/O pin (bank 1) |
| Pino 148 | I/O — User I/O pin (bank 1) |
| Pino 149 | I/O — User I/O pin (bank 1) |
| Pino 150 | I/O — User I/O pin (bank 1) |
| Pino 151 | I/O — User I/O pin (bank 1) |
| Pino 152 | I/O — User I/O pin (bank 1) |
| Pino 153 | I/O — User I/O pin (bank 1) |
| Pino 154 | I/O — User I/O pin (bank 1) |
| Pino 155 | I/O — User I/O pin (bank 1) |
| Pino 156 | I/O — User I/O pin (bank 1) |
| Pino 157 | I/O — User I/O pin (bank 1) |
| Pino 158 | I/O — User I/O pin (bank 1) |
| Pino 159 | I/O — User I/O pin (bank 1) |
| Pino 160 | I/O — User I/O pin (bank 1) |
| Pino 161 | VCCINT — Core supply voltage (3.3 V) |
| Pino 162 | GND — Ground |
| Pino 163 | I/O — User I/O pin (bank 2) |
| Pino 164 | I/O — User I/O pin (bank 2) |
| Pino 165 | I/O — User I/O pin (bank 2) |
| Pino 166 | I/O — User I/O pin (bank 2) |
| Pino 167 | I/O — User I/O pin (bank 2) |
| Pino 168 | I/O — User I/O pin (bank 2) |
| Pino 169 | I/O — User I/O pin (bank 2) |
| Pino 170 | I/O — User I/O pin (bank 2) |
| Pino 171 | I/O — User I/O pin (bank 2) |
| Pino 172 | I/O — User I/O pin (bank 2) |
| Pino 173 | VCCIO2 — I/O bank 2 supply voltage |
| Pino 174 | GND — Ground |
| Pino 175 | I/O — User I/O pin (bank 2) |
| Pino 176 | I/O — User I/O pin (bank 2) |
| Pino 177 | I/O — User I/O pin (bank 2) |
| Pino 178 | I/O — User I/O pin (bank 2) |
| Pino 179 | I/O — User I/O pin (bank 2) |
| Pino 180 | I/O — User I/O pin (bank 2) |
| Pino 181 | I/O — User I/O pin (bank 2) |
| Pino 182 | I/O — User I/O pin (bank 2) |
| Pino 183 | I/O — User I/O pin (bank 2) |
| Pino 184 | I/O — User I/O pin (bank 2) |
| Pino 185 | I/O — User I/O pin (bank 2) |
| Pino 186 | I/O — User I/O pin (bank 2) |
| Pino 187 | I/O — User I/O pin (bank 2) |
| Pino 188 | I/O — User I/O pin (bank 2) |
| Pino 189 | I/O — User I/O pin (bank 2) |
| Pino 190 | I/O — User I/O pin (bank 2) |
| Pino 191 | I/O — User I/O pin (bank 2) |
| Pino 192 | I/O — User I/O pin (bank 2) |
| Pino 193 | I/O — User I/O pin (bank 2) |
| Pino 194 | I/O — User I/O pin (bank 2) |
| Pino 195 | VCCINT — Core supply voltage (3.3 V) |
| Pino 196 | GND — Ground |
| Pino 197 | I/O — User I/O pin (bank 3) |
| Pino 198 | I/O — User I/O pin (bank 3) |
| Pino 199 | I/O — User I/O pin (bank 3) |
| Pino 200 | I/O — User I/O pin (bank 3) |
| Pino 201 | I/O — User I/O pin (bank 3) |
| Pino 202 | I/O — User I/O pin (bank 3) |
| Pino 203 | I/O — User I/O pin (bank 3) |
| Pino 204 | I/O — User I/O pin (bank 3) |
| Pino 205 | I/O — User I/O pin (bank 3) |
| Pino 206 | I/O — User I/O pin (bank 3) |
| Pino 207 | I/O — User I/O pin (bank 3) |
| Pino 208 | I/O — User I/O pin (bank 3) |
Aplicações típicas
EPM3512AQI208-10N é adequado para 6 aplicaçãos: Bus Interface Bridging (PCI / VME / ISA), Address Decoding and Chip-Select Generation, Glue Logic Replacement for ASICs, State Machine and Sequencer Controllers, Legacy Industrial Control and Instrumentation, Digital Signal Conditioning and Pulse Shaping.
Bus Interface Bridging (PCI / VME / ISA)
The EPM3512AQI208-10N fits bus-bridging applications thanks to its 172 user I/Os, 10 ns propagation delay, and MultiVolt I/O supporting 3.3 V/5 V translation. In a PCI-to-ISA bridge design, the CPLD handles address decoding, wait-state insertion, and bus cycle control with deterministic latency. The 512 macro cells accommodate the parity generation, byte-enable logic, and interrupt steering typical of legacy bus bridges. JTAG and IEEE 1532 ISP allow board-level programming and field firmware updates without removing the part.
Recomendado
Address Decoding and Chip-Select Generation
The EPM3512AQI208-10N is widely used as a centralized address decoder in multiprocessor or memory-mapped systems. Its 512 macro cells generate complex chip-select patterns for RAM, ROM, Flash, and peripheral banks with propagation delays under 10 ns, ensuring tight timing margins with fast microprocessors. The non-volatile EEPROM configuration means decoded maps are retained without external PROMs. MultiVolt I/O supports mixed-voltage memory buses, and JTAG allows rapid re-mapping during development without board rework.
Recomendado
Glue Logic Replacement for ASICs
Engineers migrating away from end-of-life ASICs commonly drop in the EPM3512AQI208-10N to recover board functionality. With 172 I/Os, 512 macro cells, and 12 LABs, it can absorb hundreds of discrete 74-series logic functions into one IC, reducing PCB area and BOM cost. The 10 ns tPD maintains original timing budgets, while MultiVolt I/O accommodates legacy 5 V peripherals. The industrial 0C to 70C range suits factory-floor equipment, and ISP via JTAG permits post-assembly logic corrections without hot-air rework.
Recomendado
State Machine and Sequencer Controllers
The EPM3512AQI208-10N is well-suited to multi-state control sequencers in industrial automation and test equipment. Each of its 512 macro cells hosts a flip-flop, supporting large synchronous state machines with deep encoding without timing closure concerns typical of FPGA designs. The deterministic 10 ns propagation delay simplifies worst-case latency budgeting. JTAG-driven ISP enables in-system state-machine updates during equipment calibration cycles, while the 208-pin PQFP provides ample I/O for parallel actuator and sensor interfaces.
Recomendado
Legacy Industrial Control and Instrumentation
The EPM3512AQI208-10N's industrial 0C to 70C operating range, EEPROM-based non-volatile configuration, and proven MAX 3000A reliability make it a workhorse in factory PLCs, motor drives, and process-control instruments. Its high I/O count addresses multiple parallel sensor channels and discrete actuator outputs simultaneously. MultiVolt I/O interfaces with both 3.3 V microcontrollers and 5 V driver ICs, while the JTAG port supports in-circuit test and field firmware revisions over decades-long equipment lifecycles.
Recomendado
Digital Signal Conditioning and Pulse Shaping
The EPM3512AQI208-10N serves in pulse-shaping, debounce, Schmitt-trigger conditioning, and frequency-counting front-ends. Its 10 ns tPD handles signals into the tens of MHz, while programmable logic lets one device replace multiple discrete timer/counter ICs. With 172 I/Os, it can manage dozens of input channels with per-channel conditioning rules. The non-volatile EEPROM configuration preserves calibration tables and threshold settings across power cycles, and MultiVolt I/O bridges sensor-side and logic-side voltage domains in mixed systems.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM3512AQI208-10N — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM3512AQC208-10N | EPM3512AQI208-10 | EPM3256AQI208-10N | EPM3512AFC256-10N | EPM3512AFI256-10N |
|---|---|---|---|---|---|---|
| Package | PQFP-208 | PQFP-208 (same) | PQFP-208 (same) | PQFP-208 (same) | BGA-256 (different) | BGA-256 (different) |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Macro Cells | 512 | 512 | 512 | 256 | 512 | 512 |
| Propagation Delay | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns |
| User I/Os | 172 | 172 | 172 | 164 | 208 | 208 |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Temperature Grade | Industrial (0C to 70C) | Commercial | Industrial | Industrial | Commercial | Industrial |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Programming Interface | JTAG / ISP (IEEE 1532) | JTAG / ISP (IEEE 1532) | JTAG / ISP (IEEE 1532) | JTAG / ISP (IEEE 1532) | JTAG / ISP (IEEE 1532) | JTAG / ISP (IEEE 1532) |
| Configuration Memory | EEPROM | EEPROM | EEPROM | EEPROM | EEPROM | EEPROM |
Principais diferenciais
- Highest density in MAX 3000A family at PQFP-208 (vs EPM3256AQI208-10N)
- Industrial temperature grade for harsh environments (vs EPM3512AQC208-10N)
- PQFP-208 surface-mount compatibility (vs EPM3512AFC256-10N)
Notas de projeto
The EPM3512AQI208-10N requires separate VCCINT (3.3 V core) and VCCIOx (per-bank I/O supply) rails. Use a 0.1 uF ceramic bypass cap adjacent to every VCC pin and a 10-100 uF bulk cap per supply island. Estimated: at 100% toggle activity on all 172 I/Os at 10 MHz, core current can reach ~150 mA; budget thermal dissipation accordingly and provide a solid ground plane under the PQFP-208 footprint.
PQFP-208 has 0.5 mm pitch leads requiring careful PCB layout. Use 0.15 mm/0.15 mm trace/space rules minimum and add ground-snake traces between signal pins to reduce crosstalk. Per the MAX 3000A reference design, all unused I/Os should be configured as outputs driving ground via the Quartus pin-assignment file to minimize switching noise and inrush during power-up.
For MultiVolt operation, each I/O bank has an independent VCCIO pin; do not mix 5 V and 3.3 V on the same bank. Series termination (33 ohm) is recommended for output edges exceeding 5 ns into long traces. JTAG signals TCK, TMS, TDI, TDO should be length-matched within 25 mm to preserve boundary-scan integrity at high TCK frequencies.
Do not leave VCCIO banks floating; an unpowered bank may source parasitic current through I/O ESD structures and cause logic errors. Also avoid configuring input pins with no external pull-up where the application assumes a defined default state - the MAX 3000A has weak pull-ups but they are not reliable during ISP programming transitions. Always verify the .pof file via JTAG readout after programming.
Informações de conformidade
RoHS and lead-free status not explicitly stated in the verified web data for the EPM3512AQI208-10N; MAX 3000A era parts are often non-RoHS. AEC-Q100 not applicable as this is a CPLD logic device not intended for automotive safety.
