FDC658AP-G - 30V P-Ch MOSFET, 50mΩ, SuperSOT-6 | onsemi
부품 번호: FDC658AP-G ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $0.57 | $0.57 |
| 10 | $0.45 | $4.50 |
| 100 | $0.3 | $30.00 |
| 500 | $0.22 | $110.00 |
| 1,000 | $0.18 | $180.00 |
| 3,000 | $0.14 | $420.00 |
FDC658AP-G 개요
A P-Channel MOSFET is a field-effect transistor whose majority carriers are holes (positive charges); because the channel conducts when the gate is pulled below the source, P-Channel parts simplify high-side load switching in negative-rail systems because the load is connected to ground and the MOSFET sits on the high side, eliminating the need for a charge pump in many low-current battery designs. Within the broader taxonomy, the FDC658AP-G sits as: P-Channel MOSFET -> small-signal MOSFET -> discrete MOSFET -> discrete semiconductor -> semiconductor device, with PowerTrench referring to a proprietary trench-gate cell architecture that minimizes RDS(on) per unit area while keeping gate charge low for fast switching edges.
Key features include a logic-level VGS(th) of typically -1.9V maximum, gate charge (Qg) on the order of a few nC, fast switching, and low input capacitance. The SuperSOT-6 (TSOT-23-6) package provides a compact 2.9mm × 1.6mm footprint with a thermal pad that reduces junction-to-ambient thermal resistance to roughly 78°C/W on a 1 oz copper JEDEC test board. The -G suffix indicates a Pb-free / RoHS-compliant terminal finish suitable for lead-free reflow at 260°C peak per IPC/JEDEC J-STD-020.
Typical applications include load switching and power management in portable battery-powered devices (notebooks, tablets, smartphones), battery protection circuits, high-side OR-ing, dc-dc converters as synchronous rectifier complements, and power-muxing between adapters and batteries. The wide safety margins on VDS and the logic-level gate make it a versatile building block for hot-swap, USB load switch, and reverse-battery protection blocks.
Designers should observe the SOA boundary at high pulse currents and consider pulsed current de-rating at elevated temperatures. Because P-Channel VGS(th) becomes less negative with rising junction temperature, the device can self-enhance on a hot PCB; verify cold-start behavior at the minimum expected battery voltage. The SuperSOT-6 thermal pad must be soldered to a copper pour to meet the rated continuous drain current, and a gate series resistor of 10-100Ω is recommended to control ringing.
드롭인 대체품: FDC658AP-G — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
FDC658AP
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
FDC658APG
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
FDC610PZ
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
FDC653N
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AO3401A
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
FDC658AP-G 최대 정격 & 전기적 특성
| Polarity / Channel Type | P-Channel MOSFET |
| Process / Technology | POWERTRENCH (trench-gate) |
| Drain-Source Voltage (VDS) | -30 V |
| Gate-Source Voltage (VGS) | ±20 V (max) |
| Continuous Drain Current (ID) | -4 A (Ta) |
| Pulsed Drain Current (IDM) | -10 A (pulsed) |
| Static Drain-Source On-Resistance (RDS(on)) | 50 mΩ (max) @ VGS = -10 V |
| Gate Threshold Voltage (VGS(th)) | -1.9 V (max), logic-level |
| Power Dissipation (PD) | 1.6 W (Ta) |
| 동작 접합 온도 | -55 C to +150 C |
| 패키지 | SuperSOT-6 (TSOT-23-6), 6-lead |
| 실장 유형 | Surface Mount |
| MSL 레벨 | 1 (per JEDEC J-STD-020) |
| Lead-Free / RoHS | Yes (Pb-free, RoHS compliant, -G suffix) |
| Reflow Profile | Lead-free, 260 C peak per IPC/JEDEC J-STD-020 |
| Recommended Gate Drive | 1.8 V / 3.3 V / 5 V logic (logic-level) |
FDC658AP-G 핀 구성
| 핀 1 | Source — Source (connected to V+ for high-side P-Ch switching) |
| 핀 2 | Source — Source (connected to V+ for high-side P-Ch switching) |
| 핀 3 | Gate — Logic-level gate drive input |
| 핀 4 | Drain — Drain (connected to load) |
| 핀 5 | Drain — Drain (connected to load) |
| 핀 6 | Drain — Drain (connected to load) |
안전 동작 영역 (P-Channel, Ta = 25 C)
일반적인 애플리케이션
FDC658AP-G 적합 용도: 6 애플리케이션s: USB VBUS Load Switch, Battery Protection / Reverse Polarity, Notebook / Tablet Power Path Management, DC-DC Converter Synchronous Rectifier, Hot-Swap / Inrush Limiting, Portable / Wearable Power Management.
USB VBUS Load Switch
The FDC658AP-G is widely used for USB VBUS load switching in phones, tablets, and notebooks. Its logic-level VGS(th) of -1.9V max allows direct drive from a 3.3V GPIO without a charge pump, while its 30V VDS easily covers 5V VBUS plus hot-plug transients. At 2A continuous load the on-resistance of 50 mΩ generates only ~100 mV drop, well within USB VBUS tolerance. A 100 kΩ pull-up on the gate to VBUS keeps the switch off during reset, and a small TVS on VBUS protects against ESD and surge. Compared to an N-Channel high-side switch, no bootstrap or charge-pump is needed, simplifying the BOM. The SuperSOT-6 thermal pad must be soldered to a copper pour to sustain the rated 1.6W dissipation under worst-case load.
추천
Battery Protection / Reverse Polarity
In single-cell Li-ion battery packs the FDC658AP-G serves as a reverse-polarity and over-discharge switch. Because it is a P-Channel MOSFET, the source ties to V+ and the drain to the load, so if the battery is installed backwards the body diode is reverse-biased and the load is protected. RDS(on) of 50 mΩ at 4A produces only ~200 mV drop, preserving battery runtime versus a Schottky diode solution. The -G suffix confirms Pb-free and RoHS compliance for consumer and wearable applications. Note that P-Channel VGS(th) becomes less negative with rising junction temperature, so designers must verify cold-start at minimum battery voltage (typically 3.0V for Li-ion cut-off).
추천
Notebook / Tablet Power Path Management
In notebook and tablet power path management (PPM) blocks the FDC658AP-G implements the high-side switch between an AC adapter and a battery. The MOSFET selects which source feeds the system load while preventing cross-conduction. Its logic-level drive lets the embedded controller (EC) GPIO control switching directly, while its low 50 mΩ on-resistance minimizes conduction losses during high-current bursts. The 30V VDS rating tolerates the inductive kick from upstream chokes during hot-swap events. The SuperSOT-6 footprint saves PCB area versus larger DPAK alternatives. onsemi application notes also reference this part in USB-PD and barrel-jacket muxing reference designs.
추천
DC-DC Converter Synchronous Rectifier
The FDC658AP-G can serve as the synchronous rectifier in low-power buck or boost converters up to ~3A continuous. Its low gate charge and fast switching edge minimize switching losses at 500 kHz to 1 MHz typical converter frequencies. P-Channel synchronous rectifiers simplify the gate-drive transformer or bootstrap network because the gate reference is the switching node, and they avoid the body-diode conduction issue common with N-Channel sync FETs. The 30V VDS rating supports 12V input rails. Use a small gate resistor (10-47 Ω) to control ringing on the gate, especially in circuits with long gate traces.
추천
Hot-Swap / Inrush Limiting
In low-power hot-swap applications (e.g. plug-in cards, eMMC, peripherals) the FDC658AP-G functions as a soft-start inrush limiter. A gate RC network (Rgate ≈ 100 kΩ, Css ≈ 100 nF) programs a controlled turn-on, limiting the inrush current that would otherwise stress the upstream supply. Once fully enhanced, the 50 mΩ RDS(on) contributes negligible loss. The 30V VDS covers 5V and 12V rails plus transient overshoot. P-Channel topology avoids the charge pump required by an N-Channel equivalent. onsemi recommends observing the SOA curve during the soft-start interval to ensure the device stays within thermal limits at peak inrush.
추천
Portable / Wearable Power Management
In portable and wearable designs (smart watches, fitness bands, BLE earbuds) the FDC658AP-G enables sub-1.6W load switching with minimal quiescent current since a MOSFET conducts only when on. Its SuperSOT-6 2.9mm × 1.6mm footprint fits the tight PCB constraints of wearables, and the 50 mΩ on-resistance keeps conduction losses low enough to preserve battery life. The 30V VDS provides ample margin for inductive spikes in small buck/boost converters. Pb-free and RoHS compliance (the -G suffix) is mandatory for consumer electronics. Use a 100 kΩ gate pull-up resistor to ensure defined off-state during MCU reset or brown-out.
추천
추천 제품 요약
엔지니어링 참조 데이터: FDC658AP-G — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | FDC658AP | FDC658APG | FDC610PZ | FDC653N | AO3401A |
|---|---|---|---|---|---|---|
| Brand | onsemi | onsemi | onsemi | onsemi | onsemi | Alpha & Omega Semiconductor |
| Package | SuperSOT-6 (TSOT-23-6) | SuperSOT-6 (TSOT-23-6) | SuperSOT-6 (TSOT-23-6) | SuperSOT-6 (TSOT-23-6) | SuperSOT-6 (TSOT-23-6) | SOT-23-6 |
| Polarity | P-Channel | P-Channel | P-Channel | N-Channel | N-Channel | P-Channel |
| VDS (max) | -30 V | -30 V | -30 V | 30 V | 30 V | -30 V |
| VGS(th) max | -1.9 V (logic-level) | -1.9 V | -1.9 V | Logic-level | Logic-level | -1.5 V (logic-level) |
| Power Dissipation (Ta) | 1.6 W | 1.6 W | 1.6 W | 1.6 W | 1.6 W | 1.4 W |
| RoHS / Pb-Free | Yes | Depends on suffix | Yes | Yes | Yes | Yes |
주요 차별점
- Logic-level gate with 1.9V max VGS(th) (vs Standard -10V gate-drive P-Channel MOSFETs)
- Compact SuperSOT-6 footprint at 2.9mm × 1.6mm (vs Larger DPAK or SO-8 P-Channel MOSFETs)
- Pb-free / RoHS terminal finish (-G suffix) (vs Legacy FDC658AP (non-Pb-free finish))
설계 노트
Solder the SuperSOT-6 thermal pad (electrically the Drain) to a copper pour of at least 1 square inch of 1 oz copper to sustain the rated 1.6W continuous dissipation. At Ta = 25 C with θJA ≈ 78 C/W the junction reaches 150 C at exactly 1.6W - the absolute maximum. In practice keep dissipation below ~1W by derating continuous current to ~3A at high ambient temperatures or by improving PCB copper area.
Keep the gate trace short and place the gate series resistor (10-100 Ω) close to the IC gate pin to suppress ringing from the gate-source inductance. Place a 100 kΩ gate pull-up resistor to V+ so the MOSFET is OFF during MCU reset, brown-out, or firmware hang. For high-side switching, route V+ directly to the source pins (1, 2) on a wide trace to minimize parasitic inductance in the high-current path.
Do not exceed |VGS| = 20 V (absolute maximum). Driving the gate to 5V logic levels is fine; driving to 12V above V+ is safe; driving to 24V will damage the gate oxide. Also note that the body diode (drain-to-source, anode on drain) is forward-biased when V+ is shorted to ground (reverse-battery scenario) - if reverse-battery protection is required, add an external Schottky or fuse. Avoid continuous operation near the SOA boundary at elevated temperature; refer to the SOA chart in the onsemi datasheet.
P-Channel VGS(th) becomes less negative with rising temperature, meaning a hot MOSFET can self-enhance near the cold-start threshold. If the design depends on the MOSFET staying OFF at a minimum gate-drive level (e.g. MCU pin in high-impedance state), add a gate pull-down to ground (10-100 kΩ) instead of relying on VGS(th) margin. For switching-edge rates above 10V/ns, add a small ferrite bead or RC snubber across the drain-source to reduce ringing and radiated EMI.
규정 준수 정보
Pb-free / RoHS compliant per -G suffix and onsemi product page. Consumer / industrial grade; not AEC-Q100 qualified (use automotive-grade onsemi parts for automotive).
