10CL055YU484C6G vs 10CL055YU484I7G Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci 10CL055YU484C6G disebabkan oleh Altera dan 10CL055YU484I7G disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr 10CL055YU484C6G 10CL055YU484I7G
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif Aktif
Family Cyclone 10 LP Cyclone 10 LP
Logic Elements (LE) 55,856 —
Embedded Memory Bits 2,396,160 bits (approximately 2.5 Mb) 2,396,160 bits
Maximum User I/Os 321 321
Embedded 18x18 Multipliers 156 —
PLLs 4 4
Global Clocks 20 —
Core Voltage 1.0 V (typical) —
I/O Voltage Standards LVDS, LVTTL, LVCMOS, SSTL, HSTL (1.2 V to 3.3 V) —
Speed Grade 6 (commercial, slowest in family) -7 (I7, industrial)
Kemasan 484-pin UBGA (19 mm x 19 mm) 484-ball UBGA (Ultra FineLine BGA), 19 mm x 19 mm
Process Technology TSMC 60 nm low-power 60 nm low-power CMOS
Suhu Operasi 0 C to +85 C (commercial, C suffix) —
Jenis Pemasangan Surface Mount —
Aras MSL [DATA_NEEDED: MSL level per JEDEC J-STD-020] 3 (per JEDEC J-STD-020)
Status RoHS Compliant Compliant
Lead-Free / Halogen-Free Yes / [DATA_NEEDED: halogen-free status] —
Configuration Modes Active Serial (AS), Passive Serial (PS), JTAG JTAG, AS, PS, FPP
Transceivers None (Cyclone 10 LP family does not include SERDES) —
Hard Memory Controller Yes (DDR/DDR2/DDR3/LPDDR2 via soft IP) —
Logic Elements — 55,856
M9K Memory Blocks — 260
DSP Blocks (18x18 multipliers) — 156
Global Clock Networks — 20
Suhu Hubungan Operasi — -40C to +100C
Core Voltage (VCCINT) — 1.0V (typical), 1.1V nominal
I/O Voltage (VCCIO) — 1.2V to 3.3V (bank-dependent)
LVDS Data Rate — Up to 875 Mbps per channel

Laporan Datasheet & Sumber

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